| commit | ca8b387803072a16baf6d8090591b10bfdf4e253 | |
| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
| Wed, 10 Jul 2013 10:09:47 +0000 (10 12:09 +0200) | ||
| committer | Vinod Koul <vinod.koul@intel.com> | |
| Tue, 27 Aug 2013 08:54:07 +0000 (27 14:24 +0530) | ||
| tree | 369a7e9cc93d4ff6d7e9445d57ef933a107eb75f | treesnapshot (tar.gz zip) |
| parent | 115357e9774ff8d70a84d3c31f271209913637b0 | commitdiff |
DMA: shdma: support the new CHCLR register layout
On newer r-car SoCs the CHCLR register only contains one bit per channel,
to which a 1 has to be written to reset the channel. Older SoC versions had
one CHCLR register per channel, to which a 0 must be written to reset the
channel and clear its buffers. This patch adds support for the newer
layout.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
On newer r-car SoCs the CHCLR register only contains one bit per channel,
to which a 1 has to be written to reset the channel. Older SoC versions had
one CHCLR register per channel, to which a 0 must be written to reset the
channel and clear its buffers. This patch adds support for the newer
layout.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| drivers/dma/sh/shdma.c | diffblobblamehistory | |
| include/linux/sh_dma.h | diffblobblamehistory |