| commit | bb034cb5eb7fa6596c40d405e31cef02de21ad30 | |
| author | Thierry Reding <thierry.reding@gmail.com> | |
| Fri, 9 Aug 2013 14:49:28 +0000 (9 16:49 +0200) | ||
| committer | Stephen Warren <swarren@nvidia.com> | |
| Mon, 12 Aug 2013 20:20:22 +0000 (12 14:20 -0600) | ||
| tree | 54ba1bdd2556fd57ba703068bfc0265a36b39608 | treesnapshot (tar.gz zip) |
| parent | 89e7ada41674197387fa67ea0a853f3651b4e375 | commitdiff |
ARM: tegra: Enable PCIe controller on Beaver
PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
| arch/arm/boot/dts/tegra30-beaver.dts | diffblobblamehistory |