| commit | 8bc218410d6c2b22a7581fac6f3dc2ac1f8fc99f | |
| author | Raphael Assenat <raph@8d.com> | |
| Tue, 3 Oct 2006 08:15:03 +0000 (3 01:15 -0700) | ||
| committer | Linus Torvalds <torvalds@g5.osdl.org> | |
| Tue, 3 Oct 2006 15:04:12 +0000 (3 08:04 -0700) | ||
| tree | e4b0ef3693052742df0233ab9c3a706382307ee3 | treesnapshot (tar.gz zip) |
| parent | 9c5b39e0bcb407a95716de4650a2d1e6064baffa | commitdiff |
[PATCH] mbxfb: Fix a chip bug? resulting in wrong pixclock
This is a workaround for what I think is a bug in the 2700G chip.
The PLL output frequency is adustable using 3 values (M, N and P. See code
for formula). The N value range is documented to be 1 to 7 but when it is set
to 1, the output frequency is lower than it should be (divided by 2), giving
unexpected results such as no sync on a CRT display.
This patch prevents N=1 when searching for the best value for the requested
pixclock.
Signed-off-by: Raphael Assenat <raph@8d.com>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This is a workaround for what I think is a bug in the 2700G chip.
The PLL output frequency is adustable using 3 values (M, N and P. See code
for formula). The N value range is documented to be 1 to 7 but when it is set
to 1, the output frequency is lower than it should be (divided by 2), giving
unexpected results such as no sync on a CRT display.
This patch prevents N=1 when searching for the best value for the requested
pixclock.
Signed-off-by: Raphael Assenat <raph@8d.com>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| drivers/video/mbx/mbxfb.c | diffblobblamehistory |