| commit | 8affaf5c7698c627b133bfcafd9869ef17faff31 | |
| author | Jingoo Han <jg1.han@samsung.com> | |
| Mon, 16 Apr 2012 00:33:12 +0000 (16 09:33 +0900) | ||
| committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | |
| Mon, 16 Apr 2012 04:19:00 +0000 (16 04:19 +0000) | ||
| tree | b8bb79b3f8709ec1fb1d99e100c22711a72ffd23 | treesnapshot (tar.gz zip) |
| parent | 8f802da33a842bc9e511d2a9c8259fbee8a6d17e | commitdiff |
video: exynos_dp: add analog and pll control setting
This patch adds analog and pll control setting. This control setting
is used for DP TX PHY block to set the values as below. It is beneficial
to improve analog characteristics.
- TX terminal registor is 50 Ohm.
- Reference clock of PHY is 24 MHz.
- Power source for TX digital logic is 1.0625 V.
- Power source for internal clock driver is 1.0625 V.
- PLL VCO range setting is 600 uA.
- Power down ring osc is turned off.
- AUX terminal resistor is 50 Ohm.
- AUX channel current is 8 mA and multiplied by 2.
- TX channel output amplitude is 400 mV.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This patch adds analog and pll control setting. This control setting
is used for DP TX PHY block to set the values as below. It is beneficial
to improve analog characteristics.
- TX terminal registor is 50 Ohm.
- Reference clock of PHY is 24 MHz.
- Power source for TX digital logic is 1.0625 V.
- Power source for internal clock driver is 1.0625 V.
- PLL VCO range setting is 600 uA.
- Power down ring osc is turned off.
- AUX terminal resistor is 50 Ohm.
- AUX channel current is 8 mA and multiplied by 2.
- TX channel output amplitude is 400 mV.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
| drivers/video/exynos/exynos_dp_core.h | diffblobblamehistory | |
| drivers/video/exynos/exynos_dp_reg.c | diffblobblamehistory | |
| drivers/video/exynos/exynos_dp_reg.h | diffblobblamehistory |