2 * Device Tree Source for AM33XX SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
14 compatible = "ti,am33xx";
27 compatible = "arm,cortex-a8";
30 * To consider voltage drop between PMIC and SoC,
31 * tolerance value is reduced to 2% from 4% and
32 * voltage value is increased as a precaution.
41 voltage-tolerance = <2>; /* 2 percentage */
42 clock-latency = <300000>; /* From omap-cpufreq driver */
47 * The soc node represents the soc top level view. It is uses for IPs
48 * that are not memory mapped in the MPU view or for the MPU itself.
51 compatible = "ti,omap-infra";
53 compatible = "ti,omap3-mpu";
59 * XXX: Use a flat representation of the AM33XX interconnect.
60 * The real AM33XX interconnect network is quite complex.Since
61 * that will not bring real advantage to represent that in DT
62 * for the moment, just use a fake OCP bus entry to represent
63 * the whole bus hierarchy.
66 compatible = "simple-bus";
70 ti,hwmods = "l3_main";
72 intc: interrupt-controller@48200000 {
73 compatible = "ti,omap2-intc";
75 #interrupt-cells = <1>;
77 reg = <0x48200000 0x1000>;
80 gpio1: gpio@44e07000 {
81 compatible = "ti,omap4-gpio";
86 #interrupt-cells = <1>;
87 reg = <0x44e07000 0x1000>;
88 interrupt-parent = <&intc>;
92 gpio2: gpio@4804c000 {
93 compatible = "ti,omap4-gpio";
98 #interrupt-cells = <1>;
99 reg = <0x4804c000 0x1000>;
100 interrupt-parent = <&intc>;
104 gpio3: gpio@481ac000 {
105 compatible = "ti,omap4-gpio";
109 interrupt-controller;
110 #interrupt-cells = <1>;
111 reg = <0x481ac000 0x1000>;
112 interrupt-parent = <&intc>;
116 gpio4: gpio@481ae000 {
117 compatible = "ti,omap4-gpio";
121 interrupt-controller;
122 #interrupt-cells = <1>;
123 reg = <0x481ae000 0x1000>;
124 interrupt-parent = <&intc>;
128 uart1: serial@44e09000 {
129 compatible = "ti,omap3-uart";
131 clock-frequency = <48000000>;
132 reg = <0x44e09000 0x2000>;
133 interrupt-parent = <&intc>;
138 uart2: serial@48022000 {
139 compatible = "ti,omap3-uart";
141 clock-frequency = <48000000>;
142 reg = <0x48022000 0x2000>;
143 interrupt-parent = <&intc>;
148 uart3: serial@48024000 {
149 compatible = "ti,omap3-uart";
151 clock-frequency = <48000000>;
152 reg = <0x48024000 0x2000>;
153 interrupt-parent = <&intc>;
158 uart4: serial@481a6000 {
159 compatible = "ti,omap3-uart";
161 clock-frequency = <48000000>;
162 reg = <0x481a6000 0x2000>;
163 interrupt-parent = <&intc>;
168 uart5: serial@481a8000 {
169 compatible = "ti,omap3-uart";
171 clock-frequency = <48000000>;
172 reg = <0x481a8000 0x2000>;
173 interrupt-parent = <&intc>;
178 uart6: serial@481aa000 {
179 compatible = "ti,omap3-uart";
181 clock-frequency = <48000000>;
182 reg = <0x481aa000 0x2000>;
183 interrupt-parent = <&intc>;
189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
193 reg = <0x44e0b000 0x1000>;
194 interrupt-parent = <&intc>;
200 compatible = "ti,omap4-i2c";
201 #address-cells = <1>;
204 reg = <0x4802a000 0x1000>;
205 interrupt-parent = <&intc>;
211 compatible = "ti,omap4-i2c";
212 #address-cells = <1>;
215 reg = <0x4819c000 0x1000>;
216 interrupt-parent = <&intc>;
222 compatible = "ti,omap3-wdt";
223 ti,hwmods = "wd_timer2";
224 reg = <0x44e35000 0x1000>;
225 interrupt-parent = <&intc>;