2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
16 /memreserve/ 0x9d000000 0x03000000;
18 /include/ "skeleton.dtsi"
21 compatible = "ti,omap5";
22 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a15";
37 compatible = "arm,armv7-timer";
38 /* 14th PPI IRQ, active low level-sensitive */
39 interrupts = <1 14 0x308>;
40 clock-frequency = <6144000>;
44 compatible = "arm,cortex-a15";
46 compatible = "arm,armv7-timer";
47 /* 14th PPI IRQ, active low level-sensitive */
48 interrupts = <1 14 0x308>;
49 clock-frequency = <6144000>;
55 * The soc node represents the soc top level view. It is uses for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
59 compatible = "ti,omap-infra";
61 compatible = "ti,omap5-mpu";
67 * XXX: Use a flat representation of the OMAP3 interconnect.
68 * The real OMAP interconnect network is quite complex.
69 * Since that will not bring real advantage to represent that in DT for
70 * the moment, just use a fake OCP bus entry to represent the whole bus
74 compatible = "ti,omap4-l3-noc", "simple-bus";
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
80 omap5_pmx_core: pinmux@4a002840 {
81 compatible = "ti,omap4-padconf", "pinctrl-single";
82 reg = <0x4a002840 0x01b6>;
85 pinctrl-single,register-width = <16>;
86 pinctrl-single,function-mask = <0x7fff>;
88 omap5_pmx_wkup: pinmux@4ae0c840 {
89 compatible = "ti,omap4-padconf", "pinctrl-single";
90 reg = <0x4ae0c840 0x0038>;
93 pinctrl-single,register-width = <16>;
94 pinctrl-single,function-mask = <0x7fff>;
97 gic: interrupt-controller@48211000 {
98 compatible = "arm,cortex-a15-gic";
100 #interrupt-cells = <3>;
101 reg = <0x48211000 0x1000>,
105 gpio1: gpio@4ae10000 {
106 compatible = "ti,omap4-gpio";
107 reg = <0x4ae10000 0x200>;
108 interrupts = <0 29 0x4>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
116 gpio2: gpio@48055000 {
117 compatible = "ti,omap4-gpio";
118 reg = <0x48055000 0x200>;
119 interrupts = <0 30 0x4>;
123 interrupt-controller;
124 #interrupt-cells = <1>;
127 gpio3: gpio@48057000 {
128 compatible = "ti,omap4-gpio";
129 reg = <0x48057000 0x200>;
130 interrupts = <0 31 0x4>;
134 interrupt-controller;
135 #interrupt-cells = <1>;
138 gpio4: gpio@48059000 {
139 compatible = "ti,omap4-gpio";
140 reg = <0x48059000 0x200>;
141 interrupts = <0 32 0x4>;
145 interrupt-controller;
146 #interrupt-cells = <1>;
149 gpio5: gpio@4805b000 {
150 compatible = "ti,omap4-gpio";
151 reg = <0x4805b000 0x200>;
152 interrupts = <0 33 0x4>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
160 gpio6: gpio@4805d000 {
161 compatible = "ti,omap4-gpio";
162 reg = <0x4805d000 0x200>;
163 interrupts = <0 34 0x4>;
167 interrupt-controller;
168 #interrupt-cells = <1>;
171 gpio7: gpio@48051000 {
172 compatible = "ti,omap4-gpio";
173 reg = <0x48051000 0x200>;
174 interrupts = <0 35 0x4>;
178 interrupt-controller;
179 #interrupt-cells = <1>;
182 gpio8: gpio@48053000 {
183 compatible = "ti,omap4-gpio";
184 reg = <0x48053000 0x200>;
185 interrupts = <0 121 0x4>;
189 interrupt-controller;
190 #interrupt-cells = <1>;
194 compatible = "ti,omap4-i2c";
195 reg = <0x48070000 0x100>;
196 interrupts = <0 56 0x4>;
197 #address-cells = <1>;
203 compatible = "ti,omap4-i2c";
204 reg = <0x48072000 0x100>;
205 interrupts = <0 57 0x4>;
206 #address-cells = <1>;
212 compatible = "ti,omap4-i2c";
213 reg = <0x48060000 0x100>;
214 interrupts = <0 61 0x4>;
215 #address-cells = <1>;
221 compatible = "ti,omap4-i2c";
222 reg = <0x4807a000 0x100>;
223 interrupts = <0 62 0x4>;
224 #address-cells = <1>;
230 compatible = "ti,omap4-i2c";
231 reg = <0x4807c000 0x100>;
232 interrupts = <0 60 0x4>;
233 #address-cells = <1>;
238 uart1: serial@4806a000 {
239 compatible = "ti,omap4-uart";
241 clock-frequency = <48000000>;
244 uart2: serial@4806c000 {
245 compatible = "ti,omap4-uart";
247 clock-frequency = <48000000>;
250 uart3: serial@48020000 {
251 compatible = "ti,omap4-uart";
253 clock-frequency = <48000000>;
256 uart4: serial@4806e000 {
257 compatible = "ti,omap4-uart";
259 clock-frequency = <48000000>;
262 uart5: serial@48066000 {
263 compatible = "ti,omap5-uart";
265 clock-frequency = <48000000>;
268 uart6: serial@48068000 {
269 compatible = "ti,omap6-uart";
271 clock-frequency = <48000000>;
275 compatible = "ti,omap4-hsmmc";
278 ti,needs-special-reset;
282 compatible = "ti,omap4-hsmmc";
284 ti,needs-special-reset;
288 compatible = "ti,omap4-hsmmc";
290 ti,needs-special-reset;
294 compatible = "ti,omap4-hsmmc";
296 ti,needs-special-reset;
300 compatible = "ti,omap4-hsmmc";
302 ti,needs-special-reset;
305 keypad: keypad@4ae1c000 {
306 compatible = "ti,omap4-keypad";
310 mcpdm: mcpdm@40132000 {
311 compatible = "ti,omap4-mcpdm";
312 reg = <0x40132000 0x7f>, /* MPU private access */
313 <0x49032000 0x7f>; /* L3 Interconnect */
314 reg-names = "mpu", "dma";
315 interrupts = <0 112 0x4>;
319 dmic: dmic@4012e000 {
320 compatible = "ti,omap4-dmic";
321 reg = <0x4012e000 0x7f>, /* MPU private access */
322 <0x4902e000 0x7f>; /* L3 Interconnect */
323 reg-names = "mpu", "dma";
324 interrupts = <0 114 0x4>;
328 mcbsp1: mcbsp@40122000 {
329 compatible = "ti,omap4-mcbsp";
330 reg = <0x40122000 0xff>, /* MPU private access */
331 <0x49022000 0xff>; /* L3 Interconnect */
332 reg-names = "mpu", "dma";
333 interrupts = <0 17 0x4>;
334 interrupt-names = "common";
335 ti,buffer-size = <128>;
336 ti,hwmods = "mcbsp1";
339 mcbsp2: mcbsp@40124000 {
340 compatible = "ti,omap4-mcbsp";
341 reg = <0x40124000 0xff>, /* MPU private access */
342 <0x49024000 0xff>; /* L3 Interconnect */
343 reg-names = "mpu", "dma";
344 interrupts = <0 22 0x4>;
345 interrupt-names = "common";
346 ti,buffer-size = <128>;
347 ti,hwmods = "mcbsp2";
350 mcbsp3: mcbsp@40126000 {
351 compatible = "ti,omap4-mcbsp";
352 reg = <0x40126000 0xff>, /* MPU private access */
353 <0x49026000 0xff>; /* L3 Interconnect */
354 reg-names = "mpu", "dma";
355 interrupts = <0 23 0x4>;
356 interrupt-names = "common";
357 ti,buffer-size = <128>;
358 ti,hwmods = "mcbsp3";