4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also include/asm-ia64/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/smp.h>
90 #include <linux/string.h>
91 #include <linux/bootmem.h>
93 #include <asm/delay.h>
94 #include <asm/hw_irq.h>
96 #include <asm/iosapic.h>
97 #include <asm/machvec.h>
98 #include <asm/processor.h>
99 #include <asm/ptrace.h>
100 #include <asm/system.h>
102 #undef DEBUG_INTERRUPT_ROUTING
104 #ifdef DEBUG_INTERRUPT_ROUTING
105 #define DBG(fmt...) printk(fmt)
110 #define NR_PREALLOCATE_RTE_ENTRIES \
111 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
112 #define RTE_PREALLOCATED (1)
114 static DEFINE_SPINLOCK(iosapic_lock
);
117 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
120 static struct iosapic
{
121 char __iomem
*addr
; /* base address of IOSAPIC */
122 unsigned int gsi_base
; /* GSI base */
123 unsigned short num_rte
; /* # of RTEs on this IOSAPIC */
124 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
126 unsigned short node
; /* numa node association via pxm */
128 spinlock_t lock
; /* lock for indirect reg access */
129 } iosapic_lists
[NR_IOSAPICS
];
131 struct iosapic_rte_info
{
132 struct list_head rte_list
; /* RTEs sharing the same vector */
133 char rte_index
; /* IOSAPIC RTE index */
134 int refcnt
; /* reference counter */
135 unsigned int flags
; /* flags */
136 struct iosapic
*iosapic
;
137 } ____cacheline_aligned
;
139 static struct iosapic_intr_info
{
140 struct list_head rtes
; /* RTEs using this vector (empty =>
141 * not an IOSAPIC interrupt) */
142 int count
; /* # of RTEs that shares this vector */
143 u32 low32
; /* current value of low word of
144 * Redirection table entry */
145 unsigned int dest
; /* destination CPU physical ID */
146 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
147 unsigned char polarity
: 1; /* interrupt polarity
149 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
150 } iosapic_intr_info
[IA64_NUM_VECTORS
];
152 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
154 static int iosapic_kmalloc_ok
;
155 static LIST_HEAD(free_rte_list
);
158 iosapic_write(struct iosapic
*iosapic
, unsigned int reg
, u32 val
)
162 spin_lock_irqsave(&iosapic
->lock
, flags
);
163 __iosapic_write(iosapic
->addr
, reg
, val
);
164 spin_unlock_irqrestore(&iosapic
->lock
, flags
);
168 * Find an IOSAPIC associated with a GSI
171 find_iosapic (unsigned int gsi
)
175 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
176 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) <
177 iosapic_lists
[i
].num_rte
)
185 _gsi_to_vector (unsigned int gsi
)
187 struct iosapic_intr_info
*info
;
188 struct iosapic_rte_info
*rte
;
190 for (info
= iosapic_intr_info
; info
<
191 iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
)
192 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
193 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
194 return info
- iosapic_intr_info
;
199 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
200 * entry exists, return -1.
203 gsi_to_vector (unsigned int gsi
)
205 return _gsi_to_vector(gsi
);
209 gsi_to_irq (unsigned int gsi
)
214 * XXX fix me: this assumes an identity mapping between IA-64 vector
215 * and Linux irq numbers...
217 spin_lock_irqsave(&iosapic_lock
, flags
);
218 irq
= _gsi_to_vector(gsi
);
219 spin_unlock_irqrestore(&iosapic_lock
, flags
);
224 static struct iosapic_rte_info
*gsi_vector_to_rte(unsigned int gsi
,
227 struct iosapic_rte_info
*rte
;
229 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
230 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
236 set_rte (unsigned int gsi
, unsigned int vector
, unsigned int dest
, int mask
)
238 unsigned long pol
, trigger
, dmode
;
242 struct iosapic_rte_info
*rte
;
244 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
246 rte
= gsi_vector_to_rte(gsi
, vector
);
248 return; /* not an IOSAPIC interrupt */
250 rte_index
= rte
->rte_index
;
251 pol
= iosapic_intr_info
[vector
].polarity
;
252 trigger
= iosapic_intr_info
[vector
].trigger
;
253 dmode
= iosapic_intr_info
[vector
].dmode
;
255 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
261 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
262 if (irq_to_vector(irq
) == vector
) {
263 set_irq_affinity_info(irq
,
264 (int)(dest
& 0xffff),
271 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
272 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
273 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
274 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
277 /* dest contains both id and eid */
278 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
280 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
281 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
282 iosapic_intr_info
[vector
].low32
= low32
;
283 iosapic_intr_info
[vector
].dest
= dest
;
287 nop (unsigned int irq
)
295 kexec_disable_iosapic(void)
297 struct iosapic_intr_info
*info
;
298 struct iosapic_rte_info
*rte
;
300 for (info
= iosapic_intr_info
; info
<
301 iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
, ++vec
) {
302 list_for_each_entry(rte
, &info
->rtes
,
304 iosapic_write(rte
->iosapic
,
305 IOSAPIC_RTE_LOW(rte
->rte_index
),
307 iosapic_eoi(rte
->iosapic
->addr
, vec
);
314 mask_irq (unsigned int irq
)
318 ia64_vector vec
= irq_to_vector(irq
);
319 struct iosapic_rte_info
*rte
;
321 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
322 return; /* not an IOSAPIC interrupt! */
324 /* set only the mask bit */
325 low32
= iosapic_intr_info
[vec
].low32
|= IOSAPIC_MASK
;
326 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
327 rte_index
= rte
->rte_index
;
328 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
333 unmask_irq (unsigned int irq
)
337 ia64_vector vec
= irq_to_vector(irq
);
338 struct iosapic_rte_info
*rte
;
340 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
341 return; /* not an IOSAPIC interrupt! */
343 low32
= iosapic_intr_info
[vec
].low32
&= ~IOSAPIC_MASK
;
344 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
345 rte_index
= rte
->rte_index
;
346 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
352 iosapic_set_affinity (unsigned int irq
, cpumask_t mask
)
357 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
359 struct iosapic_rte_info
*rte
;
360 struct iosapic
*iosapic
;
362 irq
&= (~IA64_IRQ_REDIRECTED
);
363 vec
= irq_to_vector(irq
);
365 if (cpus_empty(mask
))
368 dest
= cpu_physical_id(first_cpu(mask
));
370 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
371 return; /* not an IOSAPIC interrupt */
373 set_irq_affinity_info(irq
, dest
, redir
);
375 /* dest contains both id and eid */
376 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
378 low32
= iosapic_intr_info
[vec
].low32
& ~(7 << IOSAPIC_DELIVERY_SHIFT
);
380 /* change delivery mode to lowest priority */
381 low32
|= (IOSAPIC_LOWEST_PRIORITY
<< IOSAPIC_DELIVERY_SHIFT
);
383 /* change delivery mode to fixed */
384 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
386 iosapic_intr_info
[vec
].low32
= low32
;
387 iosapic_intr_info
[vec
].dest
= dest
;
388 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
389 iosapic
= rte
->iosapic
;
390 rte_index
= rte
->rte_index
;
391 iosapic_write(iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
392 iosapic_write(iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
398 * Handlers for level-triggered interrupts.
402 iosapic_startup_level_irq (unsigned int irq
)
409 iosapic_end_level_irq (unsigned int irq
)
411 ia64_vector vec
= irq_to_vector(irq
);
412 struct iosapic_rte_info
*rte
;
414 move_native_irq(irq
);
415 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
416 iosapic_eoi(rte
->iosapic
->addr
, vec
);
419 #define iosapic_shutdown_level_irq mask_irq
420 #define iosapic_enable_level_irq unmask_irq
421 #define iosapic_disable_level_irq mask_irq
422 #define iosapic_ack_level_irq nop
424 struct irq_chip irq_type_iosapic_level
= {
425 .name
= "IO-SAPIC-level",
426 .startup
= iosapic_startup_level_irq
,
427 .shutdown
= iosapic_shutdown_level_irq
,
428 .enable
= iosapic_enable_level_irq
,
429 .disable
= iosapic_disable_level_irq
,
430 .ack
= iosapic_ack_level_irq
,
431 .end
= iosapic_end_level_irq
,
433 .unmask
= unmask_irq
,
434 .set_affinity
= iosapic_set_affinity
438 * Handlers for edge-triggered interrupts.
442 iosapic_startup_edge_irq (unsigned int irq
)
446 * IOSAPIC simply drops interrupts pended while the
447 * corresponding pin was masked, so we can't know if an
448 * interrupt is pending already. Let's hope not...
454 iosapic_ack_edge_irq (unsigned int irq
)
456 irq_desc_t
*idesc
= irq_desc
+ irq
;
458 move_native_irq(irq
);
460 * Once we have recorded IRQ_PENDING already, we can mask the
461 * interrupt for real. This prevents IRQ storms from unhandled
464 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) ==
465 (IRQ_PENDING
|IRQ_DISABLED
))
469 #define iosapic_enable_edge_irq unmask_irq
470 #define iosapic_disable_edge_irq nop
471 #define iosapic_end_edge_irq nop
473 struct irq_chip irq_type_iosapic_edge
= {
474 .name
= "IO-SAPIC-edge",
475 .startup
= iosapic_startup_edge_irq
,
476 .shutdown
= iosapic_disable_edge_irq
,
477 .enable
= iosapic_enable_edge_irq
,
478 .disable
= iosapic_disable_edge_irq
,
479 .ack
= iosapic_ack_edge_irq
,
480 .end
= iosapic_end_edge_irq
,
482 .unmask
= unmask_irq
,
483 .set_affinity
= iosapic_set_affinity
487 iosapic_version (char __iomem
*addr
)
490 * IOSAPIC Version Register return 32 bit structure like:
492 * unsigned int version : 8;
493 * unsigned int reserved1 : 8;
494 * unsigned int max_redir : 8;
495 * unsigned int reserved2 : 8;
498 return __iosapic_read(addr
, IOSAPIC_VERSION
);
501 static int iosapic_find_sharable_vector (unsigned long trigger
,
504 int i
, vector
= -ENOSPC
, min_count
= -1;
505 struct iosapic_intr_info
*info
;
508 * shared vectors for edge-triggered interrupts are not
511 if (trigger
== IOSAPIC_EDGE
)
514 for (i
= IA64_FIRST_DEVICE_VECTOR
; i
<= IA64_LAST_DEVICE_VECTOR
; i
++) {
515 info
= &iosapic_intr_info
[i
];
516 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
517 (info
->dmode
== IOSAPIC_FIXED
|| info
->dmode
==
518 IOSAPIC_LOWEST_PRIORITY
)) {
519 if (min_count
== -1 || info
->count
< min_count
) {
521 min_count
= info
->count
;
530 * if the given vector is already owned by other,
531 * assign a new vector for the other and make the vector available
534 iosapic_reassign_vector (int vector
)
538 if (!list_empty(&iosapic_intr_info
[vector
].rtes
)) {
539 new_vector
= assign_irq_vector(AUTO_ASSIGN
);
541 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
542 printk(KERN_INFO
"Reassigning vector %d to %d\n",
544 memcpy(&iosapic_intr_info
[new_vector
], &iosapic_intr_info
[vector
],
545 sizeof(struct iosapic_intr_info
));
546 INIT_LIST_HEAD(&iosapic_intr_info
[new_vector
].rtes
);
547 list_move(iosapic_intr_info
[vector
].rtes
.next
,
548 &iosapic_intr_info
[new_vector
].rtes
);
549 memset(&iosapic_intr_info
[vector
], 0,
550 sizeof(struct iosapic_intr_info
));
551 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
552 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
556 static struct iosapic_rte_info
*iosapic_alloc_rte (void)
559 struct iosapic_rte_info
*rte
;
560 int preallocated
= 0;
562 if (!iosapic_kmalloc_ok
&& list_empty(&free_rte_list
)) {
563 rte
= alloc_bootmem(sizeof(struct iosapic_rte_info
) *
564 NR_PREALLOCATE_RTE_ENTRIES
);
567 for (i
= 0; i
< NR_PREALLOCATE_RTE_ENTRIES
; i
++, rte
++)
568 list_add(&rte
->rte_list
, &free_rte_list
);
571 if (!list_empty(&free_rte_list
)) {
572 rte
= list_entry(free_rte_list
.next
, struct iosapic_rte_info
,
574 list_del(&rte
->rte_list
);
577 rte
= kmalloc(sizeof(struct iosapic_rte_info
), GFP_ATOMIC
);
582 memset(rte
, 0, sizeof(struct iosapic_rte_info
));
584 rte
->flags
|= RTE_PREALLOCATED
;
589 static void iosapic_free_rte (struct iosapic_rte_info
*rte
)
591 if (rte
->flags
& RTE_PREALLOCATED
)
592 list_add_tail(&rte
->rte_list
, &free_rte_list
);
597 static inline int vector_is_shared (int vector
)
599 return (iosapic_intr_info
[vector
].count
> 1);
603 register_intr (unsigned int gsi
, int vector
, unsigned char delivery
,
604 unsigned long polarity
, unsigned long trigger
)
607 struct hw_interrupt_type
*irq_type
;
609 struct iosapic_rte_info
*rte
;
611 index
= find_iosapic(gsi
);
613 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
618 rte
= gsi_vector_to_rte(gsi
, vector
);
620 rte
= iosapic_alloc_rte();
622 printk(KERN_WARNING
"%s: cannot allocate memory\n",
627 rte
->iosapic
= &iosapic_lists
[index
];
628 rte
->rte_index
= gsi
- rte
->iosapic
->gsi_base
;
630 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[vector
].rtes
);
631 iosapic_intr_info
[vector
].count
++;
632 iosapic_lists
[index
].rtes_inuse
++;
634 else if (vector_is_shared(vector
)) {
635 struct iosapic_intr_info
*info
= &iosapic_intr_info
[vector
];
636 if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
638 "%s: cannot override the interrupt\n",
644 iosapic_intr_info
[vector
].polarity
= polarity
;
645 iosapic_intr_info
[vector
].dmode
= delivery
;
646 iosapic_intr_info
[vector
].trigger
= trigger
;
648 if (trigger
== IOSAPIC_EDGE
)
649 irq_type
= &irq_type_iosapic_edge
;
651 irq_type
= &irq_type_iosapic_level
;
653 idesc
= irq_desc
+ vector
;
654 if (idesc
->chip
!= irq_type
) {
655 if (idesc
->chip
!= &no_irq_type
)
657 "%s: changing vector %d from %s to %s\n",
658 __FUNCTION__
, vector
,
659 idesc
->chip
->name
, irq_type
->name
);
660 idesc
->chip
= irq_type
;
666 get_target_cpu (unsigned int gsi
, int vector
)
670 extern int cpe_vector
;
673 * In case of vector shared by multiple RTEs, all RTEs that
674 * share the vector need to use the same destination CPU.
676 if (!list_empty(&iosapic_intr_info
[vector
].rtes
))
677 return iosapic_intr_info
[vector
].dest
;
680 * If the platform supports redirection via XTP, let it
681 * distribute interrupts.
683 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
684 return cpu_physical_id(smp_processor_id());
687 * Some interrupts (ACPI SCI, for instance) are registered
688 * before the BSP is marked as online.
690 if (!cpu_online(smp_processor_id()))
691 return cpu_physical_id(smp_processor_id());
694 if (cpe_vector
> 0 && vector
== IA64_CPEP_VECTOR
)
695 return get_cpei_target_cpu();
700 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
703 iosapic_index
= find_iosapic(gsi
);
704 if (iosapic_index
< 0 ||
705 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
706 goto skip_numa_setup
;
708 cpu_mask
= node_to_cpumask(iosapic_lists
[iosapic_index
].node
);
710 for_each_cpu_mask(numa_cpu
, cpu_mask
) {
711 if (!cpu_online(numa_cpu
))
712 cpu_clear(numa_cpu
, cpu_mask
);
715 num_cpus
= cpus_weight(cpu_mask
);
718 goto skip_numa_setup
;
720 /* Use vector assignment to distribute across cpus in node */
721 cpu_index
= vector
% num_cpus
;
723 for (numa_cpu
= first_cpu(cpu_mask
) ; i
< cpu_index
; i
++)
724 numa_cpu
= next_cpu(numa_cpu
, cpu_mask
);
726 if (numa_cpu
!= NR_CPUS
)
727 return cpu_physical_id(numa_cpu
);
732 * Otherwise, round-robin interrupt vectors across all the
733 * processors. (It'd be nice if we could be smarter in the
737 if (++cpu
>= NR_CPUS
)
739 } while (!cpu_online(cpu
));
741 return cpu_physical_id(cpu
);
742 #else /* CONFIG_SMP */
743 return cpu_physical_id(smp_processor_id());
748 * ACPI can describe IOSAPIC interrupts via static tables and namespace
749 * methods. This provides an interface to register those interrupts and
750 * program the IOSAPIC RTE.
753 iosapic_register_intr (unsigned int gsi
,
754 unsigned long polarity
, unsigned long trigger
)
756 int vector
, mask
= 1, err
;
759 struct iosapic_rte_info
*rte
;
763 * If this GSI has already been registered (i.e., it's a
764 * shared interrupt, or we lost a race to register it),
765 * don't touch the RTE.
767 spin_lock_irqsave(&iosapic_lock
, flags
);
768 vector
= gsi_to_vector(gsi
);
770 rte
= gsi_vector_to_rte(gsi
, vector
);
772 goto unlock_iosapic_lock
;
775 /* If vector is running out, we try to find a sharable vector */
776 vector
= assign_irq_vector(AUTO_ASSIGN
);
778 vector
= iosapic_find_sharable_vector(trigger
, polarity
);
780 goto unlock_iosapic_lock
;
783 spin_lock(&irq_desc
[vector
].lock
);
784 dest
= get_target_cpu(gsi
, vector
);
785 err
= register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
,
793 * If the vector is shared and already unmasked for other
794 * interrupt sources, don't mask it.
796 low32
= iosapic_intr_info
[vector
].low32
;
797 if (vector_is_shared(vector
) && !(low32
& IOSAPIC_MASK
))
799 set_rte(gsi
, vector
, dest
, mask
);
801 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
802 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
803 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
804 cpu_logical_id(dest
), dest
, vector
);
806 spin_unlock(&irq_desc
[vector
].lock
);
808 spin_unlock_irqrestore(&iosapic_lock
, flags
);
813 iosapic_unregister_intr (unsigned int gsi
)
816 int irq
, vector
, index
;
819 unsigned long trigger
, polarity
;
821 struct iosapic_rte_info
*rte
;
824 * If the irq associated with the gsi is not found,
825 * iosapic_unregister_intr() is unbalanced. We need to check
826 * this again after getting locks.
828 irq
= gsi_to_irq(gsi
);
830 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
835 vector
= irq_to_vector(irq
);
837 spin_lock_irqsave(&iosapic_lock
, flags
);
838 if ((rte
= gsi_vector_to_rte(gsi
, vector
)) == NULL
) {
839 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
845 if (--rte
->refcnt
> 0)
848 /* Remove the rte entry from the list */
849 idesc
= irq_desc
+ irq
;
850 spin_lock(&idesc
->lock
);
851 list_del(&rte
->rte_list
);
852 spin_unlock(&idesc
->lock
);
854 /* Mask the interrupt */
855 low32
= iosapic_intr_info
[vector
].low32
| IOSAPIC_MASK
;
856 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte
->rte_index
), low32
);
858 iosapic_intr_info
[vector
].count
--;
859 iosapic_free_rte(rte
);
860 index
= find_iosapic(gsi
);
861 iosapic_lists
[index
].rtes_inuse
--;
862 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
864 trigger
= iosapic_intr_info
[vector
].trigger
;
865 polarity
= iosapic_intr_info
[vector
].polarity
;
866 dest
= iosapic_intr_info
[vector
].dest
;
868 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
869 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
870 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
871 cpu_logical_id(dest
), dest
, vector
);
873 if (list_empty(&iosapic_intr_info
[vector
].rtes
)) {
875 BUG_ON(iosapic_intr_info
[vector
].count
);
877 /* Clear the interrupt controller descriptor */
878 idesc
->chip
= &no_irq_type
;
882 cpus_setall(idesc
->affinity
);
885 /* Clear the interrupt information */
886 memset(&iosapic_intr_info
[vector
], 0,
887 sizeof(struct iosapic_intr_info
));
888 iosapic_intr_info
[vector
].low32
|= IOSAPIC_MASK
;
889 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
893 "interrupt handlers still exist on IRQ %u\n",
898 /* Free the interrupt vector */
899 free_irq_vector(vector
);
902 spin_unlock_irqrestore(&iosapic_lock
, flags
);
906 * ACPI calls this when it finds an entry for a platform interrupt.
909 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
910 int iosapic_vector
, u16 eid
, u16 id
,
911 unsigned long polarity
, unsigned long trigger
)
913 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
914 unsigned char delivery
;
915 int vector
, mask
= 0;
916 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
919 case ACPI_INTERRUPT_PMI
:
920 vector
= iosapic_vector
;
922 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
923 * we need to make sure the vector is available
925 iosapic_reassign_vector(vector
);
926 delivery
= IOSAPIC_PMI
;
928 case ACPI_INTERRUPT_INIT
:
929 vector
= assign_irq_vector(AUTO_ASSIGN
);
931 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
932 delivery
= IOSAPIC_INIT
;
934 case ACPI_INTERRUPT_CPEI
:
935 vector
= IA64_CPE_VECTOR
;
936 delivery
= IOSAPIC_LOWEST_PRIORITY
;
940 printk(KERN_ERR
"%s: invalid int type 0x%x\n", __FUNCTION__
,
945 register_intr(gsi
, vector
, delivery
, polarity
, trigger
);
948 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
950 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
951 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
952 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
953 cpu_logical_id(dest
), dest
, vector
);
955 set_rte(gsi
, vector
, dest
, mask
);
960 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
963 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
964 unsigned long polarity
,
965 unsigned long trigger
)
968 unsigned int dest
= cpu_physical_id(smp_processor_id());
970 vector
= isa_irq_to_vector(isa_irq
);
972 register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
, polarity
, trigger
);
974 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
975 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
976 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
977 cpu_logical_id(dest
), dest
, vector
);
979 set_rte(gsi
, vector
, dest
, 1);
983 iosapic_system_init (int system_pcat_compat
)
987 for (vector
= 0; vector
< IA64_NUM_VECTORS
; ++vector
) {
988 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
990 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
993 pcat_compat
= system_pcat_compat
;
996 * Disable the compatibility mode interrupts (8259 style),
997 * needs IN/OUT support enabled.
1000 "%s: Disabling PC-AT compatible 8259 interrupts\n",
1008 iosapic_alloc (void)
1012 for (index
= 0; index
< NR_IOSAPICS
; index
++)
1013 if (!iosapic_lists
[index
].addr
)
1016 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __FUNCTION__
);
1021 iosapic_free (int index
)
1023 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
1027 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
1030 unsigned int gsi_end
, base
, end
;
1032 /* check gsi range */
1033 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
1034 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
1035 if (!iosapic_lists
[index
].addr
)
1038 base
= iosapic_lists
[index
].gsi_base
;
1039 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
1041 if (gsi_end
< base
|| end
< gsi_base
)
1050 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1052 int num_rte
, err
, index
;
1053 unsigned int isa_irq
, ver
;
1055 unsigned long flags
;
1057 spin_lock_irqsave(&iosapic_lock
, flags
);
1058 index
= find_iosapic(gsi_base
);
1060 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1064 addr
= ioremap(phys_addr
, 0);
1065 ver
= iosapic_version(addr
);
1066 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1068 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1073 * The MAX_REDIR register holds the highest input pin number
1074 * (starting from 0). We add 1 so that we can use it for
1075 * number of pins (= RTEs)
1077 num_rte
= ((ver
>> 16) & 0xff) + 1;
1079 index
= iosapic_alloc();
1080 iosapic_lists
[index
].addr
= addr
;
1081 iosapic_lists
[index
].gsi_base
= gsi_base
;
1082 iosapic_lists
[index
].num_rte
= num_rte
;
1084 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1086 spin_lock_init(&iosapic_lists
[index
].lock
);
1087 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1089 if ((gsi_base
== 0) && pcat_compat
) {
1091 * Map the legacy ISA devices into the IOSAPIC data. Some of
1092 * these may get reprogrammed later on with data from the ACPI
1093 * Interrupt Source Override table.
1095 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1096 iosapic_override_isa_irq(isa_irq
, isa_irq
,
1103 #ifdef CONFIG_HOTPLUG
1105 iosapic_remove (unsigned int gsi_base
)
1108 unsigned long flags
;
1110 spin_lock_irqsave(&iosapic_lock
, flags
);
1111 index
= find_iosapic(gsi_base
);
1113 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1114 __FUNCTION__
, gsi_base
);
1118 if (iosapic_lists
[index
].rtes_inuse
) {
1120 printk(KERN_WARNING
"%s: IOSAPIC for GSI base %u is busy\n",
1121 __FUNCTION__
, gsi_base
);
1125 iounmap(iosapic_lists
[index
].addr
);
1126 iosapic_free(index
);
1128 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1131 #endif /* CONFIG_HOTPLUG */
1135 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1139 index
= find_iosapic(gsi_base
);
1141 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1142 __FUNCTION__
, gsi_base
);
1145 iosapic_lists
[index
].node
= node
;
1150 static int __init
iosapic_enable_kmalloc (void)
1152 iosapic_kmalloc_ok
= 1;
1155 core_initcall (iosapic_enable_kmalloc
);