2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/input.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
30 #include <linux/of_device.h>
31 #include <linux/clk.h>
32 #include <linux/slab.h>
33 #include <linux/input/matrix_keypad.h>
34 #include <linux/clk/tegra.h>
35 #include <linux/err.h>
37 #define KBC_MAX_KPENT 8
39 /* Maximum row/column supported by Tegra KBC yet is 16x8 */
40 #define KBC_MAX_GPIO 24
41 /* Maximum keys supported by Tegra KBC yet is 16 x 8*/
42 #define KBC_MAX_KEY (16 * 8)
44 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
46 /* KBC row scan time and delay for beginning the row scan. */
47 #define KBC_ROW_SCAN_TIME 16
48 #define KBC_ROW_SCAN_DLY 5
50 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
51 #define KBC_CYCLE_MS 32
55 /* KBC Control Register */
56 #define KBC_CONTROL_0 0x0
57 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
58 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
59 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
60 #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
61 #define KBC_CONTROL_KBC_EN (1 << 0)
63 /* KBC Interrupt Register */
65 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
66 #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
68 #define KBC_ROW_CFG0_0 0x8
69 #define KBC_COL_CFG0_0 0x18
70 #define KBC_TO_CNT_0 0x24
71 #define KBC_INIT_DLY_0 0x28
72 #define KBC_RPT_DLY_0 0x2c
73 #define KBC_KP_ENT0_0 0x30
74 #define KBC_KP_ENT1_0 0x34
75 #define KBC_ROW0_MASK_0 0x38
77 #define KBC_ROW_SHIFT 3
85 /* Tegra KBC hw support */
86 struct tegra_kbc_hw_support
{
91 struct tegra_kbc_pin_cfg
{
92 enum tegra_pin_type type
;
98 unsigned int debounce_cnt
;
99 unsigned int repeat_cnt
;
100 struct tegra_kbc_pin_cfg pin_cfg
[KBC_MAX_GPIO
];
101 const struct matrix_keymap_data
*keymap_data
;
104 struct input_dev
*idev
;
107 unsigned int repoll_dly
;
108 unsigned long cp_dly_jiffies
;
109 unsigned int cp_to_wkup_dly
;
111 bool use_ghost_filter
;
112 bool keypress_caused_wake
;
113 unsigned short keycode
[KBC_MAX_KEY
* 2];
114 unsigned short current_keys
[KBC_MAX_KPENT
];
115 unsigned int num_pressed_keys
;
117 struct timer_list timer
;
119 const struct tegra_kbc_hw_support
*hw_support
;
121 int num_rows_and_columns
;
124 static void tegra_kbc_report_released_keys(struct input_dev
*input
,
125 unsigned short old_keycodes
[],
126 unsigned int old_num_keys
,
127 unsigned short new_keycodes
[],
128 unsigned int new_num_keys
)
132 for (i
= 0; i
< old_num_keys
; i
++) {
133 for (j
= 0; j
< new_num_keys
; j
++)
134 if (old_keycodes
[i
] == new_keycodes
[j
])
137 if (j
== new_num_keys
)
138 input_report_key(input
, old_keycodes
[i
], 0);
142 static void tegra_kbc_report_pressed_keys(struct input_dev
*input
,
143 unsigned char scancodes
[],
144 unsigned short keycodes
[],
145 unsigned int num_pressed_keys
)
149 for (i
= 0; i
< num_pressed_keys
; i
++) {
150 input_event(input
, EV_MSC
, MSC_SCAN
, scancodes
[i
]);
151 input_report_key(input
, keycodes
[i
], 1);
155 static void tegra_kbc_report_keys(struct tegra_kbc
*kbc
)
157 unsigned char scancodes
[KBC_MAX_KPENT
];
158 unsigned short keycodes
[KBC_MAX_KPENT
];
161 unsigned int num_down
= 0;
162 bool fn_keypress
= false;
163 bool key_in_same_row
= false;
164 bool key_in_same_col
= false;
166 for (i
= 0; i
< KBC_MAX_KPENT
; i
++) {
168 val
= readl(kbc
->mmio
+ KBC_KP_ENT0_0
+ i
);
171 unsigned int col
= val
& 0x07;
172 unsigned int row
= (val
>> 3) & 0x0f;
173 unsigned char scancode
=
174 MATRIX_SCAN_CODE(row
, col
, KBC_ROW_SHIFT
);
176 scancodes
[num_down
] = scancode
;
177 keycodes
[num_down
] = kbc
->keycode
[scancode
];
178 /* If driver uses Fn map, do not report the Fn key. */
179 if ((keycodes
[num_down
] == KEY_FN
) && kbc
->use_fn_map
)
189 * Matrix keyboard designs are prone to keyboard ghosting.
190 * Ghosting occurs if there are 3 keys such that -
191 * any 2 of the 3 keys share a row, and any 2 of them share a column.
192 * If so ignore the key presses for this iteration.
194 if (kbc
->use_ghost_filter
&& num_down
>= 3) {
195 for (i
= 0; i
< num_down
; i
++) {
197 u8 curr_col
= scancodes
[i
] & 0x07;
198 u8 curr_row
= scancodes
[i
] >> KBC_ROW_SHIFT
;
201 * Find 2 keys such that one key is in the same row
202 * and the other is in the same column as the i-th key.
204 for (j
= i
+ 1; j
< num_down
; j
++) {
205 u8 col
= scancodes
[j
] & 0x07;
206 u8 row
= scancodes
[j
] >> KBC_ROW_SHIFT
;
209 key_in_same_col
= true;
211 key_in_same_row
= true;
217 * If the platform uses Fn keymaps, translate keys on a Fn keypress.
218 * Function keycodes are max_keys apart from the plain keycodes.
221 for (i
= 0; i
< num_down
; i
++) {
222 scancodes
[i
] += kbc
->max_keys
;
223 keycodes
[i
] = kbc
->keycode
[scancodes
[i
]];
227 /* Ignore the key presses for this iteration? */
228 if (key_in_same_col
&& key_in_same_row
)
231 tegra_kbc_report_released_keys(kbc
->idev
,
232 kbc
->current_keys
, kbc
->num_pressed_keys
,
234 tegra_kbc_report_pressed_keys(kbc
->idev
, scancodes
, keycodes
, num_down
);
235 input_sync(kbc
->idev
);
237 memcpy(kbc
->current_keys
, keycodes
, sizeof(kbc
->current_keys
));
238 kbc
->num_pressed_keys
= num_down
;
241 static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc
*kbc
, bool enable
)
245 val
= readl(kbc
->mmio
+ KBC_CONTROL_0
);
247 val
|= KBC_CONTROL_FIFO_CNT_INT_EN
;
249 val
&= ~KBC_CONTROL_FIFO_CNT_INT_EN
;
250 writel(val
, kbc
->mmio
+ KBC_CONTROL_0
);
253 static void tegra_kbc_keypress_timer(unsigned long data
)
255 struct tegra_kbc
*kbc
= (struct tegra_kbc
*)data
;
260 spin_lock_irqsave(&kbc
->lock
, flags
);
262 val
= (readl(kbc
->mmio
+ KBC_INT_0
) >> 4) & 0xf;
266 tegra_kbc_report_keys(kbc
);
269 * If more than one keys are pressed we need not wait
270 * for the repoll delay.
272 dly
= (val
== 1) ? kbc
->repoll_dly
: 1;
273 mod_timer(&kbc
->timer
, jiffies
+ msecs_to_jiffies(dly
));
275 /* Release any pressed keys and exit the polling loop */
276 for (i
= 0; i
< kbc
->num_pressed_keys
; i
++)
277 input_report_key(kbc
->idev
, kbc
->current_keys
[i
], 0);
278 input_sync(kbc
->idev
);
280 kbc
->num_pressed_keys
= 0;
282 /* All keys are released so enable the keypress interrupt */
283 tegra_kbc_set_fifo_interrupt(kbc
, true);
286 spin_unlock_irqrestore(&kbc
->lock
, flags
);
289 static irqreturn_t
tegra_kbc_isr(int irq
, void *args
)
291 struct tegra_kbc
*kbc
= args
;
295 spin_lock_irqsave(&kbc
->lock
, flags
);
298 * Quickly bail out & reenable interrupts if the fifo threshold
299 * count interrupt wasn't the interrupt source
301 val
= readl(kbc
->mmio
+ KBC_INT_0
);
302 writel(val
, kbc
->mmio
+ KBC_INT_0
);
304 if (val
& KBC_INT_FIFO_CNT_INT_STATUS
) {
306 * Until all keys are released, defer further processing to
307 * the polling loop in tegra_kbc_keypress_timer.
309 tegra_kbc_set_fifo_interrupt(kbc
, false);
310 mod_timer(&kbc
->timer
, jiffies
+ kbc
->cp_dly_jiffies
);
311 } else if (val
& KBC_INT_KEYPRESS_INT_STATUS
) {
312 /* We can be here only through system resume path */
313 kbc
->keypress_caused_wake
= true;
316 spin_unlock_irqrestore(&kbc
->lock
, flags
);
321 static void tegra_kbc_setup_wakekeys(struct tegra_kbc
*kbc
, bool filter
)
324 unsigned int rst_val
;
326 /* Either mask all keys or none. */
327 rst_val
= (filter
&& !kbc
->wakeup
) ? ~0 : 0;
329 for (i
= 0; i
< kbc
->hw_support
->max_rows
; i
++)
330 writel(rst_val
, kbc
->mmio
+ KBC_ROW0_MASK_0
+ i
* 4);
333 static void tegra_kbc_config_pins(struct tegra_kbc
*kbc
)
337 for (i
= 0; i
< KBC_MAX_GPIO
; i
++) {
338 u32 r_shft
= 5 * (i
% 6);
339 u32 c_shft
= 4 * (i
% 8);
340 u32 r_mask
= 0x1f << r_shft
;
341 u32 c_mask
= 0x0f << c_shft
;
342 u32 r_offs
= (i
/ 6) * 4 + KBC_ROW_CFG0_0
;
343 u32 c_offs
= (i
/ 8) * 4 + KBC_COL_CFG0_0
;
344 u32 row_cfg
= readl(kbc
->mmio
+ r_offs
);
345 u32 col_cfg
= readl(kbc
->mmio
+ c_offs
);
350 switch (kbc
->pin_cfg
[i
].type
) {
352 row_cfg
|= ((kbc
->pin_cfg
[i
].num
<< 1) | 1) << r_shft
;
356 col_cfg
|= ((kbc
->pin_cfg
[i
].num
<< 1) | 1) << c_shft
;
363 writel(row_cfg
, kbc
->mmio
+ r_offs
);
364 writel(col_cfg
, kbc
->mmio
+ c_offs
);
368 static int tegra_kbc_start(struct tegra_kbc
*kbc
)
370 unsigned int debounce_cnt
;
373 clk_prepare_enable(kbc
->clk
);
375 /* Reset the KBC controller to clear all previous status.*/
376 tegra_periph_reset_assert(kbc
->clk
);
378 tegra_periph_reset_deassert(kbc
->clk
);
381 tegra_kbc_config_pins(kbc
);
382 tegra_kbc_setup_wakekeys(kbc
, false);
384 writel(kbc
->repeat_cnt
, kbc
->mmio
+ KBC_RPT_DLY_0
);
386 /* Keyboard debounce count is maximum of 12 bits. */
387 debounce_cnt
= min(kbc
->debounce_cnt
, KBC_MAX_DEBOUNCE_CNT
);
388 val
= KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt
);
389 val
|= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
390 val
|= KBC_CONTROL_FIFO_CNT_INT_EN
; /* interrupt on FIFO threshold */
391 val
|= KBC_CONTROL_KBC_EN
; /* enable */
392 writel(val
, kbc
->mmio
+ KBC_CONTROL_0
);
395 * Compute the delay(ns) from interrupt mode to continuous polling
396 * mode so the timer routine is scheduled appropriately.
398 val
= readl(kbc
->mmio
+ KBC_INIT_DLY_0
);
399 kbc
->cp_dly_jiffies
= usecs_to_jiffies((val
& 0xfffff) * 32);
401 kbc
->num_pressed_keys
= 0;
404 * Atomically clear out any remaining entries in the key FIFO
405 * and enable keyboard interrupts.
408 val
= readl(kbc
->mmio
+ KBC_INT_0
);
413 val
= readl(kbc
->mmio
+ KBC_KP_ENT0_0
);
414 val
= readl(kbc
->mmio
+ KBC_KP_ENT1_0
);
416 writel(0x7, kbc
->mmio
+ KBC_INT_0
);
418 enable_irq(kbc
->irq
);
423 static void tegra_kbc_stop(struct tegra_kbc
*kbc
)
428 spin_lock_irqsave(&kbc
->lock
, flags
);
429 val
= readl(kbc
->mmio
+ KBC_CONTROL_0
);
431 writel(val
, kbc
->mmio
+ KBC_CONTROL_0
);
432 spin_unlock_irqrestore(&kbc
->lock
, flags
);
434 disable_irq(kbc
->irq
);
435 del_timer_sync(&kbc
->timer
);
437 clk_disable_unprepare(kbc
->clk
);
440 static int tegra_kbc_open(struct input_dev
*dev
)
442 struct tegra_kbc
*kbc
= input_get_drvdata(dev
);
444 return tegra_kbc_start(kbc
);
447 static void tegra_kbc_close(struct input_dev
*dev
)
449 struct tegra_kbc
*kbc
= input_get_drvdata(dev
);
451 return tegra_kbc_stop(kbc
);
454 static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc
*kbc
,
455 unsigned int *num_rows
)
461 for (i
= 0; i
< KBC_MAX_GPIO
; i
++) {
462 const struct tegra_kbc_pin_cfg
*pin_cfg
= &kbc
->pin_cfg
[i
];
464 switch (pin_cfg
->type
) {
466 if (pin_cfg
->num
>= kbc
->hw_support
->max_rows
) {
468 "pin_cfg[%d]: invalid row number %d\n",
476 if (pin_cfg
->num
>= kbc
->hw_support
->max_columns
) {
478 "pin_cfg[%d]: invalid column number %d\n",
489 "pin_cfg[%d]: invalid entry type %d\n",
490 pin_cfg
->type
, pin_cfg
->num
);
498 static int tegra_kbc_parse_dt(struct tegra_kbc
*kbc
)
500 struct device_node
*np
= kbc
->dev
->of_node
;
505 u32 cols_cfg
[KBC_MAX_GPIO
];
506 u32 rows_cfg
[KBC_MAX_GPIO
];
510 if (!of_property_read_u32(np
, "nvidia,debounce-delay-ms", &prop
))
511 kbc
->debounce_cnt
= prop
;
513 if (!of_property_read_u32(np
, "nvidia,repeat-delay-ms", &prop
))
514 kbc
->repeat_cnt
= prop
;
516 if (of_find_property(np
, "nvidia,needs-ghost-filter", NULL
))
517 kbc
->use_ghost_filter
= true;
519 if (of_find_property(np
, "nvidia,wakeup-source", NULL
))
522 if (!of_get_property(np
, "nvidia,kbc-row-pins", &proplen
)) {
523 dev_err(kbc
->dev
, "property nvidia,kbc-row-pins not found\n");
526 num_rows
= proplen
/ sizeof(u32
);
528 if (!of_get_property(np
, "nvidia,kbc-col-pins", &proplen
)) {
529 dev_err(kbc
->dev
, "property nvidia,kbc-col-pins not found\n");
532 num_cols
= proplen
/ sizeof(u32
);
534 if (num_rows
> kbc
->hw_support
->max_rows
) {
536 "Number of rows is more than supported by hardware\n");
540 if (num_cols
> kbc
->hw_support
->max_columns
) {
542 "Number of cols is more than supported by hardware\n");
546 if (!of_get_property(np
, "linux,keymap", &proplen
)) {
547 dev_err(kbc
->dev
, "property linux,keymap not found\n");
551 if (!num_rows
|| !num_cols
|| ((num_rows
+ num_cols
) > KBC_MAX_GPIO
)) {
553 "keypad rows/columns not porperly specified\n");
557 /* Set all pins as non-configured */
558 for (i
= 0; i
< kbc
->num_rows_and_columns
; i
++)
559 kbc
->pin_cfg
[i
].type
= PIN_CFG_IGNORE
;
561 ret
= of_property_read_u32_array(np
, "nvidia,kbc-row-pins",
564 dev_err(kbc
->dev
, "Rows configurations are not proper\n");
568 ret
= of_property_read_u32_array(np
, "nvidia,kbc-col-pins",
571 dev_err(kbc
->dev
, "Cols configurations are not proper\n");
575 for (i
= 0; i
< num_rows
; i
++) {
576 kbc
->pin_cfg
[rows_cfg
[i
]].type
= PIN_CFG_ROW
;
577 kbc
->pin_cfg
[rows_cfg
[i
]].num
= i
;
580 for (i
= 0; i
< num_cols
; i
++) {
581 kbc
->pin_cfg
[cols_cfg
[i
]].type
= PIN_CFG_COL
;
582 kbc
->pin_cfg
[cols_cfg
[i
]].num
= i
;
588 static const struct tegra_kbc_hw_support tegra20_kbc_hw_support
= {
593 static const struct tegra_kbc_hw_support tegra11_kbc_hw_support
= {
598 static const struct of_device_id tegra_kbc_of_match
[] = {
599 { .compatible
= "nvidia,tegra114-kbc", .data
= &tegra11_kbc_hw_support
},
600 { .compatible
= "nvidia,tegra30-kbc", .data
= &tegra20_kbc_hw_support
},
601 { .compatible
= "nvidia,tegra20-kbc", .data
= &tegra20_kbc_hw_support
},
604 MODULE_DEVICE_TABLE(of
, tegra_kbc_of_match
);
606 static int tegra_kbc_probe(struct platform_device
*pdev
)
608 struct tegra_kbc
*kbc
;
609 struct resource
*res
;
612 unsigned int debounce_cnt
;
613 unsigned int scan_time_rows
;
614 unsigned int keymap_rows
;
615 const struct of_device_id
*match
;
617 match
= of_match_device(of_match_ptr(tegra_kbc_of_match
), &pdev
->dev
);
619 kbc
= devm_kzalloc(&pdev
->dev
, sizeof(*kbc
), GFP_KERNEL
);
621 dev_err(&pdev
->dev
, "failed to alloc memory for kbc\n");
625 kbc
->dev
= &pdev
->dev
;
626 kbc
->hw_support
= match
->data
;
627 kbc
->max_keys
= kbc
->hw_support
->max_rows
*
628 kbc
->hw_support
->max_columns
;
629 kbc
->num_rows_and_columns
= kbc
->hw_support
->max_rows
+
630 kbc
->hw_support
->max_columns
;
631 keymap_rows
= kbc
->max_keys
;
632 spin_lock_init(&kbc
->lock
);
634 err
= tegra_kbc_parse_dt(kbc
);
638 if (!tegra_kbc_check_pin_cfg(kbc
, &num_rows
))
641 kbc
->irq
= platform_get_irq(pdev
, 0);
643 dev_err(&pdev
->dev
, "failed to get keyboard IRQ\n");
647 kbc
->idev
= devm_input_allocate_device(&pdev
->dev
);
649 dev_err(&pdev
->dev
, "failed to allocate input device\n");
653 setup_timer(&kbc
->timer
, tegra_kbc_keypress_timer
, (unsigned long)kbc
);
655 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
656 kbc
->mmio
= devm_ioremap_resource(&pdev
->dev
, res
);
657 if (IS_ERR(kbc
->mmio
))
658 return PTR_ERR(kbc
->mmio
);
660 kbc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
661 if (IS_ERR(kbc
->clk
)) {
662 dev_err(&pdev
->dev
, "failed to get keyboard clock\n");
663 return PTR_ERR(kbc
->clk
);
667 * The time delay between two consecutive reads of the FIFO is
668 * the sum of the repeat time and the time taken for scanning
669 * the rows. There is an additional delay before the row scanning
670 * starts. The repoll delay is computed in milliseconds.
672 debounce_cnt
= min(kbc
->debounce_cnt
, KBC_MAX_DEBOUNCE_CNT
);
673 scan_time_rows
= (KBC_ROW_SCAN_TIME
+ debounce_cnt
) * num_rows
;
674 kbc
->repoll_dly
= KBC_ROW_SCAN_DLY
+ scan_time_rows
+ kbc
->repeat_cnt
;
675 kbc
->repoll_dly
= DIV_ROUND_UP(kbc
->repoll_dly
, KBC_CYCLE_MS
);
677 kbc
->idev
->name
= pdev
->name
;
678 kbc
->idev
->id
.bustype
= BUS_HOST
;
679 kbc
->idev
->dev
.parent
= &pdev
->dev
;
680 kbc
->idev
->open
= tegra_kbc_open
;
681 kbc
->idev
->close
= tegra_kbc_close
;
683 if (kbc
->keymap_data
&& kbc
->use_fn_map
)
686 err
= matrix_keypad_build_keymap(kbc
->keymap_data
, NULL
,
688 kbc
->hw_support
->max_columns
,
689 kbc
->keycode
, kbc
->idev
);
691 dev_err(&pdev
->dev
, "failed to setup keymap\n");
695 __set_bit(EV_REP
, kbc
->idev
->evbit
);
696 input_set_capability(kbc
->idev
, EV_MSC
, MSC_SCAN
);
698 input_set_drvdata(kbc
->idev
, kbc
);
700 err
= devm_request_irq(&pdev
->dev
, kbc
->irq
, tegra_kbc_isr
,
701 IRQF_NO_SUSPEND
| IRQF_TRIGGER_HIGH
, pdev
->name
, kbc
);
703 dev_err(&pdev
->dev
, "failed to request keyboard IRQ\n");
707 disable_irq(kbc
->irq
);
709 err
= input_register_device(kbc
->idev
);
711 dev_err(&pdev
->dev
, "failed to register input device\n");
715 platform_set_drvdata(pdev
, kbc
);
716 device_init_wakeup(&pdev
->dev
, kbc
->wakeup
);
721 #ifdef CONFIG_PM_SLEEP
722 static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc
*kbc
, bool enable
)
726 val
= readl(kbc
->mmio
+ KBC_CONTROL_0
);
728 val
|= KBC_CONTROL_KEYPRESS_INT_EN
;
730 val
&= ~KBC_CONTROL_KEYPRESS_INT_EN
;
731 writel(val
, kbc
->mmio
+ KBC_CONTROL_0
);
734 static int tegra_kbc_suspend(struct device
*dev
)
736 struct platform_device
*pdev
= to_platform_device(dev
);
737 struct tegra_kbc
*kbc
= platform_get_drvdata(pdev
);
739 mutex_lock(&kbc
->idev
->mutex
);
740 if (device_may_wakeup(&pdev
->dev
)) {
741 disable_irq(kbc
->irq
);
742 del_timer_sync(&kbc
->timer
);
743 tegra_kbc_set_fifo_interrupt(kbc
, false);
745 /* Forcefully clear the interrupt status */
746 writel(0x7, kbc
->mmio
+ KBC_INT_0
);
748 * Store the previous resident time of continuous polling mode.
749 * Force the keyboard into interrupt mode.
751 kbc
->cp_to_wkup_dly
= readl(kbc
->mmio
+ KBC_TO_CNT_0
);
752 writel(0, kbc
->mmio
+ KBC_TO_CNT_0
);
754 tegra_kbc_setup_wakekeys(kbc
, true);
757 kbc
->keypress_caused_wake
= false;
758 /* Enable keypress interrupt before going into suspend. */
759 tegra_kbc_set_keypress_interrupt(kbc
, true);
760 enable_irq(kbc
->irq
);
761 enable_irq_wake(kbc
->irq
);
763 if (kbc
->idev
->users
)
766 mutex_unlock(&kbc
->idev
->mutex
);
771 static int tegra_kbc_resume(struct device
*dev
)
773 struct platform_device
*pdev
= to_platform_device(dev
);
774 struct tegra_kbc
*kbc
= platform_get_drvdata(pdev
);
777 mutex_lock(&kbc
->idev
->mutex
);
778 if (device_may_wakeup(&pdev
->dev
)) {
779 disable_irq_wake(kbc
->irq
);
780 tegra_kbc_setup_wakekeys(kbc
, false);
781 /* We will use fifo interrupts for key detection. */
782 tegra_kbc_set_keypress_interrupt(kbc
, false);
784 /* Restore the resident time of continuous polling mode. */
785 writel(kbc
->cp_to_wkup_dly
, kbc
->mmio
+ KBC_TO_CNT_0
);
787 tegra_kbc_set_fifo_interrupt(kbc
, true);
789 if (kbc
->keypress_caused_wake
&& kbc
->wakeup_key
) {
791 * We can't report events directly from the ISR
792 * because timekeeping is stopped when processing
793 * wakeup request and we get a nasty warning when
794 * we try to call do_gettimeofday() in evdev
797 input_report_key(kbc
->idev
, kbc
->wakeup_key
, 1);
798 input_sync(kbc
->idev
);
799 input_report_key(kbc
->idev
, kbc
->wakeup_key
, 0);
800 input_sync(kbc
->idev
);
803 if (kbc
->idev
->users
)
804 err
= tegra_kbc_start(kbc
);
806 mutex_unlock(&kbc
->idev
->mutex
);
812 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops
, tegra_kbc_suspend
, tegra_kbc_resume
);
814 static struct platform_driver tegra_kbc_driver
= {
815 .probe
= tegra_kbc_probe
,
818 .owner
= THIS_MODULE
,
819 .pm
= &tegra_kbc_pm_ops
,
820 .of_match_table
= tegra_kbc_of_match
,
823 module_platform_driver(tegra_kbc_driver
);
825 MODULE_LICENSE("GPL");
826 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
827 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
828 MODULE_ALIAS("platform:tegra-kbc");