1 /* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/timer.h>
21 #include <linux/init.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
25 #include <linux/i2c.h>
27 #include <linux/gpio.h>
28 #include <linux/delay.h>
29 #include <linux/dm9000.h>
31 #include <video/platform_lcd.h>
32 #include <video/samsung_fimd.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/irq.h>
38 #include <mach/hardware.h>
42 #include <asm/mach-types.h>
44 #include <plat/regs-serial.h>
45 #include <linux/platform_data/i2c-s3c2410.h>
48 #include <plat/clock.h>
49 #include <plat/devs.h>
51 #include <mach/regs-gpio.h>
54 #include "regs-modem.h"
57 #define ANW6410_PA_DM9000 (0x18000000)
59 /* A hardware buffer to control external devices is mapped at 0x30000000.
60 * It can not be read. So current status must be kept in anw6410_extdev_status.
62 #define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
63 #define ANW6410_PA_EXTDEV (0x30000000)
65 #define ANW6410_EN_DM9000 (1<<11)
66 #define ANW6410_EN_LCD (1<<14)
68 static __u32 anw6410_extdev_status
;
70 static struct s3c2410_uartcfg anw6410_uartcfgs
[] __initdata
= {
87 /* framebuffer and LCD setup. */
88 static void __init
anw6410_lcd_mode_set(void)
92 /* set the LCD type */
93 tmp
= __raw_readl(S3C64XX_SPCON
);
94 tmp
&= ~S3C64XX_SPCON_LCD_SEL_MASK
;
95 tmp
|= S3C64XX_SPCON_LCD_SEL_RGB
;
96 __raw_writel(tmp
, S3C64XX_SPCON
);
98 /* remove the LCD bypass */
99 tmp
= __raw_readl(S3C64XX_MODEM_MIFPCON
);
100 tmp
&= ~MIFPCON_LCD_BYPASS
;
101 __raw_writel(tmp
, S3C64XX_MODEM_MIFPCON
);
104 /* GPF1 = LCD panel power
105 * GPF4 = LCD backlight control
107 static void anw6410_lcd_power_set(struct plat_lcd_data
*pd
,
111 anw6410_extdev_status
|= (ANW6410_EN_LCD
<< 16);
112 __raw_writel(anw6410_extdev_status
, ANW6410_VA_EXTDEV
);
114 gpio_direction_output(S3C64XX_GPF(1), 1);
115 gpio_direction_output(S3C64XX_GPF(4), 1);
117 anw6410_extdev_status
&= ~(ANW6410_EN_LCD
<< 16);
118 __raw_writel(anw6410_extdev_status
, ANW6410_VA_EXTDEV
);
120 gpio_direction_output(S3C64XX_GPF(1), 0);
121 gpio_direction_output(S3C64XX_GPF(4), 0);
125 static struct plat_lcd_data anw6410_lcd_power_data
= {
126 .set_power
= anw6410_lcd_power_set
,
129 static struct platform_device anw6410_lcd_powerdev
= {
130 .name
= "platform-lcd",
131 .dev
.parent
= &s3c_device_fb
.dev
,
132 .dev
.platform_data
= &anw6410_lcd_power_data
,
135 static struct s3c_fb_pd_win anw6410_fb_win0
= {
142 static struct fb_videomode anw6410_lcd_timing
= {
153 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
154 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata
= {
155 .setup_gpio
= s3c64xx_fb_gpio_setup_24bpp
,
156 .vtiming
= &anw6410_lcd_timing
,
157 .win
[0] = &anw6410_fb_win0
,
158 .vidcon0
= VIDCON0_VIDOUT_RGB
| VIDCON0_PNRMODE_RGB
,
159 .vidcon1
= VIDCON1_INV_HSYNC
| VIDCON1_INV_VSYNC
,
162 /* DM9000AEP 10/100 ethernet controller */
163 static void __init
anw6410_dm9000_enable(void)
165 anw6410_extdev_status
|= (ANW6410_EN_DM9000
<< 16);
166 __raw_writel(anw6410_extdev_status
, ANW6410_VA_EXTDEV
);
169 static struct resource anw6410_dm9000_resource
[] = {
170 [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000
, 4),
171 [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000
+ 4, 501),
172 [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL
, IORESOURCE_IRQ \
173 | IRQF_TRIGGER_HIGH
),
176 static struct dm9000_plat_data anw6410_dm9000_pdata
= {
177 .flags
= (DM9000_PLATF_16BITONLY
| DM9000_PLATF_NO_EEPROM
),
178 /* dev_addr can be set to provide hwaddr. */
181 static struct platform_device anw6410_device_eth
= {
184 .num_resources
= ARRAY_SIZE(anw6410_dm9000_resource
),
185 .resource
= anw6410_dm9000_resource
,
187 .platform_data
= &anw6410_dm9000_pdata
,
191 static struct map_desc anw6410_iodesc
[] __initdata
= {
193 .virtual = (unsigned long)ANW6410_VA_EXTDEV
,
194 .pfn
= __phys_to_pfn(ANW6410_PA_EXTDEV
),
200 static struct platform_device
*anw6410_devices
[] __initdata
= {
202 &anw6410_lcd_powerdev
,
206 static void __init
anw6410_map_io(void)
208 s3c64xx_init_io(anw6410_iodesc
, ARRAY_SIZE(anw6410_iodesc
));
209 s3c24xx_init_clocks(12000000);
210 s3c24xx_init_uarts(anw6410_uartcfgs
, ARRAY_SIZE(anw6410_uartcfgs
));
212 anw6410_lcd_mode_set();
215 static void __init
anw6410_machine_init(void)
217 s3c_fb_set_platdata(&anw6410_lcd_pdata
);
219 gpio_request(S3C64XX_GPF(1), "panel power");
220 gpio_request(S3C64XX_GPF(4), "LCD backlight");
222 anw6410_dm9000_enable();
224 platform_add_devices(anw6410_devices
, ARRAY_SIZE(anw6410_devices
));
227 MACHINE_START(ANW6410
, "A&W6410")
228 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
229 .atag_offset
= 0x100,
231 .init_irq
= s3c6410_init_irq
,
232 .map_io
= anw6410_map_io
,
233 .init_machine
= anw6410_machine_init
,
234 .init_late
= s3c64xx_init_late
,
235 .init_time
= s3c24xx_timer_init
,
236 .restart
= s3c64xx_restart
,