arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/uaccess.h>
  19
  20 #include <asm/irq_regs.h>
  21 #include <asm/pmu.h>
  22 #include <asm/stacktrace.h>
  23
  24 static int
  25 armpmu_map_cache_event(const unsigned (*cache_map)
  26                                       [PERF_COUNT_HW_CACHE_MAX]
  27                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  28                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  29                        u64 config)
  30 {
  31         unsigned int cache_type, cache_op, cache_result, ret;
  32
  33         cache_type = (config >>  0) & 0xff;
  34         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  35                 return -EINVAL;
  36
  37         cache_op = (config >>  8) & 0xff;
  38         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  39                 return -EINVAL;
  40
  41         cache_result = (config >> 16) & 0xff;
  42         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  43                 return -EINVAL;
  44
  45         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  46
  47         if (ret == CACHE_OP_UNSUPPORTED)
  48                 return -ENOENT;
  49
  50         return ret;
  51 }
  52
  53 static int
  54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  55 {
  56         int mapping = (*event_map)[config];
  57         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  58 }
  59
  60 static int
  61 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  62 {
  63         return (int)(config & raw_event_mask);
  64 }
  65
  66 int
  67 armpmu_map_event(struct perf_event *event,
  68                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  69                  const unsigned (*cache_map)
  70                                 [PERF_COUNT_HW_CACHE_MAX]
  71                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  72                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  73                  u32 raw_event_mask)
  74 {
  75         u64 config = event->attr.config;
  76
  77         switch (event->attr.type) {
  78         case PERF_TYPE_HARDWARE:
  79                 return armpmu_map_hw_event(event_map, config);
  80         case PERF_TYPE_HW_CACHE:
  81                 return armpmu_map_cache_event(cache_map, config);
  82         case PERF_TYPE_RAW:
  83                 return armpmu_map_raw_event(raw_event_mask, config);
  84         }
  85
  86         return -ENOENT;
  87 }
  88
  89 int armpmu_event_set_period(struct perf_event *event)
  90 {
  91         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  92         struct hw_perf_event *hwc = &event->hw;
  93         s64 left = local64_read(&hwc->period_left);
  94         s64 period = hwc->sample_period;
  95         int ret = 0;
  96
  97         /* The period may have been changed by PERF_EVENT_IOC_PERIOD */
  98         if (unlikely(period != hwc->last_period))
  99                 left = period - (hwc->last_period - left);
 100
 101         if (unlikely(left <= -period)) {
 102                 left = period;
 103                 local64_set(&hwc->period_left, left);
 104                 hwc->last_period = period;
 105                 ret = 1;
 106         }
 107
 108         if (unlikely(left <= 0)) {
 109                 left += period;
 110                 local64_set(&hwc->period_left, left);
 111                 hwc->last_period = period;
 112                 ret = 1;
 113         }
 114
 115         if (left > (s64)armpmu->max_period)
 116                 left = armpmu->max_period;
 117
 118         local64_set(&hwc->prev_count, (u64)-left);
 119
 120         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 121
 122         perf_event_update_userpage(event);
 123
 124         return ret;
 125 }
 126
 127 u64 armpmu_event_update(struct perf_event *event)
 128 {
 129         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 130         struct hw_perf_event *hwc = &event->hw;
 131         u64 delta, prev_raw_count, new_raw_count;
 132
 133 again:
 134         prev_raw_count = local64_read(&hwc->prev_count);
 135         new_raw_count = armpmu->read_counter(event);
 136
 137         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 138                              new_raw_count) != prev_raw_count)
 139                 goto again;
 140
 141         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 142
 143         local64_add(delta, &event->count);
 144         local64_sub(delta, &hwc->period_left);
 145
 146         return new_raw_count;
 147 }
 148
 149 static void
 150 armpmu_read(struct perf_event *event)
 151 {
 152         armpmu_event_update(event);
 153 }
 154
 155 static void
 156 armpmu_stop(struct perf_event *event, int flags)
 157 {
 158         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 159         struct hw_perf_event *hwc = &event->hw;
 160
 161         /*
 162          * ARM pmu always has to update the counter, so ignore
 163          * PERF_EF_UPDATE, see comments in armpmu_start().
 164          */
 165         if (!(hwc->state & PERF_HES_STOPPED)) {
 166                 armpmu->disable(event);
 167                 armpmu_event_update(event);
 168                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 169         }
 170 }
 171
 172 static void armpmu_start(struct perf_event *event, int flags)
 173 {
 174         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 175         struct hw_perf_event *hwc = &event->hw;
 176
 177         /*
 178          * ARM pmu always has to reprogram the period, so ignore
 179          * PERF_EF_RELOAD, see the comment below.
 180          */
 181         if (flags & PERF_EF_RELOAD)
 182                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 183
 184         hwc->state = 0;
 185         /*
 186          * Set the period again. Some counters can't be stopped, so when we
 187          * were stopped we simply disabled the IRQ source and the counter
 188          * may have been left counting. If we don't do this step then we may
 189          * get an interrupt too soon or *way* too late if the overflow has
 190          * happened since disabling.
 191          */
 192         armpmu_event_set_period(event);
 193         armpmu->enable(event);
 194 }
 195
 196 static void
 197 armpmu_del(struct perf_event *event, int flags)
 198 {
 199         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 200         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 201         struct hw_perf_event *hwc = &event->hw;
 202         int idx = hwc->idx;
 203
 204         armpmu_stop(event, PERF_EF_UPDATE);
 205         hw_events->events[idx] = NULL;
 206         clear_bit(idx, hw_events->used_mask);
 207
 208         perf_event_update_userpage(event);
 209 }
 210
 211 static int
 212 armpmu_add(struct perf_event *event, int flags)
 213 {
 214         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 215         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 216         struct hw_perf_event *hwc = &event->hw;
 217         int idx;
 218         int err = 0;
 219
 220         perf_pmu_disable(event->pmu);
 221
 222         /* If we don't have a space for the counter then finish early. */
 223         idx = armpmu->get_event_idx(hw_events, event);
 224         if (idx < 0) {
 225                 err = idx;
 226                 goto out;
 227         }
 228
 229         /*
 230          * If there is an event in the counter we are going to use then make
 231          * sure it is disabled.
 232          */
 233         event->hw.idx = idx;
 234         armpmu->disable(event);
 235         hw_events->events[idx] = event;
 236
 237         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 238         if (flags & PERF_EF_START)
 239                 armpmu_start(event, PERF_EF_RELOAD);
 240
 241         /* Propagate our changes to the userspace mapping. */
 242         perf_event_update_userpage(event);
 243
 244 out:
 245         perf_pmu_enable(event->pmu);
 246         return err;
 247 }
 248
 249 static int
 250 validate_event(struct pmu_hw_events *hw_events,
 251                struct perf_event *event)
 252 {
 253         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 254         struct pmu *leader_pmu = event->group_leader->pmu;
 255
 256         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 257                 return 1;
 258
 259         return armpmu->get_event_idx(hw_events, event) >= 0;
 260 }
 261
 262 static int
 263 validate_group(struct perf_event *event)
 264 {
 265         struct perf_event *sibling, *leader = event->group_leader;
 266         struct pmu_hw_events fake_pmu;
 267         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 268
 269         /*
 270          * Initialise the fake PMU. We only need to populate the
 271          * used_mask for the purposes of validation.
 272          */
 273         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 274         fake_pmu.used_mask = fake_used_mask;
 275
 276         if (!validate_event(&fake_pmu, leader))
 277                 return -EINVAL;
 278
 279         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 280                 if (!validate_event(&fake_pmu, sibling))
 281                         return -EINVAL;
 282         }
 283
 284         if (!validate_event(&fake_pmu, event))
 285                 return -EINVAL;
 286
 287         return 0;
 288 }
 289
 290 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 291 {
 292         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 293         struct platform_device *plat_device = armpmu->plat_device;
 294         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 295
 296         if (plat && plat->handle_irq)
 297                 return plat->handle_irq(irq, dev, armpmu->handle_irq);
 298         else
 299                 return armpmu->handle_irq(irq, dev);
 300 }
 301
 302 static void
 303 armpmu_release_hardware(struct arm_pmu *armpmu)
 304 {
 305         armpmu->free_irq(armpmu);
 306         pm_runtime_put_sync(&armpmu->plat_device->dev);
 307 }
 308
 309 static int
 310 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 311 {
 312         int err;
 313         struct platform_device *pmu_device = armpmu->plat_device;
 314
 315         if (!pmu_device)
 316                 return -ENODEV;
 317
 318         pm_runtime_get_sync(&pmu_device->dev);
 319         err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
 320         if (err) {
 321                 armpmu_release_hardware(armpmu);
 322                 return err;
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void
 329 hw_perf_event_destroy(struct perf_event *event)
 330 {
 331         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 332         atomic_t *active_events  = &armpmu->active_events;
 333         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 334
 335         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 336                 armpmu_release_hardware(armpmu);
 337                 mutex_unlock(pmu_reserve_mutex);
 338         }
 339 }
 340
 341 static int
 342 event_requires_mode_exclusion(struct perf_event_attr *attr)
 343 {
 344         return attr->exclude_idle || attr->exclude_user ||
 345                attr->exclude_kernel || attr->exclude_hv;
 346 }
 347
 348 static int
 349 __hw_perf_event_init(struct perf_event *event)
 350 {
 351         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 352         struct hw_perf_event *hwc = &event->hw;
 353         int mapping;
 354
 355         mapping = armpmu->map_event(event);
 356
 357         if (mapping < 0) {
 358                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 359                          event->attr.config);
 360                 return mapping;
 361         }
 362
 363         /*
 364          * We don't assign an index until we actually place the event onto
 365          * hardware. Use -1 to signify that we haven't decided where to put it
 366          * yet. For SMP systems, each core has it's own PMU so we can't do any
 367          * clever allocation or constraints checking at this point.
 368          */
 369         hwc->idx                = -1;
 370         hwc->config_base        = 0;
 371         hwc->config             = 0;
 372         hwc->event_base         = 0;
 373
 374         /*
 375          * Check whether we need to exclude the counter from certain modes.
 376          */
 377         if ((!armpmu->set_event_filter ||
 378              armpmu->set_event_filter(hwc, &event->attr)) &&
 379              event_requires_mode_exclusion(&event->attr)) {
 380                 pr_debug("ARM performance counters do not support "
 381                          "mode exclusion\n");
 382                 return -EOPNOTSUPP;
 383         }
 384
 385         /*
 386          * Store the event encoding into the config_base field.
 387          */
 388         hwc->config_base            |= (unsigned long)mapping;
 389
 390         if (!hwc->sample_period) {
 391                 /*
 392                  * For non-sampling runs, limit the sample_period to half
 393                  * of the counter width. That way, the new counter value
 394                  * is far less likely to overtake the previous one unless
 395                  * you have some serious IRQ latency issues.
 396                  */
 397                 hwc->sample_period  = armpmu->max_period >> 1;
 398                 hwc->last_period    = hwc->sample_period;
 399                 local64_set(&hwc->period_left, hwc->sample_period);
 400         }
 401
 402         if (event->group_leader != event) {
 403                 if (validate_group(event) != 0)
 404                         return -EINVAL;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int armpmu_event_init(struct perf_event *event)
 411 {
 412         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 413         int err = 0;
 414         atomic_t *active_events = &armpmu->active_events;
 415
 416         /* does not support taken branch sampling */
 417         if (has_branch_stack(event))
 418                 return -EOPNOTSUPP;
 419
 420         if (armpmu->map_event(event) == -ENOENT)
 421                 return -ENOENT;
 422
 423         event->destroy = hw_perf_event_destroy;
 424
 425         if (!atomic_inc_not_zero(active_events)) {
 426                 mutex_lock(&armpmu->reserve_mutex);
 427                 if (atomic_read(active_events) == 0)
 428                         err = armpmu_reserve_hardware(armpmu);
 429
 430                 if (!err)
 431                         atomic_inc(active_events);
 432                 mutex_unlock(&armpmu->reserve_mutex);
 433         }
 434
 435         if (err)
 436                 return err;
 437
 438         err = __hw_perf_event_init(event);
 439         if (err)
 440                 hw_perf_event_destroy(event);
 441
 442         return err;
 443 }
 444
 445 static void armpmu_enable(struct pmu *pmu)
 446 {
 447         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 448         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 449         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 450
 451         if (enabled)
 452                 armpmu->start(armpmu);
 453 }
 454
 455 static void armpmu_disable(struct pmu *pmu)
 456 {
 457         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 458         armpmu->stop(armpmu);
 459 }
 460
 461 #ifdef CONFIG_PM_RUNTIME
 462 static int armpmu_runtime_resume(struct device *dev)
 463 {
 464         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 465
 466         if (plat && plat->runtime_resume)
 467                 return plat->runtime_resume(dev);
 468
 469         return 0;
 470 }
 471
 472 static int armpmu_runtime_suspend(struct device *dev)
 473 {
 474         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 475
 476         if (plat && plat->runtime_suspend)
 477                 return plat->runtime_suspend(dev);
 478
 479         return 0;
 480 }
 481 #endif
 482
 483 const struct dev_pm_ops armpmu_dev_pm_ops = {
 484         SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
 485 };
 486
 487 static void armpmu_init(struct arm_pmu *armpmu)
 488 {
 489         atomic_set(&armpmu->active_events, 0);
 490         mutex_init(&armpmu->reserve_mutex);
 491
 492         armpmu->pmu = (struct pmu) {
 493                 .pmu_enable     = armpmu_enable,
 494                 .pmu_disable    = armpmu_disable,
 495                 .event_init     = armpmu_event_init,
 496                 .add            = armpmu_add,
 497                 .del            = armpmu_del,
 498                 .start          = armpmu_start,
 499                 .stop           = armpmu_stop,
 500                 .read           = armpmu_read,
 501         };
 502 }
 503
 504 int armpmu_register(struct arm_pmu *armpmu, int type)
 505 {
 506         armpmu_init(armpmu);
 507         pm_runtime_enable(&armpmu->plat_device->dev);
 508         pr_info("enabled with %s PMU driver, %d counters available\n",
 509                         armpmu->name, armpmu->num_events);
 510         return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 511 }
 512
 513 /*
 514  * Callchain handling code.
 515  */
 516
 517 /*
 518  * The registers we're interested in are at the end of the variable
 519  * length saved register structure. The fp points at the end of this
 520  * structure so the address of this struct is:
 521  * (struct frame_tail *)(xxx->fp)-1
 522  *
 523  * This code has been adapted from the ARM OProfile support.
 524  */
 525 struct frame_tail {
 526         struct frame_tail __user *fp;
 527         unsigned long sp;
 528         unsigned long lr;
 529 } __attribute__((packed));
 530
 531 /*
 532  * Get the return address for a single stackframe and return a pointer to the
 533  * next frame tail.
 534  */
 535 static struct frame_tail __user *
 536 user_backtrace(struct frame_tail __user *tail,
 537                struct perf_callchain_entry *entry)
 538 {
 539         struct frame_tail buftail;
 540
 541         /* Also check accessibility of one struct frame_tail beyond */
 542         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 543                 return NULL;
 544         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 545                 return NULL;
 546
 547         perf_callchain_store(entry, buftail.lr);
 548
 549         /*
 550          * Frame pointers should strictly progress back up the stack
 551          * (towards higher addresses).
 552          */
 553         if (tail + 1 >= buftail.fp)
 554                 return NULL;
 555
 556         return buftail.fp - 1;
 557 }
 558
 559 void
 560 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 561 {
 562         struct frame_tail __user *tail;
 563
 564         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 565                 /* We don't support guest os callchain now */
 566                 return;
 567         }
 568
 569         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 570
 571         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 572                tail && !((unsigned long)tail & 0x3))
 573                 tail = user_backtrace(tail, entry);
 574 }
 575
 576 /*
 577  * Gets called by walk_stackframe() for every stackframe. This will be called
 578  * whist unwinding the stackframe and is like a subroutine return so we use
 579  * the PC.
 580  */
 581 static int
 582 callchain_trace(struct stackframe *fr,
 583                 void *data)
 584 {
 585         struct perf_callchain_entry *entry = data;
 586         perf_callchain_store(entry, fr->pc);
 587         return 0;
 588 }
 589
 590 void
 591 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 592 {
 593         struct stackframe fr;
 594
 595         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 596                 /* We don't support guest os callchain now */
 597                 return;
 598         }
 599
 600         fr.fp = regs->ARM_fp;
 601         fr.sp = regs->ARM_sp;
 602         fr.lr = regs->ARM_lr;
 603         fr.pc = regs->ARM_pc;
 604         walk_stackframe(&fr, callchain_trace, entry);
 605 }
 606
 607 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 608 {
 609         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
 610                 return perf_guest_cbs->get_guest_ip();
 611
 612         return instruction_pointer(regs);
 613 }
 614
 615 unsigned long perf_misc_flags(struct pt_regs *regs)
 616 {
 617         int misc = 0;
 618
 619         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 620                 if (perf_guest_cbs->is_user_mode())
 621                         misc |= PERF_RECORD_MISC_GUEST_USER;
 622                 else
 623                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
 624         } else {
 625                 if (user_mode(regs))
 626                         misc |= PERF_RECORD_MISC_USER;
 627                 else
 628                         misc |= PERF_RECORD_MISC_KERNEL;
 629         }
 630
 631         return misc;
 632 }