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MIPS: Print correct PC in trace dump after NMI exception
[linux-2.6.git] / arch / mips / kernel / traps.c
bloba17b6efb8bfe2ddcf8e6c794384e3a61d457acb8
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/context_tracking.h>
17 #include <linux/kexec.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mm.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/spinlock.h>
25 #include <linux/kallsyms.h>
26 #include <linux/bootmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/ptrace.h>
29 #include <linux/kgdb.h>
30 #include <linux/kdebug.h>
31 #include <linux/kprobes.h>
32 #include <linux/notifier.h>
33 #include <linux/kdb.h>
34 #include <linux/irq.h>
35 #include <linux/perf_event.h>
36
37 #include <asm/bootinfo.h>
38 #include <asm/branch.h>
39 #include <asm/break.h>
40 #include <asm/cop2.h>
41 #include <asm/cpu.h>
42 #include <asm/cpu-type.h>
43 #include <asm/dsp.h>
44 #include <asm/fpu.h>
45 #include <asm/fpu_emulator.h>
46 #include <asm/idle.h>
47 #include <asm/mipsregs.h>
48 #include <asm/mipsmtregs.h>
49 #include <asm/module.h>
50 #include <asm/pgtable.h>
51 #include <asm/ptrace.h>
52 #include <asm/sections.h>
53 #include <asm/tlbdebug.h>
54 #include <asm/traps.h>
55 #include <asm/uaccess.h>
56 #include <asm/watch.h>
57 #include <asm/mmu_context.h>
58 #include <asm/types.h>
59 #include <asm/stacktrace.h>
60 #include <asm/uasm.h>
61
62 extern void check_wait(void);
63 extern asmlinkage void rollback_handle_int(void);
64 extern asmlinkage void handle_int(void);
65 extern u32 handle_tlbl[];
66 extern u32 handle_tlbs[];
67 extern u32 handle_tlbm[];
68 extern asmlinkage void handle_adel(void);
69 extern asmlinkage void handle_ades(void);
70 extern asmlinkage void handle_ibe(void);
71 extern asmlinkage void handle_dbe(void);
72 extern asmlinkage void handle_sys(void);
73 extern asmlinkage void handle_bp(void);
74 extern asmlinkage void handle_ri(void);
75 extern asmlinkage void handle_ri_rdhwr_vivt(void);
76 extern asmlinkage void handle_ri_rdhwr(void);
77 extern asmlinkage void handle_cpu(void);
78 extern asmlinkage void handle_ov(void);
79 extern asmlinkage void handle_tr(void);
80 extern asmlinkage void handle_fpe(void);
81 extern asmlinkage void handle_mdmx(void);
82 extern asmlinkage void handle_watch(void);
83 extern asmlinkage void handle_mt(void);
84 extern asmlinkage void handle_dsp(void);
85 extern asmlinkage void handle_mcheck(void);
86 extern asmlinkage void handle_reserved(void);
87
88 void (*board_be_init)(void);
89 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
90 void (*board_nmi_handler_setup)(void);
91 void (*board_ejtag_handler_setup)(void);
92 void (*board_bind_eic_interrupt)(int irq, int regset);
93 void (*board_ebase_setup)(void);
94 void(*board_cache_error_setup)(void);
95
96 static void show_raw_backtrace(unsigned long reg29)
97 {
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
99 unsigned long addr;
100
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
103 printk("\n");
104 #endif
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112 if (__kernel_text_address(addr))
113 print_ip_sym(addr);
114 }
115 printk("\n");
116 }
117
118 #ifdef CONFIG_KALLSYMS
119 int raw_show_trace;
120 static int __init set_raw_show_trace(char *str)
121 {
122 raw_show_trace = 1;
123 return 1;
124 }
125 __setup("raw_show_trace", set_raw_show_trace);
126 #endif
127
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
129 {
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
133
134 if (!task)
135 task = current;
136
137 if (raw_show_trace || !__kernel_text_address(pc)) {
138 show_raw_backtrace(sp);
139 return;
140 }
141 printk("Call Trace:\n");
142 do {
143 print_ip_sym(pc);
144 pc = unwind_stack(task, &sp, pc, &ra);
145 } while (pc);
146 printk("\n");
147 }
148
149 /*
150 * This routine abuses get_user()/put_user() to reference pointers
151 * with at least a bit of error checking ...
152 */
153 static void show_stacktrace(struct task_struct *task,
154 const struct pt_regs *regs)
155 {
156 const int field = 2 * sizeof(unsigned long);
157 long stackdata;
158 int i;
159 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
160
161 printk("Stack :");
162 i = 0;
163 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
164 if (i && ((i % (64 / field)) == 0))
165 printk("\n ");
166 if (i > 39) {
167 printk(" ...");
168 break;
169 }
170
171 if (__get_user(stackdata, sp++)) {
172 printk(" (Bad stack address)");
173 break;
174 }
175
176 printk(" %0*lx", field, stackdata);
177 i++;
178 }
179 printk("\n");
180 show_backtrace(task, regs);
181 }
182
183 void show_stack(struct task_struct *task, unsigned long *sp)
184 {
185 struct pt_regs regs;
186 if (sp) {
187 regs.regs[29] = (unsigned long)sp;
188 regs.regs[31] = 0;
189 regs.cp0_epc = 0;
190 } else {
191 if (task && task != current) {
192 regs.regs[29] = task->thread.reg29;
193 regs.regs[31] = 0;
194 regs.cp0_epc = task->thread.reg31;
195 #ifdef CONFIG_KGDB_KDB
196 } else if (atomic_read(&kgdb_active) != -1 &&
197 kdb_current_regs) {
198 memcpy(&regs, kdb_current_regs, sizeof(regs));
199 #endif /* CONFIG_KGDB_KDB */
200 } else {
201 prepare_frametrace(&regs);
202 }
203 }
204 show_stacktrace(task, &regs);
205 }
206
207 static void show_code(unsigned int __user *pc)
208 {
209 long i;
210 unsigned short __user *pc16 = NULL;
211
212 printk("\nCode:");
213
214 if ((unsigned long)pc & 1)
215 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
216 for(i = -3 ; i < 6 ; i++) {
217 unsigned int insn;
218 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
219 printk(" (Bad address in epc)\n");
220 break;
221 }
222 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
223 }
224 }
225
226 static void __show_regs(const struct pt_regs *regs)
227 {
228 const int field = 2 * sizeof(unsigned long);
229 unsigned int cause = regs->cp0_cause;
230 int i;
231
232 show_regs_print_info(KERN_DEFAULT);
233
234 /*
235 * Saved main processor registers
236 */
237 for (i = 0; i < 32; ) {
238 if ((i % 4) == 0)
239 printk("$%2d :", i);
240 if (i == 0)
241 printk(" %0*lx", field, 0UL);
242 else if (i == 26 || i == 27)
243 printk(" %*s", field, "");
244 else
245 printk(" %0*lx", field, regs->regs[i]);
246
247 i++;
248 if ((i % 4) == 0)
249 printk("\n");
250 }
251
252 #ifdef CONFIG_CPU_HAS_SMARTMIPS
253 printk("Acx : %0*lx\n", field, regs->acx);
254 #endif
255 printk("Hi : %0*lx\n", field, regs->hi);
256 printk("Lo : %0*lx\n", field, regs->lo);
257
258 /*
259 * Saved cp0 registers
260 */
261 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
262 (void *) regs->cp0_epc);
263 printk(" %s\n", print_tainted());
264 printk("ra : %0*lx %pS\n", field, regs->regs[31],
265 (void *) regs->regs[31]);
266
267 printk("Status: %08x ", (uint32_t) regs->cp0_status);
268
269 if (cpu_has_3kex) {
270 if (regs->cp0_status & ST0_KUO)
271 printk("KUo ");
272 if (regs->cp0_status & ST0_IEO)
273 printk("IEo ");
274 if (regs->cp0_status & ST0_KUP)
275 printk("KUp ");
276 if (regs->cp0_status & ST0_IEP)
277 printk("IEp ");
278 if (regs->cp0_status & ST0_KUC)
279 printk("KUc ");
280 if (regs->cp0_status & ST0_IEC)
281 printk("IEc ");
282 } else if (cpu_has_4kex) {
283 if (regs->cp0_status & ST0_KX)
284 printk("KX ");
285 if (regs->cp0_status & ST0_SX)
286 printk("SX ");
287 if (regs->cp0_status & ST0_UX)
288 printk("UX ");
289 switch (regs->cp0_status & ST0_KSU) {
290 case KSU_USER:
291 printk("USER ");
292 break;
293 case KSU_SUPERVISOR:
294 printk("SUPERVISOR ");
295 break;
296 case KSU_KERNEL:
297 printk("KERNEL ");
298 break;
299 default:
300 printk("BAD_MODE ");
301 break;
302 }
303 if (regs->cp0_status & ST0_ERL)
304 printk("ERL ");
305 if (regs->cp0_status & ST0_EXL)
306 printk("EXL ");
307 if (regs->cp0_status & ST0_IE)
308 printk("IE ");
309 }
310 printk("\n");
311
312 printk("Cause : %08x\n", cause);
313
314 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
315 if (1 <= cause && cause <= 5)
316 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
317
318 printk("PrId : %08x (%s)\n", read_c0_prid(),
319 cpu_name_string());
320 }
321
322 /*
323 * FIXME: really the generic show_regs should take a const pointer argument.
324 */
325 void show_regs(struct pt_regs *regs)
326 {
327 __show_regs((struct pt_regs *)regs);
328 }
329
330 void show_registers(struct pt_regs *regs)
331 {
332 const int field = 2 * sizeof(unsigned long);
333 mm_segment_t old_fs = get_fs();
334
335 __show_regs(regs);
336 print_modules();
337 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
338 current->comm, current->pid, current_thread_info(), current,
339 field, current_thread_info()->tp_value);
340 if (cpu_has_userlocal) {
341 unsigned long tls;
342
343 tls = read_c0_userlocal();
344 if (tls != current_thread_info()->tp_value)
345 printk("*HwTLS: %0*lx\n", field, tls);
346 }
347
348 if (!user_mode(regs))
349 /* Necessary for getting the correct stack content */
350 set_fs(KERNEL_DS);
351 show_stacktrace(current, regs);
352 show_code((unsigned int __user *) regs->cp0_epc);
353 printk("\n");
354 set_fs(old_fs);
355 }
356
357 static int regs_to_trapnr(struct pt_regs *regs)
358 {
359 return (regs->cp0_cause >> 2) & 0x1f;
360 }
361
362 static DEFINE_RAW_SPINLOCK(die_lock);
363
364 void __noreturn die(const char *str, struct pt_regs *regs)
365 {
366 static int die_counter;
367 int sig = SIGSEGV;
368 #ifdef CONFIG_MIPS_MT_SMTC
369 unsigned long dvpret;
370 #endif /* CONFIG_MIPS_MT_SMTC */
371
372 oops_enter();
373
374 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
375 sig = 0;
376
377 console_verbose();
378 raw_spin_lock_irq(&die_lock);
379 #ifdef CONFIG_MIPS_MT_SMTC
380 dvpret = dvpe();
381 #endif /* CONFIG_MIPS_MT_SMTC */
382 bust_spinlocks(1);
383 #ifdef CONFIG_MIPS_MT_SMTC
384 mips_mt_regdump(dvpret);
385 #endif /* CONFIG_MIPS_MT_SMTC */
386
387 printk("%s[#%d]:\n", str, ++die_counter);
388 show_registers(regs);
389 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
390 raw_spin_unlock_irq(&die_lock);
391
392 oops_exit();
393
394 if (in_interrupt())
395 panic("Fatal exception in interrupt");
396
397 if (panic_on_oops) {
398 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
399 ssleep(5);
400 panic("Fatal exception");
401 }
402
403 if (regs && kexec_should_crash(current))
404 crash_kexec(regs);
405
406 do_exit(sig);
407 }
408
409 extern struct exception_table_entry __start___dbe_table[];
410 extern struct exception_table_entry __stop___dbe_table[];
411
412 __asm__(
413 " .section __dbe_table, \"a\"\n"
414 " .previous \n");
415
416 /* Given an address, look for it in the exception tables. */
417 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
418 {
419 const struct exception_table_entry *e;
420
421 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
422 if (!e)
423 e = search_module_dbetables(addr);
424 return e;
425 }
426
427 asmlinkage void do_be(struct pt_regs *regs)
428 {
429 const int field = 2 * sizeof(unsigned long);
430 const struct exception_table_entry *fixup = NULL;
431 int data = regs->cp0_cause & 4;
432 int action = MIPS_BE_FATAL;
433 enum ctx_state prev_state;
434
435 prev_state = exception_enter();
436 /* XXX For now. Fixme, this searches the wrong table ... */
437 if (data && !user_mode(regs))
438 fixup = search_dbe_tables(exception_epc(regs));
439
440 if (fixup)
441 action = MIPS_BE_FIXUP;
442
443 if (board_be_handler)
444 action = board_be_handler(regs, fixup != NULL);
445
446 switch (action) {
447 case MIPS_BE_DISCARD:
448 goto out;
449 case MIPS_BE_FIXUP:
450 if (fixup) {
451 regs->cp0_epc = fixup->nextinsn;
452 goto out;
453 }
454 break;
455 default:
456 break;
457 }
458
459 /*
460 * Assume it would be too dangerous to continue ...
461 */
462 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
463 data ? "Data" : "Instruction",
464 field, regs->cp0_epc, field, regs->regs[31]);
465 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
466 == NOTIFY_STOP)
467 goto out;
468
469 die_if_kernel("Oops", regs);
470 force_sig(SIGBUS, current);
471
472 out:
473 exception_exit(prev_state);
474 }
475
476 /*
477 * ll/sc, rdhwr, sync emulation
478 */
479
480 #define OPCODE 0xfc000000
481 #define BASE 0x03e00000
482 #define RT 0x001f0000
483 #define OFFSET 0x0000ffff
484 #define LL 0xc0000000
485 #define SC 0xe0000000
486 #define SPEC0 0x00000000
487 #define SPEC3 0x7c000000
488 #define RD 0x0000f800
489 #define FUNC 0x0000003f
490 #define SYNC 0x0000000f
491 #define RDHWR 0x0000003b
492
493 /* microMIPS definitions */
494 #define MM_POOL32A_FUNC 0xfc00ffff
495 #define MM_RDHWR 0x00006b3c
496 #define MM_RS 0x001f0000
497 #define MM_RT 0x03e00000
498
499 /*
500 * The ll_bit is cleared by r*_switch.S
501 */
502
503 unsigned int ll_bit;
504 struct task_struct *ll_task;
505
506 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
507 {
508 unsigned long value, __user *vaddr;
509 long offset;
510
511 /*
512 * analyse the ll instruction that just caused a ri exception
513 * and put the referenced address to addr.
514 */
515
516 /* sign extend offset */
517 offset = opcode & OFFSET;
518 offset <<= 16;
519 offset >>= 16;
520
521 vaddr = (unsigned long __user *)
522 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
523
524 if ((unsigned long)vaddr & 3)
525 return SIGBUS;
526 if (get_user(value, vaddr))
527 return SIGSEGV;
528
529 preempt_disable();
530
531 if (ll_task == NULL || ll_task == current) {
532 ll_bit = 1;
533 } else {
534 ll_bit = 0;
535 }
536 ll_task = current;
537
538 preempt_enable();
539
540 regs->regs[(opcode & RT) >> 16] = value;
541
542 return 0;
543 }
544
545 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
546 {
547 unsigned long __user *vaddr;
548 unsigned long reg;
549 long offset;
550
551 /*
552 * analyse the sc instruction that just caused a ri exception
553 * and put the referenced address to addr.
554 */
555
556 /* sign extend offset */
557 offset = opcode & OFFSET;
558 offset <<= 16;
559 offset >>= 16;
560
561 vaddr = (unsigned long __user *)
562 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
563 reg = (opcode & RT) >> 16;
564
565 if ((unsigned long)vaddr & 3)
566 return SIGBUS;
567
568 preempt_disable();
569
570 if (ll_bit == 0 || ll_task != current) {
571 regs->regs[reg] = 0;
572 preempt_enable();
573 return 0;
574 }
575
576 preempt_enable();
577
578 if (put_user(regs->regs[reg], vaddr))
579 return SIGSEGV;
580
581 regs->regs[reg] = 1;
582
583 return 0;
584 }
585
586 /*
587 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
588 * opcodes are supposed to result in coprocessor unusable exceptions if
589 * executed on ll/sc-less processors. That's the theory. In practice a
590 * few processors such as NEC's VR4100 throw reserved instruction exceptions
591 * instead, so we're doing the emulation thing in both exception handlers.
592 */
593 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
594 {
595 if ((opcode & OPCODE) == LL) {
596 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
597 1, regs, 0);
598 return simulate_ll(regs, opcode);
599 }
600 if ((opcode & OPCODE) == SC) {
601 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
602 1, regs, 0);
603 return simulate_sc(regs, opcode);
604 }
605
606 return -1; /* Must be something else ... */
607 }
608
609 /*
610 * Simulate trapping 'rdhwr' instructions to provide user accessible
611 * registers not implemented in hardware.
612 */
613 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
614 {
615 struct thread_info *ti = task_thread_info(current);
616
617 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
618 1, regs, 0);
619 switch (rd) {
620 case 0: /* CPU number */
621 regs->regs[rt] = smp_processor_id();
622 return 0;
623 case 1: /* SYNCI length */
624 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
625 current_cpu_data.icache.linesz);
626 return 0;
627 case 2: /* Read count register */
628 regs->regs[rt] = read_c0_count();
629 return 0;
630 case 3: /* Count register resolution */
631 switch (current_cpu_type()) {
632 case CPU_20KC:
633 case CPU_25KF:
634 regs->regs[rt] = 1;
635 break;
636 default:
637 regs->regs[rt] = 2;
638 }
639 return 0;
640 case 29:
641 regs->regs[rt] = ti->tp_value;
642 return 0;
643 default:
644 return -1;
645 }
646 }
647
648 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
649 {
650 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
651 int rd = (opcode & RD) >> 11;
652 int rt = (opcode & RT) >> 16;
653
654 simulate_rdhwr(regs, rd, rt);
655 return 0;
656 }
657
658 /* Not ours. */
659 return -1;
660 }
661
662 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
663 {
664 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
665 int rd = (opcode & MM_RS) >> 16;
666 int rt = (opcode & MM_RT) >> 21;
667 simulate_rdhwr(regs, rd, rt);
668 return 0;
669 }
670
671 /* Not ours. */
672 return -1;
673 }
674
675 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
676 {
677 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
678 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
679 1, regs, 0);
680 return 0;
681 }
682
683 return -1; /* Must be something else ... */
684 }
685
686 asmlinkage void do_ov(struct pt_regs *regs)
687 {
688 enum ctx_state prev_state;
689 siginfo_t info;
690
691 prev_state = exception_enter();
692 die_if_kernel("Integer overflow", regs);
693
694 info.si_code = FPE_INTOVF;
695 info.si_signo = SIGFPE;
696 info.si_errno = 0;
697 info.si_addr = (void __user *) regs->cp0_epc;
698 force_sig_info(SIGFPE, &info, current);
699 exception_exit(prev_state);
700 }
701
702 int process_fpemu_return(int sig, void __user *fault_addr)
703 {
704 if (sig == SIGSEGV || sig == SIGBUS) {
705 struct siginfo si = {0};
706 si.si_addr = fault_addr;
707 si.si_signo = sig;
708 if (sig == SIGSEGV) {
709 if (find_vma(current->mm, (unsigned long)fault_addr))
710 si.si_code = SEGV_ACCERR;
711 else
712 si.si_code = SEGV_MAPERR;
713 } else {
714 si.si_code = BUS_ADRERR;
715 }
716 force_sig_info(sig, &si, current);
717 return 1;
718 } else if (sig) {
719 force_sig(sig, current);
720 return 1;
721 } else {
722 return 0;
723 }
724 }
725
726 /*
727 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
728 */
729 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
730 {
731 enum ctx_state prev_state;
732 siginfo_t info = {0};
733
734 prev_state = exception_enter();
735 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
736 == NOTIFY_STOP)
737 goto out;
738 die_if_kernel("FP exception in kernel code", regs);
739
740 if (fcr31 & FPU_CSR_UNI_X) {
741 int sig;
742 void __user *fault_addr = NULL;
743
744 /*
745 * Unimplemented operation exception. If we've got the full
746 * software emulator on-board, let's use it...
747 *
748 * Force FPU to dump state into task/thread context. We're
749 * moving a lot of data here for what is probably a single
750 * instruction, but the alternative is to pre-decode the FP
751 * register operands before invoking the emulator, which seems
752 * a bit extreme for what should be an infrequent event.
753 */
754 /* Ensure 'resume' not overwrite saved fp context again. */
755 lose_fpu(1);
756
757 /* Run the emulator */
758 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
759 &fault_addr);
760
761 /*
762 * We can't allow the emulated instruction to leave any of
763 * the cause bit set in $fcr31.
764 */
765 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
766
767 /* Restore the hardware register state */
768 own_fpu(1); /* Using the FPU again. */
769
770 /* If something went wrong, signal */
771 process_fpemu_return(sig, fault_addr);
772
773 goto out;
774 } else if (fcr31 & FPU_CSR_INV_X)
775 info.si_code = FPE_FLTINV;
776 else if (fcr31 & FPU_CSR_DIV_X)
777 info.si_code = FPE_FLTDIV;
778 else if (fcr31 & FPU_CSR_OVF_X)
779 info.si_code = FPE_FLTOVF;
780 else if (fcr31 & FPU_CSR_UDF_X)
781 info.si_code = FPE_FLTUND;
782 else if (fcr31 & FPU_CSR_INE_X)
783 info.si_code = FPE_FLTRES;
784 else
785 info.si_code = __SI_FAULT;
786 info.si_signo = SIGFPE;
787 info.si_errno = 0;
788 info.si_addr = (void __user *) regs->cp0_epc;
789 force_sig_info(SIGFPE, &info, current);
790
791 out:
792 exception_exit(prev_state);
793 }
794
795 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
796 const char *str)
797 {
798 siginfo_t info;
799 char b[40];
800
801 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
802 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
803 return;
804 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
805
806 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
807 return;
808
809 /*
810 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
811 * insns, even for trap and break codes that indicate arithmetic
812 * failures. Weird ...
813 * But should we continue the brokenness??? --macro
814 */
815 switch (code) {
816 case BRK_OVERFLOW:
817 case BRK_DIVZERO:
818 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
819 die_if_kernel(b, regs);
820 if (code == BRK_DIVZERO)
821 info.si_code = FPE_INTDIV;
822 else
823 info.si_code = FPE_INTOVF;
824 info.si_signo = SIGFPE;
825 info.si_errno = 0;
826 info.si_addr = (void __user *) regs->cp0_epc;
827 force_sig_info(SIGFPE, &info, current);
828 break;
829 case BRK_BUG:
830 die_if_kernel("Kernel bug detected", regs);
831 force_sig(SIGTRAP, current);
832 break;
833 case BRK_MEMU:
834 /*
835 * Address errors may be deliberately induced by the FPU
836 * emulator to retake control of the CPU after executing the
837 * instruction in the delay slot of an emulated branch.
838 *
839 * Terminate if exception was recognized as a delay slot return
840 * otherwise handle as normal.
841 */
842 if (do_dsemulret(regs))
843 return;
844
845 die_if_kernel("Math emu break/trap", regs);
846 force_sig(SIGTRAP, current);
847 break;
848 default:
849 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
850 die_if_kernel(b, regs);
851 force_sig(SIGTRAP, current);
852 }
853 }
854
855 asmlinkage void do_bp(struct pt_regs *regs)
856 {
857 unsigned int opcode, bcode;
858 enum ctx_state prev_state;
859 unsigned long epc;
860 u16 instr[2];
861
862 prev_state = exception_enter();
863 if (get_isa16_mode(regs->cp0_epc)) {
864 /* Calculate EPC. */
865 epc = exception_epc(regs);
866 if (cpu_has_mmips) {
867 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
868 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
869 goto out_sigsegv;
870 opcode = (instr[0] << 16) | instr[1];
871 } else {
872 /* MIPS16e mode */
873 if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
874 goto out_sigsegv;
875 bcode = (instr[0] >> 6) & 0x3f;
876 do_trap_or_bp(regs, bcode, "Break");
877 goto out;
878 }
879 } else {
880 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
881 goto out_sigsegv;
882 }
883
884 /*
885 * There is the ancient bug in the MIPS assemblers that the break
886 * code starts left to bit 16 instead to bit 6 in the opcode.
887 * Gas is bug-compatible, but not always, grrr...
888 * We handle both cases with a simple heuristics. --macro
889 */
890 bcode = ((opcode >> 6) & ((1 << 20) - 1));
891 if (bcode >= (1 << 10))
892 bcode >>= 10;
893
894 /*
895 * notify the kprobe handlers, if instruction is likely to
896 * pertain to them.
897 */
898 switch (bcode) {
899 case BRK_KPROBE_BP:
900 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
901 goto out;
902 else
903 break;
904 case BRK_KPROBE_SSTEPBP:
905 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
906 goto out;
907 else
908 break;
909 default:
910 break;
911 }
912
913 do_trap_or_bp(regs, bcode, "Break");
914
915 out:
916 exception_exit(prev_state);
917 return;
918
919 out_sigsegv:
920 force_sig(SIGSEGV, current);
921 goto out;
922 }
923
924 asmlinkage void do_tr(struct pt_regs *regs)
925 {
926 u32 opcode, tcode = 0;
927 enum ctx_state prev_state;
928 u16 instr[2];
929 unsigned long epc = msk_isa16_mode(exception_epc(regs));
930
931 prev_state = exception_enter();
932 if (get_isa16_mode(regs->cp0_epc)) {
933 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
934 __get_user(instr[1], (u16 __user *)(epc + 2)))
935 goto out_sigsegv;
936 opcode = (instr[0] << 16) | instr[1];
937 /* Immediate versions don't provide a code. */
938 if (!(opcode & OPCODE))
939 tcode = (opcode >> 12) & ((1 << 4) - 1);
940 } else {
941 if (__get_user(opcode, (u32 __user *)epc))
942 goto out_sigsegv;
943 /* Immediate versions don't provide a code. */
944 if (!(opcode & OPCODE))
945 tcode = (opcode >> 6) & ((1 << 10) - 1);
946 }
947
948 do_trap_or_bp(regs, tcode, "Trap");
949
950 out:
951 exception_exit(prev_state);
952 return;
953
954 out_sigsegv:
955 force_sig(SIGSEGV, current);
956 goto out;
957 }
958
959 asmlinkage void do_ri(struct pt_regs *regs)
960 {
961 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
962 unsigned long old_epc = regs->cp0_epc;
963 unsigned long old31 = regs->regs[31];
964 enum ctx_state prev_state;
965 unsigned int opcode = 0;
966 int status = -1;
967
968 prev_state = exception_enter();
969 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
970 == NOTIFY_STOP)
971 goto out;
972
973 die_if_kernel("Reserved instruction in kernel code", regs);
974
975 if (unlikely(compute_return_epc(regs) < 0))
976 goto out;
977
978 if (get_isa16_mode(regs->cp0_epc)) {
979 unsigned short mmop[2] = { 0 };
980
981 if (unlikely(get_user(mmop[0], epc) < 0))
982 status = SIGSEGV;
983 if (unlikely(get_user(mmop[1], epc) < 0))
984 status = SIGSEGV;
985 opcode = (mmop[0] << 16) | mmop[1];
986
987 if (status < 0)
988 status = simulate_rdhwr_mm(regs, opcode);
989 } else {
990 if (unlikely(get_user(opcode, epc) < 0))
991 status = SIGSEGV;
992
993 if (!cpu_has_llsc && status < 0)
994 status = simulate_llsc(regs, opcode);
995
996 if (status < 0)
997 status = simulate_rdhwr_normal(regs, opcode);
998
999 if (status < 0)
1000 status = simulate_sync(regs, opcode);
1001 }
1002
1003 if (status < 0)
1004 status = SIGILL;
1005
1006 if (unlikely(status > 0)) {
1007 regs->cp0_epc = old_epc; /* Undo skip-over. */
1008 regs->regs[31] = old31;
1009 force_sig(status, current);
1010 }
1011
1012 out:
1013 exception_exit(prev_state);
1014 }
1015
1016 /*
1017 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1018 * emulated more than some threshold number of instructions, force migration to
1019 * a "CPU" that has FP support.
1020 */
1021 static void mt_ase_fp_affinity(void)
1022 {
1023 #ifdef CONFIG_MIPS_MT_FPAFF
1024 if (mt_fpemul_threshold > 0 &&
1025 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1026 /*
1027 * If there's no FPU present, or if the application has already
1028 * restricted the allowed set to exclude any CPUs with FPUs,
1029 * we'll skip the procedure.
1030 */
1031 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1032 cpumask_t tmask;
1033
1034 current->thread.user_cpus_allowed
1035 = current->cpus_allowed;
1036 cpus_and(tmask, current->cpus_allowed,
1037 mt_fpu_cpumask);
1038 set_cpus_allowed_ptr(current, &tmask);
1039 set_thread_flag(TIF_FPUBOUND);
1040 }
1041 }
1042 #endif /* CONFIG_MIPS_MT_FPAFF */
1043 }
1044
1045 /*
1046 * No lock; only written during early bootup by CPU 0.
1047 */
1048 static RAW_NOTIFIER_HEAD(cu2_chain);
1049
1050 int __ref register_cu2_notifier(struct notifier_block *nb)
1051 {
1052 return raw_notifier_chain_register(&cu2_chain, nb);
1053 }
1054
1055 int cu2_notifier_call_chain(unsigned long val, void *v)
1056 {
1057 return raw_notifier_call_chain(&cu2_chain, val, v);
1058 }
1059
1060 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1061 void *data)
1062 {
1063 struct pt_regs *regs = data;
1064
1065 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1066 "instruction", regs);
1067 force_sig(SIGILL, current);
1068
1069 return NOTIFY_OK;
1070 }
1071
1072 asmlinkage void do_cpu(struct pt_regs *regs)
1073 {
1074 enum ctx_state prev_state;
1075 unsigned int __user *epc;
1076 unsigned long old_epc, old31;
1077 unsigned int opcode;
1078 unsigned int cpid;
1079 int status;
1080 unsigned long __maybe_unused flags;
1081
1082 prev_state = exception_enter();
1083 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1084
1085 if (cpid != 2)
1086 die_if_kernel("do_cpu invoked from kernel context!", regs);
1087
1088 switch (cpid) {
1089 case 0:
1090 epc = (unsigned int __user *)exception_epc(regs);
1091 old_epc = regs->cp0_epc;
1092 old31 = regs->regs[31];
1093 opcode = 0;
1094 status = -1;
1095
1096 if (unlikely(compute_return_epc(regs) < 0))
1097 goto out;
1098
1099 if (get_isa16_mode(regs->cp0_epc)) {
1100 unsigned short mmop[2] = { 0 };
1101
1102 if (unlikely(get_user(mmop[0], epc) < 0))
1103 status = SIGSEGV;
1104 if (unlikely(get_user(mmop[1], epc) < 0))
1105 status = SIGSEGV;
1106 opcode = (mmop[0] << 16) | mmop[1];
1107
1108 if (status < 0)
1109 status = simulate_rdhwr_mm(regs, opcode);
1110 } else {
1111 if (unlikely(get_user(opcode, epc) < 0))
1112 status = SIGSEGV;
1113
1114 if (!cpu_has_llsc && status < 0)
1115 status = simulate_llsc(regs, opcode);
1116
1117 if (status < 0)
1118 status = simulate_rdhwr_normal(regs, opcode);
1119 }
1120
1121 if (status < 0)
1122 status = SIGILL;
1123
1124 if (unlikely(status > 0)) {
1125 regs->cp0_epc = old_epc; /* Undo skip-over. */
1126 regs->regs[31] = old31;
1127 force_sig(status, current);
1128 }
1129
1130 goto out;
1131
1132 case 3:
1133 /*
1134 * Old (MIPS I and MIPS II) processors will set this code
1135 * for COP1X opcode instructions that replaced the original
1136 * COP3 space. We don't limit COP1 space instructions in
1137 * the emulator according to the CPU ISA, so we want to
1138 * treat COP1X instructions consistently regardless of which
1139 * code the CPU chose. Therefore we redirect this trap to
1140 * the FP emulator too.
1141 *
1142 * Then some newer FPU-less processors use this code
1143 * erroneously too, so they are covered by this choice
1144 * as well.
1145 */
1146 if (raw_cpu_has_fpu)
1147 break;
1148 /* Fall through. */
1149
1150 case 1:
1151 if (used_math()) /* Using the FPU again. */
1152 own_fpu(1);
1153 else { /* First time FPU user. */
1154 init_fpu();
1155 set_used_math();
1156 }
1157
1158 if (!raw_cpu_has_fpu) {
1159 int sig;
1160 void __user *fault_addr = NULL;
1161 sig = fpu_emulator_cop1Handler(regs,
1162 &current->thread.fpu,
1163 0, &fault_addr);
1164 if (!process_fpemu_return(sig, fault_addr))
1165 mt_ase_fp_affinity();
1166 }
1167
1168 goto out;
1169
1170 case 2:
1171 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1172 goto out;
1173 }
1174
1175 force_sig(SIGILL, current);
1176
1177 out:
1178 exception_exit(prev_state);
1179 }
1180
1181 asmlinkage void do_mdmx(struct pt_regs *regs)
1182 {
1183 enum ctx_state prev_state;
1184
1185 prev_state = exception_enter();
1186 force_sig(SIGILL, current);
1187 exception_exit(prev_state);
1188 }
1189
1190 /*
1191 * Called with interrupts disabled.
1192 */
1193 asmlinkage void do_watch(struct pt_regs *regs)
1194 {
1195 enum ctx_state prev_state;
1196 u32 cause;
1197
1198 prev_state = exception_enter();
1199 /*
1200 * Clear WP (bit 22) bit of cause register so we don't loop
1201 * forever.
1202 */
1203 cause = read_c0_cause();
1204 cause &= ~(1 << 22);
1205 write_c0_cause(cause);
1206
1207 /*
1208 * If the current thread has the watch registers loaded, save
1209 * their values and send SIGTRAP. Otherwise another thread
1210 * left the registers set, clear them and continue.
1211 */
1212 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1213 mips_read_watch_registers();
1214 local_irq_enable();
1215 force_sig(SIGTRAP, current);
1216 } else {
1217 mips_clear_watch_registers();
1218 local_irq_enable();
1219 }
1220 exception_exit(prev_state);
1221 }
1222
1223 asmlinkage void do_mcheck(struct pt_regs *regs)
1224 {
1225 const int field = 2 * sizeof(unsigned long);
1226 int multi_match = regs->cp0_status & ST0_TS;
1227 enum ctx_state prev_state;
1228
1229 prev_state = exception_enter();
1230 show_regs(regs);
1231
1232 if (multi_match) {
1233 printk("Index : %0x\n", read_c0_index());
1234 printk("Pagemask: %0x\n", read_c0_pagemask());
1235 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1236 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1237 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1238 printk("\n");
1239 dump_tlb_all();
1240 }
1241
1242 show_code((unsigned int __user *) regs->cp0_epc);
1243
1244 /*
1245 * Some chips may have other causes of machine check (e.g. SB1
1246 * graduation timer)
1247 */
1248 panic("Caught Machine Check exception - %scaused by multiple "
1249 "matching entries in the TLB.",
1250 (multi_match) ? "" : "not ");
1251 }
1252
1253 asmlinkage void do_mt(struct pt_regs *regs)
1254 {
1255 int subcode;
1256
1257 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1258 >> VPECONTROL_EXCPT_SHIFT;
1259 switch (subcode) {
1260 case 0:
1261 printk(KERN_DEBUG "Thread Underflow\n");
1262 break;
1263 case 1:
1264 printk(KERN_DEBUG "Thread Overflow\n");
1265 break;
1266 case 2:
1267 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1268 break;
1269 case 3:
1270 printk(KERN_DEBUG "Gating Storage Exception\n");
1271 break;
1272 case 4:
1273 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1274 break;
1275 case 5:
1276 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1277 break;
1278 default:
1279 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1280 subcode);
1281 break;
1282 }
1283 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1284
1285 force_sig(SIGILL, current);
1286 }
1287
1288
1289 asmlinkage void do_dsp(struct pt_regs *regs)
1290 {
1291 if (cpu_has_dsp)
1292 panic("Unexpected DSP exception");
1293
1294 force_sig(SIGILL, current);
1295 }
1296
1297 asmlinkage void do_reserved(struct pt_regs *regs)
1298 {
1299 /*
1300 * Game over - no way to handle this if it ever occurs. Most probably
1301 * caused by a new unknown cpu type or after another deadly
1302 * hard/software error.
1303 */
1304 show_regs(regs);
1305 panic("Caught reserved exception %ld - should not happen.",
1306 (regs->cp0_cause & 0x7f) >> 2);
1307 }
1308
1309 static int __initdata l1parity = 1;
1310 static int __init nol1parity(char *s)
1311 {
1312 l1parity = 0;
1313 return 1;
1314 }
1315 __setup("nol1par", nol1parity);
1316 static int __initdata l2parity = 1;
1317 static int __init nol2parity(char *s)
1318 {
1319 l2parity = 0;
1320 return 1;
1321 }
1322 __setup("nol2par", nol2parity);
1323
1324 /*
1325 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1326 * it different ways.
1327 */
1328 static inline void parity_protection_init(void)
1329 {
1330 switch (current_cpu_type()) {
1331 case CPU_24K:
1332 case CPU_34K:
1333 case CPU_74K:
1334 case CPU_1004K:
1335 {
1336 #define ERRCTL_PE 0x80000000
1337 #define ERRCTL_L2P 0x00800000
1338 unsigned long errctl;
1339 unsigned int l1parity_present, l2parity_present;
1340
1341 errctl = read_c0_ecc();
1342 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1343
1344 /* probe L1 parity support */
1345 write_c0_ecc(errctl | ERRCTL_PE);
1346 back_to_back_c0_hazard();
1347 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1348
1349 /* probe L2 parity support */
1350 write_c0_ecc(errctl|ERRCTL_L2P);
1351 back_to_back_c0_hazard();
1352 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1353
1354 if (l1parity_present && l2parity_present) {
1355 if (l1parity)
1356 errctl |= ERRCTL_PE;
1357 if (l1parity ^ l2parity)
1358 errctl |= ERRCTL_L2P;
1359 } else if (l1parity_present) {
1360 if (l1parity)
1361 errctl |= ERRCTL_PE;
1362 } else if (l2parity_present) {
1363 if (l2parity)
1364 errctl |= ERRCTL_L2P;
1365 } else {
1366 /* No parity available */
1367 }
1368
1369 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1370
1371 write_c0_ecc(errctl);
1372 back_to_back_c0_hazard();
1373 errctl = read_c0_ecc();
1374 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1375
1376 if (l1parity_present)
1377 printk(KERN_INFO "Cache parity protection %sabled\n",
1378 (errctl & ERRCTL_PE) ? "en" : "dis");
1379
1380 if (l2parity_present) {
1381 if (l1parity_present && l1parity)
1382 errctl ^= ERRCTL_L2P;
1383 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1384 (errctl & ERRCTL_L2P) ? "en" : "dis");
1385 }
1386 }
1387 break;
1388
1389 case CPU_5KC:
1390 case CPU_5KE:
1391 case CPU_LOONGSON1:
1392 write_c0_ecc(0x80000000);
1393 back_to_back_c0_hazard();
1394 /* Set the PE bit (bit 31) in the c0_errctl register. */
1395 printk(KERN_INFO "Cache parity protection %sabled\n",
1396 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1397 break;
1398 case CPU_20KC:
1399 case CPU_25KF:
1400 /* Clear the DE bit (bit 16) in the c0_status register. */
1401 printk(KERN_INFO "Enable cache parity protection for "
1402 "MIPS 20KC/25KF CPUs.\n");
1403 clear_c0_status(ST0_DE);
1404 break;
1405 default:
1406 break;
1407 }
1408 }
1409
1410 asmlinkage void cache_parity_error(void)
1411 {
1412 const int field = 2 * sizeof(unsigned long);
1413 unsigned int reg_val;
1414
1415 /* For the moment, report the problem and hang. */
1416 printk("Cache error exception:\n");
1417 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1418 reg_val = read_c0_cacheerr();
1419 printk("c0_cacheerr == %08x\n", reg_val);
1420
1421 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1422 reg_val & (1<<30) ? "secondary" : "primary",
1423 reg_val & (1<<31) ? "data" : "insn");
1424 printk("Error bits: %s%s%s%s%s%s%s\n",
1425 reg_val & (1<<29) ? "ED " : "",
1426 reg_val & (1<<28) ? "ET " : "",
1427 reg_val & (1<<26) ? "EE " : "",
1428 reg_val & (1<<25) ? "EB " : "",
1429 reg_val & (1<<24) ? "EI " : "",
1430 reg_val & (1<<23) ? "E1 " : "",
1431 reg_val & (1<<22) ? "E0 " : "");
1432 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1433
1434 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1435 if (reg_val & (1<<22))
1436 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1437
1438 if (reg_val & (1<<23))
1439 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1440 #endif
1441
1442 panic("Can't handle the cache error!");
1443 }
1444
1445 /*
1446 * SDBBP EJTAG debug exception handler.
1447 * We skip the instruction and return to the next instruction.
1448 */
1449 void ejtag_exception_handler(struct pt_regs *regs)
1450 {
1451 const int field = 2 * sizeof(unsigned long);
1452 unsigned long depc, old_epc, old_ra;
1453 unsigned int debug;
1454
1455 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1456 depc = read_c0_depc();
1457 debug = read_c0_debug();
1458 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1459 if (debug & 0x80000000) {
1460 /*
1461 * In branch delay slot.
1462 * We cheat a little bit here and use EPC to calculate the
1463 * debug return address (DEPC). EPC is restored after the
1464 * calculation.
1465 */
1466 old_epc = regs->cp0_epc;
1467 old_ra = regs->regs[31];
1468 regs->cp0_epc = depc;
1469 compute_return_epc(regs);
1470 depc = regs->cp0_epc;
1471 regs->cp0_epc = old_epc;
1472 regs->regs[31] = old_ra;
1473 } else
1474 depc += 4;
1475 write_c0_depc(depc);
1476
1477 #if 0
1478 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1479 write_c0_debug(debug | 0x100);
1480 #endif
1481 }
1482
1483 /*
1484 * NMI exception handler.
1485 * No lock; only written during early bootup by CPU 0.
1486 */
1487 static RAW_NOTIFIER_HEAD(nmi_chain);
1488
1489 int register_nmi_notifier(struct notifier_block *nb)
1490 {
1491 return raw_notifier_chain_register(&nmi_chain, nb);
1492 }
1493
1494 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1495 {
1496 char str[100];
1497
1498 raw_notifier_call_chain(&nmi_chain, 0, regs);
1499 bust_spinlocks(1);
1500 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1501 smp_processor_id(), regs->cp0_epc);
1502 regs->cp0_epc = read_c0_errorepc();
1503 die(str, regs);
1504 }
1505
1506 #define VECTORSPACING 0x100 /* for EI/VI mode */
1507
1508 unsigned long ebase;
1509 unsigned long exception_handlers[32];
1510 unsigned long vi_handlers[64];
1511
1512 void __init *set_except_vector(int n, void *addr)
1513 {
1514 unsigned long handler = (unsigned long) addr;
1515 unsigned long old_handler;
1516
1517 #ifdef CONFIG_CPU_MICROMIPS
1518 /*
1519 * Only the TLB handlers are cache aligned with an even
1520 * address. All other handlers are on an odd address and
1521 * require no modification. Otherwise, MIPS32 mode will
1522 * be entered when handling any TLB exceptions. That
1523 * would be bad...since we must stay in microMIPS mode.
1524 */
1525 if (!(handler & 0x1))
1526 handler |= 1;
1527 #endif
1528 old_handler = xchg(&exception_handlers[n], handler);
1529
1530 if (n == 0 && cpu_has_divec) {
1531 #ifdef CONFIG_CPU_MICROMIPS
1532 unsigned long jump_mask = ~((1 << 27) - 1);
1533 #else
1534 unsigned long jump_mask = ~((1 << 28) - 1);
1535 #endif
1536 u32 *buf = (u32 *)(ebase + 0x200);
1537 unsigned int k0 = 26;
1538 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1539 uasm_i_j(&buf, handler & ~jump_mask);
1540 uasm_i_nop(&buf);
1541 } else {
1542 UASM_i_LA(&buf, k0, handler);
1543 uasm_i_jr(&buf, k0);
1544 uasm_i_nop(&buf);
1545 }
1546 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1547 }
1548 return (void *)old_handler;
1549 }
1550
1551 static void do_default_vi(void)
1552 {
1553 show_regs(get_irq_regs());
1554 panic("Caught unexpected vectored interrupt.");
1555 }
1556
1557 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1558 {
1559 unsigned long handler;
1560 unsigned long old_handler = vi_handlers[n];
1561 int srssets = current_cpu_data.srsets;
1562 u16 *h;
1563 unsigned char *b;
1564
1565 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1566
1567 if (addr == NULL) {
1568 handler = (unsigned long) do_default_vi;
1569 srs = 0;
1570 } else
1571 handler = (unsigned long) addr;
1572 vi_handlers[n] = handler;
1573
1574 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1575
1576 if (srs >= srssets)
1577 panic("Shadow register set %d not supported", srs);
1578
1579 if (cpu_has_veic) {
1580 if (board_bind_eic_interrupt)
1581 board_bind_eic_interrupt(n, srs);
1582 } else if (cpu_has_vint) {
1583 /* SRSMap is only defined if shadow sets are implemented */
1584 if (srssets > 1)
1585 change_c0_srsmap(0xf << n*4, srs << n*4);
1586 }
1587
1588 if (srs == 0) {
1589 /*
1590 * If no shadow set is selected then use the default handler
1591 * that does normal register saving and standard interrupt exit
1592 */
1593 extern char except_vec_vi, except_vec_vi_lui;
1594 extern char except_vec_vi_ori, except_vec_vi_end;
1595 extern char rollback_except_vec_vi;
1596 char *vec_start = using_rollback_handler() ?
1597 &rollback_except_vec_vi : &except_vec_vi;
1598 #ifdef CONFIG_MIPS_MT_SMTC
1599 /*
1600 * We need to provide the SMTC vectored interrupt handler
1601 * not only with the address of the handler, but with the
1602 * Status.IM bit to be masked before going there.
1603 */
1604 extern char except_vec_vi_mori;
1605 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1606 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1607 #else
1608 const int mori_offset = &except_vec_vi_mori - vec_start;
1609 #endif
1610 #endif /* CONFIG_MIPS_MT_SMTC */
1611 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1612 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1613 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1614 #else
1615 const int lui_offset = &except_vec_vi_lui - vec_start;
1616 const int ori_offset = &except_vec_vi_ori - vec_start;
1617 #endif
1618 const int handler_len = &except_vec_vi_end - vec_start;
1619
1620 if (handler_len > VECTORSPACING) {
1621 /*
1622 * Sigh... panicing won't help as the console
1623 * is probably not configured :(
1624 */
1625 panic("VECTORSPACING too small");
1626 }
1627
1628 set_handler(((unsigned long)b - ebase), vec_start,
1629 #ifdef CONFIG_CPU_MICROMIPS
1630 (handler_len - 1));
1631 #else
1632 handler_len);
1633 #endif
1634 #ifdef CONFIG_MIPS_MT_SMTC
1635 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1636
1637 h = (u16 *)(b + mori_offset);
1638 *h = (0x100 << n);
1639 #endif /* CONFIG_MIPS_MT_SMTC */
1640 h = (u16 *)(b + lui_offset);
1641 *h = (handler >> 16) & 0xffff;
1642 h = (u16 *)(b + ori_offset);
1643 *h = (handler & 0xffff);
1644 local_flush_icache_range((unsigned long)b,
1645 (unsigned long)(b+handler_len));
1646 }
1647 else {
1648 /*
1649 * In other cases jump directly to the interrupt handler. It
1650 * is the handler's responsibility to save registers if required
1651 * (eg hi/lo) and return from the exception using "eret".
1652 */
1653 u32 insn;
1654
1655 h = (u16 *)b;
1656 /* j handler */
1657 #ifdef CONFIG_CPU_MICROMIPS
1658 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1659 #else
1660 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1661 #endif
1662 h[0] = (insn >> 16) & 0xffff;
1663 h[1] = insn & 0xffff;
1664 h[2] = 0;
1665 h[3] = 0;
1666 local_flush_icache_range((unsigned long)b,
1667 (unsigned long)(b+8));
1668 }
1669
1670 return (void *)old_handler;
1671 }
1672
1673 void *set_vi_handler(int n, vi_handler_t addr)
1674 {
1675 return set_vi_srs_handler(n, addr, 0);
1676 }
1677
1678 extern void tlb_init(void);
1679
1680 /*
1681 * Timer interrupt
1682 */
1683 int cp0_compare_irq;
1684 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1685 int cp0_compare_irq_shift;
1686
1687 /*
1688 * Performance counter IRQ or -1 if shared with timer
1689 */
1690 int cp0_perfcount_irq;
1691 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1692
1693 static int noulri;
1694
1695 static int __init ulri_disable(char *s)
1696 {
1697 pr_info("Disabling ulri\n");
1698 noulri = 1;
1699
1700 return 1;
1701 }
1702 __setup("noulri", ulri_disable);
1703
1704 void per_cpu_trap_init(bool is_boot_cpu)
1705 {
1706 unsigned int cpu = smp_processor_id();
1707 unsigned int status_set = ST0_CU0;
1708 unsigned int hwrena = cpu_hwrena_impl_bits;
1709 #ifdef CONFIG_MIPS_MT_SMTC
1710 int secondaryTC = 0;
1711 int bootTC = (cpu == 0);
1712
1713 /*
1714 * Only do per_cpu_trap_init() for first TC of Each VPE.
1715 * Note that this hack assumes that the SMTC init code
1716 * assigns TCs consecutively and in ascending order.
1717 */
1718
1719 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1720 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1721 secondaryTC = 1;
1722 #endif /* CONFIG_MIPS_MT_SMTC */
1723
1724 /*
1725 * Disable coprocessors and select 32-bit or 64-bit addressing
1726 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1727 * flag that some firmware may have left set and the TS bit (for
1728 * IP27). Set XX for ISA IV code to work.
1729 */
1730 #ifdef CONFIG_64BIT
1731 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1732 #endif
1733 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1734 status_set |= ST0_XX;
1735 if (cpu_has_dsp)
1736 status_set |= ST0_MX;
1737
1738 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1739 status_set);
1740
1741 if (cpu_has_mips_r2)
1742 hwrena |= 0x0000000f;
1743
1744 if (!noulri && cpu_has_userlocal)
1745 hwrena |= (1 << 29);
1746
1747 if (hwrena)
1748 write_c0_hwrena(hwrena);
1749
1750 #ifdef CONFIG_MIPS_MT_SMTC
1751 if (!secondaryTC) {
1752 #endif /* CONFIG_MIPS_MT_SMTC */
1753
1754 if (cpu_has_veic || cpu_has_vint) {
1755 unsigned long sr = set_c0_status(ST0_BEV);
1756 write_c0_ebase(ebase);
1757 write_c0_status(sr);
1758 /* Setting vector spacing enables EI/VI mode */
1759 change_c0_intctl(0x3e0, VECTORSPACING);
1760 }
1761 if (cpu_has_divec) {
1762 if (cpu_has_mipsmt) {
1763 unsigned int vpflags = dvpe();
1764 set_c0_cause(CAUSEF_IV);
1765 evpe(vpflags);
1766 } else
1767 set_c0_cause(CAUSEF_IV);
1768 }
1769
1770 /*
1771 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1772 *
1773 * o read IntCtl.IPTI to determine the timer interrupt
1774 * o read IntCtl.IPPCI to determine the performance counter interrupt
1775 */
1776 if (cpu_has_mips_r2) {
1777 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1778 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1779 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1780 if (cp0_perfcount_irq == cp0_compare_irq)
1781 cp0_perfcount_irq = -1;
1782 } else {
1783 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1784 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1785 cp0_perfcount_irq = -1;
1786 }
1787
1788 #ifdef CONFIG_MIPS_MT_SMTC
1789 }
1790 #endif /* CONFIG_MIPS_MT_SMTC */
1791
1792 if (!cpu_data[cpu].asid_cache)
1793 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1794
1795 atomic_inc(&init_mm.mm_count);
1796 current->active_mm = &init_mm;
1797 BUG_ON(current->mm);
1798 enter_lazy_tlb(&init_mm, current);
1799
1800 #ifdef CONFIG_MIPS_MT_SMTC
1801 if (bootTC) {
1802 #endif /* CONFIG_MIPS_MT_SMTC */
1803 /* Boot CPU's cache setup in setup_arch(). */
1804 if (!is_boot_cpu)
1805 cpu_cache_init();
1806 tlb_init();
1807 #ifdef CONFIG_MIPS_MT_SMTC
1808 } else if (!secondaryTC) {
1809 /*
1810 * First TC in non-boot VPE must do subset of tlb_init()
1811 * for MMU countrol registers.
1812 */
1813 write_c0_pagemask(PM_DEFAULT_MASK);
1814 write_c0_wired(0);
1815 }
1816 #endif /* CONFIG_MIPS_MT_SMTC */
1817 TLBMISS_HANDLER_SETUP();
1818 }
1819
1820 /* Install CPU exception handler */
1821 void set_handler(unsigned long offset, void *addr, unsigned long size)
1822 {
1823 #ifdef CONFIG_CPU_MICROMIPS
1824 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1825 #else
1826 memcpy((void *)(ebase + offset), addr, size);
1827 #endif
1828 local_flush_icache_range(ebase + offset, ebase + offset + size);
1829 }
1830
1831 static char panic_null_cerr[] =
1832 "Trying to set NULL cache error exception handler";
1833
1834 /*
1835 * Install uncached CPU exception handler.
1836 * This is suitable only for the cache error exception which is the only
1837 * exception handler that is being run uncached.
1838 */
1839 void set_uncached_handler(unsigned long offset, void *addr,
1840 unsigned long size)
1841 {
1842 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1843
1844 if (!addr)
1845 panic(panic_null_cerr);
1846
1847 memcpy((void *)(uncached_ebase + offset), addr, size);
1848 }
1849
1850 static int __initdata rdhwr_noopt;
1851 static int __init set_rdhwr_noopt(char *str)
1852 {
1853 rdhwr_noopt = 1;
1854 return 1;
1855 }
1856
1857 __setup("rdhwr_noopt", set_rdhwr_noopt);
1858
1859 void __init trap_init(void)
1860 {
1861 extern char except_vec3_generic;
1862 extern char except_vec4;
1863 extern char except_vec3_r4000;
1864 unsigned long i;
1865
1866 check_wait();
1867
1868 #if defined(CONFIG_KGDB)
1869 if (kgdb_early_setup)
1870 return; /* Already done */
1871 #endif
1872
1873 if (cpu_has_veic || cpu_has_vint) {
1874 unsigned long size = 0x200 + VECTORSPACING*64;
1875 ebase = (unsigned long)
1876 __alloc_bootmem(size, 1 << fls(size), 0);
1877 } else {
1878 #ifdef CONFIG_KVM_GUEST
1879 #define KVM_GUEST_KSEG0 0x40000000
1880 ebase = KVM_GUEST_KSEG0;
1881 #else
1882 ebase = CKSEG0;
1883 #endif
1884 if (cpu_has_mips_r2)
1885 ebase += (read_c0_ebase() & 0x3ffff000);
1886 }
1887
1888 if (cpu_has_mmips) {
1889 unsigned int config3 = read_c0_config3();
1890
1891 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1892 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1893 else
1894 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1895 }
1896
1897 if (board_ebase_setup)
1898 board_ebase_setup();
1899 per_cpu_trap_init(true);
1900
1901 /*
1902 * Copy the generic exception handlers to their final destination.
1903 * This will be overriden later as suitable for a particular
1904 * configuration.
1905 */
1906 set_handler(0x180, &except_vec3_generic, 0x80);
1907
1908 /*
1909 * Setup default vectors
1910 */
1911 for (i = 0; i <= 31; i++)
1912 set_except_vector(i, handle_reserved);
1913
1914 /*
1915 * Copy the EJTAG debug exception vector handler code to it's final
1916 * destination.
1917 */
1918 if (cpu_has_ejtag && board_ejtag_handler_setup)
1919 board_ejtag_handler_setup();
1920
1921 /*
1922 * Only some CPUs have the watch exceptions.
1923 */
1924 if (cpu_has_watch)
1925 set_except_vector(23, handle_watch);
1926
1927 /*
1928 * Initialise interrupt handlers
1929 */
1930 if (cpu_has_veic || cpu_has_vint) {
1931 int nvec = cpu_has_veic ? 64 : 8;
1932 for (i = 0; i < nvec; i++)
1933 set_vi_handler(i, NULL);
1934 }
1935 else if (cpu_has_divec)
1936 set_handler(0x200, &except_vec4, 0x8);
1937
1938 /*
1939 * Some CPUs can enable/disable for cache parity detection, but does
1940 * it different ways.
1941 */
1942 parity_protection_init();
1943
1944 /*
1945 * The Data Bus Errors / Instruction Bus Errors are signaled
1946 * by external hardware. Therefore these two exceptions
1947 * may have board specific handlers.
1948 */
1949 if (board_be_init)
1950 board_be_init();
1951
1952 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
1953 : handle_int);
1954 set_except_vector(1, handle_tlbm);
1955 set_except_vector(2, handle_tlbl);
1956 set_except_vector(3, handle_tlbs);
1957
1958 set_except_vector(4, handle_adel);
1959 set_except_vector(5, handle_ades);
1960
1961 set_except_vector(6, handle_ibe);
1962 set_except_vector(7, handle_dbe);
1963
1964 set_except_vector(8, handle_sys);
1965 set_except_vector(9, handle_bp);
1966 set_except_vector(10, rdhwr_noopt ? handle_ri :
1967 (cpu_has_vtag_icache ?
1968 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1969 set_except_vector(11, handle_cpu);
1970 set_except_vector(12, handle_ov);
1971 set_except_vector(13, handle_tr);
1972
1973 if (current_cpu_type() == CPU_R6000 ||
1974 current_cpu_type() == CPU_R6000A) {
1975 /*
1976 * The R6000 is the only R-series CPU that features a machine
1977 * check exception (similar to the R4000 cache error) and
1978 * unaligned ldc1/sdc1 exception. The handlers have not been
1979 * written yet. Well, anyway there is no R6000 machine on the
1980 * current list of targets for Linux/MIPS.
1981 * (Duh, crap, there is someone with a triple R6k machine)
1982 */
1983 //set_except_vector(14, handle_mc);
1984 //set_except_vector(15, handle_ndc);
1985 }
1986
1987
1988 if (board_nmi_handler_setup)
1989 board_nmi_handler_setup();
1990
1991 if (cpu_has_fpu && !cpu_has_nofpuex)
1992 set_except_vector(15, handle_fpe);
1993
1994 set_except_vector(22, handle_mdmx);
1995
1996 if (cpu_has_mcheck)
1997 set_except_vector(24, handle_mcheck);
1998
1999 if (cpu_has_mipsmt)
2000 set_except_vector(25, handle_mt);
2001
2002 set_except_vector(26, handle_dsp);
2003
2004 if (board_cache_error_setup)
2005 board_cache_error_setup();
2006
2007 if (cpu_has_vce)
2008 /* Special exception: R4[04]00 uses also the divec space. */
2009 set_handler(0x180, &except_vec3_r4000, 0x100);
2010 else if (cpu_has_4kex)
2011 set_handler(0x180, &except_vec3_generic, 0x80);
2012 else
2013 set_handler(0x080, &except_vec3_generic, 0x80);
2014
2015 local_flush_icache_range(ebase, ebase + 0x400);
2016
2017 sort_extable(__start___dbe_table, __stop___dbe_table);
2018
2019 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2020 }
Linus' kernel tree