2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, 2011, Broadcom Corporation
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/export.h>
14 #include <linux/bcma/bcma.h>
16 u32
bcma_chipco_pll_read(struct bcma_drv_cc
*cc
, u32 offset
)
18 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
19 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
20 return bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
22 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read
);
24 void bcma_chipco_pll_write(struct bcma_drv_cc
*cc
, u32 offset
, u32 value
)
26 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
27 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
28 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, value
);
30 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write
);
32 void bcma_chipco_pll_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
35 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
36 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
37 bcma_cc_maskset32(cc
, BCMA_CC_PLLCTL_DATA
, mask
, set
);
39 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset
);
41 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc
*cc
,
42 u32 offset
, u32 mask
, u32 set
)
44 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL_ADDR
, offset
);
45 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_ADDR
);
46 bcma_cc_maskset32(cc
, BCMA_CC_CHIPCTL_DATA
, mask
, set
);
48 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset
);
50 void bcma_chipco_regctl_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
53 bcma_cc_write32(cc
, BCMA_CC_REGCTL_ADDR
, offset
);
54 bcma_cc_read32(cc
, BCMA_CC_REGCTL_ADDR
);
55 bcma_cc_maskset32(cc
, BCMA_CC_REGCTL_DATA
, mask
, set
);
57 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset
);
59 static void bcma_pmu_resources_init(struct bcma_drv_cc
*cc
)
61 struct bcma_bus
*bus
= cc
->core
->bus
;
62 u32 min_msk
= 0, max_msk
= 0;
64 switch (bus
->chipinfo
.id
) {
65 case BCMA_CHIP_ID_BCM4313
:
70 bcma_debug(bus
, "PMU resource config unknown or not needed for device 0x%04X\n",
74 /* Set the resource masks. */
76 bcma_cc_write32(cc
, BCMA_CC_PMU_MINRES_MSK
, min_msk
);
78 bcma_cc_write32(cc
, BCMA_CC_PMU_MAXRES_MSK
, max_msk
);
81 * Add some delay; allow resources to come up and settle.
82 * Delay is required for SoC (early init).
87 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
88 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc
*cc
, bool enable
)
90 struct bcma_bus
*bus
= cc
->core
->bus
;
93 val
= bcma_cc_read32(cc
, BCMA_CC_CHIPCTL
);
95 val
|= BCMA_CHIPCTL_4331_EXTPA_EN
;
96 if (bus
->chipinfo
.pkg
== 9 || bus
->chipinfo
.pkg
== 11)
97 val
|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
98 else if (bus
->chipinfo
.rev
> 0)
99 val
|= BCMA_CHIPCTL_4331_EXTPA_EN2
;
101 val
&= ~BCMA_CHIPCTL_4331_EXTPA_EN
;
102 val
&= ~BCMA_CHIPCTL_4331_EXTPA_EN2
;
103 val
&= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
105 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL
, val
);
108 static void bcma_pmu_workarounds(struct bcma_drv_cc
*cc
)
110 struct bcma_bus
*bus
= cc
->core
->bus
;
112 switch (bus
->chipinfo
.id
) {
113 case BCMA_CHIP_ID_BCM4313
:
114 /* enable 12 mA drive strenth for 4313 and set chipControl
116 bcma_chipco_chipctl_maskset(cc
, 0,
117 ~BCMA_CCTRL_4313_12MA_LED_DRIVE
,
118 BCMA_CCTRL_4313_12MA_LED_DRIVE
);
120 case BCMA_CHIP_ID_BCM4331
:
121 case BCMA_CHIP_ID_BCM43431
:
122 /* Ext PA lines must be enabled for tx on BCM4331 */
123 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc
, true);
125 case BCMA_CHIP_ID_BCM43224
:
126 case BCMA_CHIP_ID_BCM43421
:
127 /* enable 12 mA drive strenth for 43224 and set chipControl
129 if (bus
->chipinfo
.rev
== 0) {
130 bcma_cc_maskset32(cc
, BCMA_CC_CHIPCTL
,
131 ~BCMA_CCTRL_43224_GPIO_TOGGLE
,
132 BCMA_CCTRL_43224_GPIO_TOGGLE
);
133 bcma_chipco_chipctl_maskset(cc
, 0,
134 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE
,
135 BCMA_CCTRL_43224A0_12MA_LED_DRIVE
);
137 bcma_chipco_chipctl_maskset(cc
, 0,
138 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE
,
139 BCMA_CCTRL_43224B0_12MA_LED_DRIVE
);
143 bcma_debug(bus
, "Workarounds unknown or not needed for device 0x%04X\n",
148 void bcma_pmu_early_init(struct bcma_drv_cc
*cc
)
152 pmucap
= bcma_cc_read32(cc
, BCMA_CC_PMU_CAP
);
153 cc
->pmu
.rev
= (pmucap
& BCMA_CC_PMU_CAP_REVISION
);
155 bcma_debug(cc
->core
->bus
, "Found rev %u PMU (capabilities 0x%08X)\n",
156 cc
->pmu
.rev
, pmucap
);
159 void bcma_pmu_init(struct bcma_drv_cc
*cc
)
161 if (cc
->pmu
.rev
== 1)
162 bcma_cc_mask32(cc
, BCMA_CC_PMU_CTL
,
163 ~BCMA_CC_PMU_CTL_NOILPONW
);
165 bcma_cc_set32(cc
, BCMA_CC_PMU_CTL
,
166 BCMA_CC_PMU_CTL_NOILPONW
);
168 bcma_pmu_resources_init(cc
);
169 bcma_pmu_workarounds(cc
);
172 u32
bcma_pmu_get_alp_clock(struct bcma_drv_cc
*cc
)
174 struct bcma_bus
*bus
= cc
->core
->bus
;
176 switch (bus
->chipinfo
.id
) {
177 case BCMA_CHIP_ID_BCM4313
:
178 case BCMA_CHIP_ID_BCM43224
:
179 case BCMA_CHIP_ID_BCM43225
:
180 case BCMA_CHIP_ID_BCM43227
:
181 case BCMA_CHIP_ID_BCM43228
:
182 case BCMA_CHIP_ID_BCM4331
:
183 case BCMA_CHIP_ID_BCM43421
:
184 case BCMA_CHIP_ID_BCM43428
:
185 case BCMA_CHIP_ID_BCM43431
:
186 case BCMA_CHIP_ID_BCM4716
:
187 case BCMA_CHIP_ID_BCM47162
:
188 case BCMA_CHIP_ID_BCM4748
:
189 case BCMA_CHIP_ID_BCM4749
:
190 case BCMA_CHIP_ID_BCM5357
:
191 case BCMA_CHIP_ID_BCM53572
:
192 case BCMA_CHIP_ID_BCM6362
:
195 case BCMA_CHIP_ID_BCM4706
:
196 case BCMA_CHIP_ID_BCM5356
:
199 case BCMA_CHIP_ID_BCM43460
:
200 case BCMA_CHIP_ID_BCM4352
:
201 case BCMA_CHIP_ID_BCM4360
:
202 if (cc
->status
& BCMA_CC_CHIPST_4360_XTAL_40MZ
)
207 bcma_warn(bus
, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
208 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_ALP_CLOCK
);
210 return BCMA_CC_PMU_ALP_CLOCK
;
213 /* Find the output of the "m" pll divider given pll controls that start with
214 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
216 static u32
bcma_pmu_pll_clock(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
218 u32 tmp
, div
, ndiv
, p1
, p2
, fc
;
219 struct bcma_bus
*bus
= cc
->core
->bus
;
221 BUG_ON((pll0
& 3) || (pll0
> BCMA_CC_PMU4716_MAINPLL_PLL0
));
225 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM5357
||
226 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4749
) {
227 /* Detect failure in clock setting */
228 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
230 return 133 * 1000000;
233 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_P1P2_OFF
);
234 p1
= (tmp
& BCMA_CC_PPL_P1_MASK
) >> BCMA_CC_PPL_P1_SHIFT
;
235 p2
= (tmp
& BCMA_CC_PPL_P2_MASK
) >> BCMA_CC_PPL_P2_SHIFT
;
237 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_M14_OFF
);
238 div
= (tmp
>> ((m
- 1) * BCMA_CC_PPL_MDIV_WIDTH
)) &
239 BCMA_CC_PPL_MDIV_MASK
;
241 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_NM5_OFF
);
242 ndiv
= (tmp
& BCMA_CC_PPL_NDIV_MASK
) >> BCMA_CC_PPL_NDIV_SHIFT
;
244 /* Do calculation in Mhz */
245 fc
= bcma_pmu_get_alp_clock(cc
) / 1000000;
246 fc
= (p1
* ndiv
* fc
) / p2
;
248 /* Return clock in Hertz */
249 return (fc
/ div
) * 1000000;
252 static u32
bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
254 u32 tmp
, ndiv
, p1div
, p2div
;
259 /* Get N, P1 and P2 dividers to determine CPU clock */
260 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PMU6_4706_PROCPLL_OFF
);
261 ndiv
= (tmp
& BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK
)
262 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT
;
263 p1div
= (tmp
& BCMA_CC_PMU6_4706_PROC_P1DIV_MASK
)
264 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT
;
265 p2div
= (tmp
& BCMA_CC_PMU6_4706_PROC_P2DIV_MASK
)
266 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT
;
268 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
269 if (tmp
& BCMA_CC_CHIPST_4706_PKG_OPTION
)
270 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
271 clock
= (25000000 / 4) * ndiv
* p2div
/ p1div
;
273 /* Fixed reference clock 25MHz and m = 2 */
274 clock
= (25000000 / 2) * ndiv
* p2div
/ p1div
;
276 if (m
== BCMA_CC_PMU5_MAINPLL_SSB
)
282 /* query bus clock frequency for PMU-enabled chipcommon */
283 u32
bcma_pmu_get_bus_clock(struct bcma_drv_cc
*cc
)
285 struct bcma_bus
*bus
= cc
->core
->bus
;
287 switch (bus
->chipinfo
.id
) {
288 case BCMA_CHIP_ID_BCM4716
:
289 case BCMA_CHIP_ID_BCM4748
:
290 case BCMA_CHIP_ID_BCM47162
:
291 return bcma_pmu_pll_clock(cc
, BCMA_CC_PMU4716_MAINPLL_PLL0
,
292 BCMA_CC_PMU5_MAINPLL_SSB
);
293 case BCMA_CHIP_ID_BCM5356
:
294 return bcma_pmu_pll_clock(cc
, BCMA_CC_PMU5356_MAINPLL_PLL0
,
295 BCMA_CC_PMU5_MAINPLL_SSB
);
296 case BCMA_CHIP_ID_BCM5357
:
297 case BCMA_CHIP_ID_BCM4749
:
298 return bcma_pmu_pll_clock(cc
, BCMA_CC_PMU5357_MAINPLL_PLL0
,
299 BCMA_CC_PMU5_MAINPLL_SSB
);
300 case BCMA_CHIP_ID_BCM4706
:
301 return bcma_pmu_pll_clock_bcm4706(cc
,
302 BCMA_CC_PMU4706_MAINPLL_PLL0
,
303 BCMA_CC_PMU5_MAINPLL_SSB
);
304 case BCMA_CHIP_ID_BCM53572
:
307 bcma_warn(bus
, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
308 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_HT_CLOCK
);
310 return BCMA_CC_PMU_HT_CLOCK
;
312 EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock
);
314 /* query cpu clock frequency for PMU-enabled chipcommon */
315 u32
bcma_pmu_get_cpu_clock(struct bcma_drv_cc
*cc
)
317 struct bcma_bus
*bus
= cc
->core
->bus
;
319 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM53572
)
322 /* New PMUs can have different clock for bus and CPU */
323 if (cc
->pmu
.rev
>= 5) {
325 switch (bus
->chipinfo
.id
) {
326 case BCMA_CHIP_ID_BCM4706
:
327 return bcma_pmu_pll_clock_bcm4706(cc
,
328 BCMA_CC_PMU4706_MAINPLL_PLL0
,
329 BCMA_CC_PMU5_MAINPLL_CPU
);
330 case BCMA_CHIP_ID_BCM5356
:
331 pll
= BCMA_CC_PMU5356_MAINPLL_PLL0
;
333 case BCMA_CHIP_ID_BCM5357
:
334 case BCMA_CHIP_ID_BCM4749
:
335 pll
= BCMA_CC_PMU5357_MAINPLL_PLL0
;
338 pll
= BCMA_CC_PMU4716_MAINPLL_PLL0
;
342 return bcma_pmu_pll_clock(cc
, pll
, BCMA_CC_PMU5_MAINPLL_CPU
);
345 /* On old PMUs CPU has the same clock as the bus */
346 return bcma_pmu_get_bus_clock(cc
);
349 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc
*cc
, u32 offset
,
352 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
353 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, value
);
356 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc
*cc
, int spuravoid
)
359 u8 phypll_offset
= 0;
360 u8 bcm5357_bcm43236_p1div
[] = {0x1, 0x5, 0x5};
361 u8 bcm5357_bcm43236_ndiv
[] = {0x30, 0xf6, 0xfc};
362 struct bcma_bus
*bus
= cc
->core
->bus
;
364 switch (bus
->chipinfo
.id
) {
365 case BCMA_CHIP_ID_BCM5357
:
366 case BCMA_CHIP_ID_BCM4749
:
367 case BCMA_CHIP_ID_BCM53572
:
368 /* 5357[ab]0, 43236[ab]0, and 6362b0 */
370 /* BCM5357 needs to touch PLL1_PLLCTL[02],
371 so offset PLL0_PLLCTL[02] by 6 */
372 phypll_offset
= (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM5357
||
373 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4749
||
374 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM53572
) ? 6 : 0;
376 /* RMW only the P1 divider */
377 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
,
378 BCMA_CC_PMU_PLL_CTL0
+ phypll_offset
);
379 tmp
= bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
380 tmp
&= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK
));
381 tmp
|= (bcm5357_bcm43236_p1div
[spuravoid
] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT
);
382 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, tmp
);
384 /* RMW only the int feedback divider */
385 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
,
386 BCMA_CC_PMU_PLL_CTL2
+ phypll_offset
);
387 tmp
= bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
388 tmp
&= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK
);
389 tmp
|= (bcm5357_bcm43236_ndiv
[spuravoid
]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT
;
390 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, tmp
);
392 tmp
= BCMA_CC_PMU_CTL_PLL_UPD
;
395 case BCMA_CHIP_ID_BCM4331
:
396 case BCMA_CHIP_ID_BCM43431
:
397 if (spuravoid
== 2) {
398 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
400 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
402 } else if (spuravoid
== 1) {
403 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
405 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
408 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
410 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
413 tmp
= BCMA_CC_PMU_CTL_PLL_UPD
;
416 case BCMA_CHIP_ID_BCM43224
:
417 case BCMA_CHIP_ID_BCM43225
:
418 case BCMA_CHIP_ID_BCM43421
:
419 if (spuravoid
== 1) {
420 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
422 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
424 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
426 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
428 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
430 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
433 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
435 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
437 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
439 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
441 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
443 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
446 tmp
= BCMA_CC_PMU_CTL_PLL_UPD
;
449 case BCMA_CHIP_ID_BCM4716
:
450 case BCMA_CHIP_ID_BCM4748
:
451 case BCMA_CHIP_ID_BCM47162
:
452 if (spuravoid
== 1) {
453 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
455 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
457 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
459 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
461 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
463 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
466 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
468 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
470 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
472 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
474 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
476 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
480 tmp
= BCMA_CC_PMU_CTL_PLL_UPD
| BCMA_CC_PMU_CTL_NOILPONW
;
483 case BCMA_CHIP_ID_BCM43227
:
484 case BCMA_CHIP_ID_BCM43228
:
485 case BCMA_CHIP_ID_BCM43428
:
487 /* PLL Settings for spur avoidance on/off mode,
488 no on2 support for 43228A0 */
489 if (spuravoid
== 1) {
490 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
492 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
494 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
496 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
498 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
500 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
503 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
505 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
507 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
509 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
511 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
513 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
516 tmp
= BCMA_CC_PMU_CTL_PLL_UPD
;
519 bcma_err(bus
, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
524 tmp
|= bcma_cc_read32(cc
, BCMA_CC_PMU_CTL
);
525 bcma_cc_write32(cc
, BCMA_CC_PMU_CTL
, tmp
);
527 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate
);