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mm: vmscan: immediately reclaim end-of-LRU dirty pages when writeback completes
[linux-2.6.git] / drivers / gpio / gpio-pch.c
blob1e8a4a5388108b756e132203d11115401d7f58c8
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/gpio.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22
23 #define PCH_EDGE_FALLING 0
24 #define PCH_EDGE_RISING BIT(0)
25 #define PCH_LEVEL_L BIT(1)
26 #define PCH_LEVEL_H (BIT(0) | BIT(1))
27 #define PCH_EDGE_BOTH BIT(2)
28 #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
29
30 #define PCH_IRQ_BASE 24
31
32 struct pch_regs {
33 u32 ien;
34 u32 istatus;
35 u32 idisp;
36 u32 iclr;
37 u32 imask;
38 u32 imaskclr;
39 u32 po;
40 u32 pi;
41 u32 pm;
42 u32 im0;
43 u32 im1;
44 u32 reserved[3];
45 u32 gpio_use_sel;
46 u32 reset;
47 };
48
49 enum pch_type_t {
50 INTEL_EG20T_PCH,
51 OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */
52 OKISEMI_ML7223n_IOH /* OKISEMI ML7223 IOH PCIe Bus-n */
53 };
54
55 /* Specifies number of GPIO PINS */
56 static int gpio_pins[] = {
57 [INTEL_EG20T_PCH] = 12,
58 [OKISEMI_ML7223m_IOH] = 8,
59 [OKISEMI_ML7223n_IOH] = 8,
60 };
61
62 /**
63 * struct pch_gpio_reg_data - The register store data.
64 * @ien_reg: To store contents of IEN register.
65 * @imask_reg: To store contents of IMASK register.
66 * @po_reg: To store contents of PO register.
67 * @pm_reg: To store contents of PM register.
68 * @im0_reg: To store contents of IM0 register.
69 * @im1_reg: To store contents of IM1 register.
70 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
71 * (Only ML7223 Bus-n)
72 */
73 struct pch_gpio_reg_data {
74 u32 ien_reg;
75 u32 imask_reg;
76 u32 po_reg;
77 u32 pm_reg;
78 u32 im0_reg;
79 u32 im1_reg;
80 u32 gpio_use_sel_reg;
81 };
82
83 /**
84 * struct pch_gpio - GPIO private data structure.
85 * @base: PCI base address of Memory mapped I/O register.
86 * @reg: Memory mapped PCH GPIO register list.
87 * @dev: Pointer to device structure.
88 * @gpio: Data for GPIO infrastructure.
89 * @pch_gpio_reg: Memory mapped Register data is saved here
90 * when suspend.
91 * @lock: Used for register access protection
92 * @irq_base: Save base of IRQ number for interrupt
93 * @ioh: IOH ID
94 * @spinlock: Used for register access protection in
95 * interrupt context pch_irq_mask,
96 * pch_irq_unmask and pch_irq_type;
97 */
98 struct pch_gpio {
99 void __iomem *base;
100 struct pch_regs __iomem *reg;
101 struct device *dev;
102 struct gpio_chip gpio;
103 struct pch_gpio_reg_data pch_gpio_reg;
104 struct mutex lock;
105 int irq_base;
106 enum pch_type_t ioh;
107 spinlock_t spinlock;
108 };
109
110 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
111 {
112 u32 reg_val;
113 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
114
115 mutex_lock(&chip->lock);
116 reg_val = ioread32(&chip->reg->po);
117 if (val)
118 reg_val |= (1 << nr);
119 else
120 reg_val &= ~(1 << nr);
121
122 iowrite32(reg_val, &chip->reg->po);
123 mutex_unlock(&chip->lock);
124 }
125
126 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
127 {
128 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
129
130 return ioread32(&chip->reg->pi) & (1 << nr);
131 }
132
133 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
134 int val)
135 {
136 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
137 u32 pm;
138 u32 reg_val;
139
140 mutex_lock(&chip->lock);
141 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
142 pm |= (1 << nr);
143 iowrite32(pm, &chip->reg->pm);
144
145 reg_val = ioread32(&chip->reg->po);
146 if (val)
147 reg_val |= (1 << nr);
148 else
149 reg_val &= ~(1 << nr);
150 iowrite32(reg_val, &chip->reg->po);
151
152 mutex_unlock(&chip->lock);
153
154 return 0;
155 }
156
157 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
158 {
159 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
160 u32 pm;
161
162 mutex_lock(&chip->lock);
163 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
164 pm &= ~(1 << nr);
165 iowrite32(pm, &chip->reg->pm);
166 mutex_unlock(&chip->lock);
167
168 return 0;
169 }
170
171 /*
172 * Save register configuration and disable interrupts.
173 */
174 static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
175 {
176 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
177 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
178 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
179 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
180 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
181 if (chip->ioh == INTEL_EG20T_PCH)
182 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
183 if (chip->ioh == OKISEMI_ML7223n_IOH)
184 chip->pch_gpio_reg.gpio_use_sel_reg =\
185 ioread32(&chip->reg->gpio_use_sel);
186 }
187
188 /*
189 * This function restores the register configuration of the GPIO device.
190 */
191 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
192 {
193 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
194 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
195 /* to store contents of PO register */
196 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
197 /* to store contents of PM register */
198 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
199 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
200 if (chip->ioh == INTEL_EG20T_PCH)
201 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
202 if (chip->ioh == OKISEMI_ML7223n_IOH)
203 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
204 &chip->reg->gpio_use_sel);
205 }
206
207 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
208 {
209 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
210 return chip->irq_base + offset;
211 }
212
213 static void pch_gpio_setup(struct pch_gpio *chip)
214 {
215 struct gpio_chip *gpio = &chip->gpio;
216
217 gpio->label = dev_name(chip->dev);
218 gpio->owner = THIS_MODULE;
219 gpio->direction_input = pch_gpio_direction_input;
220 gpio->get = pch_gpio_get;
221 gpio->direction_output = pch_gpio_direction_output;
222 gpio->set = pch_gpio_set;
223 gpio->dbg_show = NULL;
224 gpio->base = -1;
225 gpio->ngpio = gpio_pins[chip->ioh];
226 gpio->can_sleep = 0;
227 gpio->to_irq = pch_gpio_to_irq;
228 }
229
230 static int pch_irq_type(struct irq_data *d, unsigned int type)
231 {
232 u32 im;
233 u32 *im_reg;
234 u32 ien;
235 u32 im_pos;
236 int ch;
237 unsigned long flags;
238 u32 val;
239 int irq = d->irq;
240 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
241 struct pch_gpio *chip = gc->private;
242
243 ch = irq - chip->irq_base;
244 if (irq <= chip->irq_base + 7) {
245 im_reg = &chip->reg->im0;
246 im_pos = ch;
247 } else {
248 im_reg = &chip->reg->im1;
249 im_pos = ch - 8;
250 }
251 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
252 __func__, irq, type, ch, im_pos);
253
254 spin_lock_irqsave(&chip->spinlock, flags);
255
256 switch (type) {
257 case IRQ_TYPE_EDGE_RISING:
258 val = PCH_EDGE_RISING;
259 break;
260 case IRQ_TYPE_EDGE_FALLING:
261 val = PCH_EDGE_FALLING;
262 break;
263 case IRQ_TYPE_EDGE_BOTH:
264 val = PCH_EDGE_BOTH;
265 break;
266 case IRQ_TYPE_LEVEL_HIGH:
267 val = PCH_LEVEL_H;
268 break;
269 case IRQ_TYPE_LEVEL_LOW:
270 val = PCH_LEVEL_L;
271 break;
272 case IRQ_TYPE_PROBE:
273 goto end;
274 default:
275 dev_warn(chip->dev, "%s: unknown type(%dd)",
276 __func__, type);
277 goto end;
278 }
279
280 /* Set interrupt mode */
281 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
282 iowrite32(im | (val << (im_pos * 4)), im_reg);
283
284 /* iclr */
285 iowrite32(BIT(ch), &chip->reg->iclr);
286
287 /* IMASKCLR */
288 iowrite32(BIT(ch), &chip->reg->imaskclr);
289
290 /* Enable interrupt */
291 ien = ioread32(&chip->reg->ien);
292 iowrite32(ien | BIT(ch), &chip->reg->ien);
293 end:
294 spin_unlock_irqrestore(&chip->spinlock, flags);
295
296 return 0;
297 }
298
299 static void pch_irq_unmask(struct irq_data *d)
300 {
301 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
302 struct pch_gpio *chip = gc->private;
303
304 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
305 }
306
307 static void pch_irq_mask(struct irq_data *d)
308 {
309 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
310 struct pch_gpio *chip = gc->private;
311
312 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
313 }
314
315 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
316 {
317 struct pch_gpio *chip = dev_id;
318 u32 reg_val = ioread32(&chip->reg->istatus);
319 int i;
320 int ret = IRQ_NONE;
321
322 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
323 if (reg_val & BIT(i)) {
324 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
325 __func__, i, irq, reg_val);
326 iowrite32(BIT(i), &chip->reg->iclr);
327 generic_handle_irq(chip->irq_base + i);
328 ret = IRQ_HANDLED;
329 }
330 }
331 return ret;
332 }
333
334 static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
335 unsigned int irq_start, unsigned int num)
336 {
337 struct irq_chip_generic *gc;
338 struct irq_chip_type *ct;
339
340 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
341 handle_simple_irq);
342 gc->private = chip;
343 ct = gc->chip_types;
344
345 ct->chip.irq_mask = pch_irq_mask;
346 ct->chip.irq_unmask = pch_irq_unmask;
347 ct->chip.irq_set_type = pch_irq_type;
348
349 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
350 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
351 }
352
353 static int __devinit pch_gpio_probe(struct pci_dev *pdev,
354 const struct pci_device_id *id)
355 {
356 s32 ret;
357 struct pch_gpio *chip;
358 int irq_base;
359
360 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
361 if (chip == NULL)
362 return -ENOMEM;
363
364 chip->dev = &pdev->dev;
365 ret = pci_enable_device(pdev);
366 if (ret) {
367 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
368 goto err_pci_enable;
369 }
370
371 ret = pci_request_regions(pdev, KBUILD_MODNAME);
372 if (ret) {
373 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
374 goto err_request_regions;
375 }
376
377 chip->base = pci_iomap(pdev, 1, 0);
378 if (chip->base == 0) {
379 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
380 ret = -ENOMEM;
381 goto err_iomap;
382 }
383
384 if (pdev->device == 0x8803)
385 chip->ioh = INTEL_EG20T_PCH;
386 else if (pdev->device == 0x8014)
387 chip->ioh = OKISEMI_ML7223m_IOH;
388 else if (pdev->device == 0x8043)
389 chip->ioh = OKISEMI_ML7223n_IOH;
390
391 chip->reg = chip->base;
392 pci_set_drvdata(pdev, chip);
393 mutex_init(&chip->lock);
394 pch_gpio_setup(chip);
395 ret = gpiochip_add(&chip->gpio);
396 if (ret) {
397 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
398 goto err_gpiochip_add;
399 }
400
401 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
402 if (irq_base < 0) {
403 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
404 chip->irq_base = -1;
405 goto end;
406 }
407 chip->irq_base = irq_base;
408
409 ret = request_irq(pdev->irq, pch_gpio_handler,
410 IRQF_SHARED, KBUILD_MODNAME, chip);
411 if (ret != 0) {
412 dev_err(&pdev->dev,
413 "%s request_irq failed\n", __func__);
414 goto err_request_irq;
415 }
416
417 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
418
419 /* Initialize interrupt ien register */
420 iowrite32(0, &chip->reg->ien);
421 end:
422 return 0;
423
424 err_request_irq:
425 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
426
427 ret = gpiochip_remove(&chip->gpio);
428 if (ret)
429 dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
430
431 err_gpiochip_add:
432 pci_iounmap(pdev, chip->base);
433
434 err_iomap:
435 pci_release_regions(pdev);
436
437 err_request_regions:
438 pci_disable_device(pdev);
439
440 err_pci_enable:
441 kfree(chip);
442 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
443 return ret;
444 }
445
446 static void __devexit pch_gpio_remove(struct pci_dev *pdev)
447 {
448 int err;
449 struct pch_gpio *chip = pci_get_drvdata(pdev);
450
451 if (chip->irq_base != -1) {
452 free_irq(pdev->irq, chip);
453
454 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
455 }
456
457 err = gpiochip_remove(&chip->gpio);
458 if (err)
459 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
460
461 pci_iounmap(pdev, chip->base);
462 pci_release_regions(pdev);
463 pci_disable_device(pdev);
464 kfree(chip);
465 }
466
467 #ifdef CONFIG_PM
468 static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
469 {
470 s32 ret;
471 struct pch_gpio *chip = pci_get_drvdata(pdev);
472 unsigned long flags;
473
474 spin_lock_irqsave(&chip->spinlock, flags);
475 pch_gpio_save_reg_conf(chip);
476 spin_unlock_irqrestore(&chip->spinlock, flags);
477
478 ret = pci_save_state(pdev);
479 if (ret) {
480 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
481 return ret;
482 }
483 pci_disable_device(pdev);
484 pci_set_power_state(pdev, PCI_D0);
485 ret = pci_enable_wake(pdev, PCI_D0, 1);
486 if (ret)
487 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
488
489 return 0;
490 }
491
492 static int pch_gpio_resume(struct pci_dev *pdev)
493 {
494 s32 ret;
495 struct pch_gpio *chip = pci_get_drvdata(pdev);
496 unsigned long flags;
497
498 ret = pci_enable_wake(pdev, PCI_D0, 0);
499
500 pci_set_power_state(pdev, PCI_D0);
501 ret = pci_enable_device(pdev);
502 if (ret) {
503 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
504 return ret;
505 }
506 pci_restore_state(pdev);
507
508 spin_lock_irqsave(&chip->spinlock, flags);
509 iowrite32(0x01, &chip->reg->reset);
510 iowrite32(0x00, &chip->reg->reset);
511 pch_gpio_restore_reg_conf(chip);
512 spin_unlock_irqrestore(&chip->spinlock, flags);
513
514 return 0;
515 }
516 #else
517 #define pch_gpio_suspend NULL
518 #define pch_gpio_resume NULL
519 #endif
520
521 #define PCI_VENDOR_ID_ROHM 0x10DB
522 static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
523 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
524 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
525 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
526 { 0, }
527 };
528 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
529
530 static struct pci_driver pch_gpio_driver = {
531 .name = "pch_gpio",
532 .id_table = pch_gpio_pcidev_id,
533 .probe = pch_gpio_probe,
534 .remove = __devexit_p(pch_gpio_remove),
535 .suspend = pch_gpio_suspend,
536 .resume = pch_gpio_resume
537 };
538
539 static int __init pch_gpio_pci_init(void)
540 {
541 return pci_register_driver(&pch_gpio_driver);
542 }
543 module_init(pch_gpio_pci_init);
544
545 static void __exit pch_gpio_pci_exit(void)
546 {
547 pci_unregister_driver(&pch_gpio_driver);
548 }
549 module_exit(pch_gpio_pci_exit);
550
551 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
552 MODULE_LICENSE("GPL");
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