arch/arm/mach-davinci/gpio.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/gpio.h>
  20
  21 #include <asm/mach/irq.h>
  22
  23 struct davinci_gpio_regs {
  24         u32     dir;
  25         u32     out_data;
  26         u32     set_data;
  27         u32     clr_data;
  28         u32     in_data;
  29         u32     set_rising;
  30         u32     clr_rising;
  31         u32     set_falling;
  32         u32     clr_falling;
  33         u32     intstat;
  34 };
  35
  36 #define chip2controller(chip)   \
  37         container_of(chip, struct davinci_gpio_controller, chip)
  38
  39 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
  40 static void __iomem *gpio_base;
  41
  42 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
  43 {
  44         void __iomem *ptr;
  45
  46         if (gpio < 32 * 1)
  47                 ptr = gpio_base + 0x10;
  48         else if (gpio < 32 * 2)
  49                 ptr = gpio_base + 0x38;
  50         else if (gpio < 32 * 3)
  51                 ptr = gpio_base + 0x60;
  52         else if (gpio < 32 * 4)
  53                 ptr = gpio_base + 0x88;
  54         else if (gpio < 32 * 5)
  55                 ptr = gpio_base + 0xb0;
  56         else
  57                 ptr = NULL;
  58         return ptr;
  59 }
  60
  61 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
  62 {
  63         struct davinci_gpio_regs __iomem *g;
  64
  65         g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
  66
  67         return g;
  68 }
  69
  70 static int __init davinci_gpio_irq_setup(void);
  71
  72 /*--------------------------------------------------------------------------*/
  73
  74 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  75 static inline int __davinci_direction(struct gpio_chip *chip,
  76                         unsigned offset, bool out, int value)
  77 {
  78         struct davinci_gpio_controller *d = chip2controller(chip);
  79         struct davinci_gpio_regs __iomem *g = d->regs;
  80         unsigned long flags;
  81         u32 temp;
  82         u32 mask = 1 << offset;
  83
  84         spin_lock_irqsave(&d->lock, flags);
  85         temp = __raw_readl(&g->dir);
  86         if (out) {
  87                 temp &= ~mask;
  88                 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
  89         } else {
  90                 temp |= mask;
  91         }
  92         __raw_writel(temp, &g->dir);
  93         spin_unlock_irqrestore(&d->lock, flags);
  94
  95         return 0;
  96 }
  97
  98 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  99 {
 100         return __davinci_direction(chip, offset, false, 0);
 101 }
 102
 103 static int
 104 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 105 {
 106         return __davinci_direction(chip, offset, true, value);
 107 }
 108
 109 /*
 110  * Read the pin's value (works even if it's set up as output);
 111  * returns zero/nonzero.
 112  *
 113  * Note that changes are synched to the GPIO clock, so reading values back
 114  * right after you've set them may give old values.
 115  */
 116 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 117 {
 118         struct davinci_gpio_controller *d = chip2controller(chip);
 119         struct davinci_gpio_regs __iomem *g = d->regs;
 120
 121         return (1 << offset) & __raw_readl(&g->in_data);
 122 }
 123
 124 /*
 125  * Assuming the pin is muxed as a gpio output, set its output value.
 126  */
 127 static void
 128 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 129 {
 130         struct davinci_gpio_controller *d = chip2controller(chip);
 131         struct davinci_gpio_regs __iomem *g = d->regs;
 132
 133         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 134 }
 135
 136 static int __init davinci_gpio_setup(void)
 137 {
 138         int i, base;
 139         unsigned ngpio;
 140         struct davinci_soc_info *soc_info = &davinci_soc_info;
 141         struct davinci_gpio_regs *regs;
 142
 143         if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
 144                 return 0;
 145
 146         /*
 147          * The gpio banks conceptually expose a segmented bitmap,
 148          * and "ngpio" is one more than the largest zero-based
 149          * bit index that's valid.
 150          */
 151         ngpio = soc_info->gpio_num;
 152         if (ngpio == 0) {
 153                 pr_err("GPIO setup:  how many GPIOs?\n");
 154                 return -EINVAL;
 155         }
 156
 157         if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 158                 ngpio = DAVINCI_N_GPIO;
 159
 160         gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
 161         if (WARN_ON(!gpio_base))
 162                 return -ENOMEM;
 163
 164         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 165                 chips[i].chip.label = "DaVinci";
 166
 167                 chips[i].chip.direction_input = davinci_direction_in;
 168                 chips[i].chip.get = davinci_gpio_get;
 169                 chips[i].chip.direction_output = davinci_direction_out;
 170                 chips[i].chip.set = davinci_gpio_set;
 171
 172                 chips[i].chip.base = base;
 173                 chips[i].chip.ngpio = ngpio - base;
 174                 if (chips[i].chip.ngpio > 32)
 175                         chips[i].chip.ngpio = 32;
 176
 177                 spin_lock_init(&chips[i].lock);
 178
 179                 regs = gpio2regs(base);
 180                 chips[i].regs = regs;
 181                 chips[i].set_data = &regs->set_data;
 182                 chips[i].clr_data = &regs->clr_data;
 183                 chips[i].in_data = &regs->in_data;
 184
 185                 gpiochip_add(&chips[i].chip);
 186         }
 187
 188         soc_info->gpio_ctlrs = chips;
 189         soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
 190
 191         davinci_gpio_irq_setup();
 192         return 0;
 193 }
 194 pure_initcall(davinci_gpio_setup);
 195
 196 /*--------------------------------------------------------------------------*/
 197 /*
 198  * We expect irqs will normally be set up as input pins, but they can also be
 199  * used as output pins ... which is convenient for testing.
 200  *
 201  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 202  * to their GPIOBNK0 irq, with a bit less overhead.
 203  *
 204  * All those INTC hookups (direct, plus several IRQ banks) can also
 205  * serve as EDMA event triggers.
 206  */
 207
 208 static void gpio_irq_disable(struct irq_data *d)
 209 {
 210         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
 211         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 212
 213         __raw_writel(mask, &g->clr_falling);
 214         __raw_writel(mask, &g->clr_rising);
 215 }
 216
 217 static void gpio_irq_enable(struct irq_data *d)
 218 {
 219         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
 220         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 221         unsigned status = irqd_get_trigger_type(d);
 222
 223         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 224         if (!status)
 225                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 226
 227         if (status & IRQ_TYPE_EDGE_FALLING)
 228                 __raw_writel(mask, &g->set_falling);
 229         if (status & IRQ_TYPE_EDGE_RISING)
 230                 __raw_writel(mask, &g->set_rising);
 231 }
 232
 233 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 234 {
 235         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
 236         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 237
 238         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 239                 return -EINVAL;
 240
 241         return 0;
 242 }
 243
 244 static struct irq_chip gpio_irqchip = {
 245         .name           = "GPIO",
 246         .irq_enable     = gpio_irq_enable,
 247         .irq_disable    = gpio_irq_disable,
 248         .irq_set_type   = gpio_irq_type,
 249         .flags          = IRQCHIP_SET_TYPE_MASKED,
 250 };
 251
 252 static void
 253 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 254 {
 255         struct davinci_gpio_regs __iomem *g;
 256         u32 mask = 0xffff;
 257         struct davinci_gpio_controller *d;
 258
 259         d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
 260         g = (struct davinci_gpio_regs __iomem *)d->regs;
 261
 262         /* we only care about one bank */
 263         if (irq & 1)
 264                 mask <<= 16;
 265
 266         /* temporarily mask (level sensitive) parent IRQ */
 267         desc->irq_data.chip->irq_mask(&desc->irq_data);
 268         desc->irq_data.chip->irq_ack(&desc->irq_data);
 269         while (1) {
 270                 u32             status;
 271                 int             n;
 272                 int             res;
 273
 274                 /* ack any irqs */
 275                 status = __raw_readl(&g->intstat) & mask;
 276                 if (!status)
 277                         break;
 278                 __raw_writel(status, &g->intstat);
 279
 280                 /* now demux them to the right lowlevel handler */
 281                 n = d->irq_base;
 282                 if (irq & 1) {
 283                         n += 16;
 284                         status >>= 16;
 285                 }
 286
 287                 while (status) {
 288                         res = ffs(status);
 289                         n += res;
 290                         generic_handle_irq(n - 1);
 291                         status >>= res;
 292                 }
 293         }
 294         desc->irq_data.chip->irq_unmask(&desc->irq_data);
 295         /* now it may re-trigger */
 296 }
 297
 298 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 299 {
 300         struct davinci_gpio_controller *d = chip2controller(chip);
 301
 302         if (d->irq_base >= 0)
 303                 return d->irq_base + offset;
 304         else
 305                 return -ENODEV;
 306 }
 307
 308 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 309 {
 310         struct davinci_soc_info *soc_info = &davinci_soc_info;
 311
 312         /* NOTE:  we assume for now that only irqs in the first gpio_chip
 313          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 314          */
 315         if (offset < soc_info->gpio_unbanked)
 316                 return soc_info->gpio_irq + offset;
 317         else
 318                 return -ENODEV;
 319 }
 320
 321 static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
 322 {
 323         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
 324         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 325
 326         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 327                 return -EINVAL;
 328
 329         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 330                      ? &g->set_falling : &g->clr_falling);
 331         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 332                      ? &g->set_rising : &g->clr_rising);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * NOTE:  for suspend/resume, probably best to make a platform_device with
 339  * suspend_late/resume_resume calls hooking into results of the set_wake()
 340  * calls ... so if no gpios are wakeup events the clock can be disabled,
 341  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 342  * (dm6446) can be set appropriately for GPIOV33 pins.
 343  */
 344
 345 static int __init davinci_gpio_irq_setup(void)
 346 {
 347         unsigned        gpio, irq, bank;
 348         struct clk      *clk;
 349         u32             binten = 0;
 350         unsigned        ngpio, bank_irq;
 351         struct davinci_soc_info *soc_info = &davinci_soc_info;
 352         struct davinci_gpio_regs        __iomem *g;
 353
 354         ngpio = soc_info->gpio_num;
 355
 356         bank_irq = soc_info->gpio_irq;
 357         if (bank_irq == 0) {
 358                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
 359                 return -EINVAL;
 360         }
 361
 362         clk = clk_get(NULL, "gpio");
 363         if (IS_ERR(clk)) {
 364                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 365                        PTR_ERR(clk));
 366                 return PTR_ERR(clk);
 367         }
 368         clk_enable(clk);
 369
 370         /* Arrange gpio_to_irq() support, handling either direct IRQs or
 371          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 372          * IRQs, while the others use banked IRQs, would need some setup
 373          * tweaks to recognize hardware which can do that.
 374          */
 375         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
 376                 chips[bank].chip.to_irq = gpio_to_irq_banked;
 377                 chips[bank].irq_base = soc_info->gpio_unbanked
 378                         ? -EINVAL
 379                         : (soc_info->intc_irq_num + gpio);
 380         }
 381
 382         /*
 383          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 384          * controller only handling trigger modes.  We currently assume no
 385          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 386          */
 387         if (soc_info->gpio_unbanked) {
 388                 static struct irq_chip gpio_irqchip_unbanked;
 389
 390                 /* pass "bank 0" GPIO IRQs to AINTC */
 391                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
 392                 binten = BIT(0);
 393
 394                 /* AINTC handles mask/unmask; GPIO handles triggering */
 395                 irq = bank_irq;
 396                 gpio_irqchip_unbanked = *irq_get_chip(irq);
 397                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
 398                 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
 399
 400                 /* default trigger: both edges */
 401                 g = gpio2regs(0);
 402                 __raw_writel(~0, &g->set_falling);
 403                 __raw_writel(~0, &g->set_rising);
 404
 405                 /* set the direct IRQs up to use that irqchip */
 406                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 407                         irq_set_chip(irq, &gpio_irqchip_unbanked);
 408                         irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
 409                         irq_set_chip_data(irq, (__force void *)g);
 410                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
 411                 }
 412
 413                 goto done;
 414         }
 415
 416         /*
 417          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 418          * then chain through our own handler.
 419          */
 420         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
 421                         gpio < ngpio;
 422                         bank++, bank_irq++) {
 423                 unsigned                i;
 424
 425                 /* disabled by default, enabled only as needed */
 426                 g = gpio2regs(gpio);
 427                 __raw_writel(~0, &g->clr_falling);
 428                 __raw_writel(~0, &g->clr_rising);
 429
 430                 /* set up all irqs in this bank */
 431                 irq_set_chained_handler(bank_irq, gpio_irq_handler);
 432
 433                 /*
 434                  * Each chip handles 32 gpios, and each irq bank consists of 16
 435                  * gpio irqs. Pass the irq bank's corresponding controller to
 436                  * the chained irq handler.
 437                  */
 438                 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
 439
 440                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 441                         irq_set_chip(irq, &gpio_irqchip);
 442                         irq_set_chip_data(irq, (__force void *)g);
 443                         irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
 444                         irq_set_handler(irq, handle_simple_irq);
 445                         set_irq_flags(irq, IRQF_VALID);
 446                 }
 447
 448                 binten |= BIT(bank);
 449         }
 450
 451 done:
 452         /* BINTEN -- per-bank interrupt enable. genirq would also let these
 453          * bits be set/cleared dynamically.
 454          */
 455         __raw_writel(binten, gpio_base + 0x08);
 456
 457         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 458
 459         return 0;
 460 }