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bnx2x: propagate DCBX negotiation
[linux-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blob967c41b8b1728a97334665d6a498b1190e5aa3bf
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if.h>
43 #include <linux/if_vlan.h>
44 #include <net/ip.h>
45 #include <net/ipv6.h>
46 #include <net/tcp.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
54 #include <linux/io.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
79
80 static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2);
94
95 static int multi_mode = 1;
96 module_param(multi_mode, int, 0);
97 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
100 int num_queues;
101 module_param(num_queues, int, 0);
102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
104
105 static int disable_tpa;
106 module_param(disable_tpa, int, 0);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
111 static int int_mode;
112 module_param(int_mode, int, 0);
113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)");
115
116 static int dropless_fc;
117 module_param(dropless_fc, int, 0);
118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
120 static int poll;
121 module_param(poll, int, 0);
122 MODULE_PARM_DESC(poll, " Use polling (for debug)");
123
124 static int mrrs = -1;
125 module_param(mrrs, int, 0);
126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127
128 static int debug;
129 module_param(debug, int, 0);
130 MODULE_PARM_DESC(debug, " Default debug msglevel");
131
132
133
134 struct workqueue_struct *bnx2x_wq;
135
136 enum bnx2x_board_type {
137 BCM57710 = 0,
138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
142 BCM57800,
143 BCM57800_MF,
144 BCM57810,
145 BCM57810_MF,
146 BCM57840,
147 BCM57840_MF
148 };
149
150 /* indexed by board_type, above */
151 static struct {
152 char *name;
153 } board_info[] __devinitdata = {
154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
166 };
167
168 #ifndef PCI_DEVICE_ID_NX2_57710
169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170 #endif
171 #ifndef PCI_DEVICE_ID_NX2_57711
172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711E
175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57712
178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712_MF
181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57800
184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800_MF
187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57810
190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810_MF
193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57840
196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_MF
199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200 #endif
201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 { 0 }
214 };
215
216 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217
218 /****************************************************************************
219 * General service functions
220 ****************************************************************************/
221
222 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping)
224 {
225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping));
227 }
228
229 static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid)
231 {
232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234
235 __storm_memset_dma_mapping(bp, addr, mapping);
236 }
237
238 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id)
240 {
241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id);
249 }
250
251 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable)
253 {
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable);
262 }
263
264 static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data,
266 u16 pfid)
267 {
268 size_t size = sizeof(struct event_ring_data);
269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273 }
274
275 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid)
277 {
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod);
280 }
281
282 /* used only at init
283 * locking is done by mcp
284 */
285 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
286 {
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET);
291 }
292
293 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 {
295 u32 val;
296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET);
301
302 return val;
303 }
304
305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309 #define DMAE_DP_DST_NONE "dst_addr [none]"
310
311 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl)
313 {
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315
316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val);
326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val);
334 break;
335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val);
344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val);
352 break;
353 default:
354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n"
356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val);
361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n"
363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val);
368 break;
369 }
370
371 }
372
373 /* copy command into DMAE command memory and set DMAE command go */
374 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
375 {
376 u32 cmd_offset;
377 int i;
378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382
383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387 }
388
389 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 {
391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE);
393 }
394
395 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 {
397 return opcode & ~DMAE_CMD_SRC_RESET;
398 }
399
400 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type)
402 {
403 u32 opcode = 0;
404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT));
407
408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
414
415 #ifdef __BIG_ENDIAN
416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 #else
418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
419 #endif
420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode;
423 }
424
425 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type)
428 {
429 memset(dmae, 0, sizeof(struct dmae_command));
430
431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI);
434
435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL;
439 }
440
441 /* issue a dmae command over the init-channel and wailt for completion */
442 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae)
444 {
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
447 int rc = 0;
448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
452
453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */
458 spin_lock_bh(&bp->dmae_lock);
459
460 /* reset completion */
461 *wb_comp = 0;
462
463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465
466 /* wait for completion */
467 udelay(5);
468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470
471 if (!cnt) {
472 BNX2X_ERR("DMAE timeout!\n");
473 rc = DMAE_TIMEOUT;
474 goto unlock;
475 }
476 cnt--;
477 udelay(50);
478 }
479 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
480 BNX2X_ERR("DMAE PCI error!\n");
481 rc = DMAE_PCI_ERROR;
482 }
483
484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
487
488 unlock:
489 spin_unlock_bh(&bp->dmae_lock);
490 return rc;
491 }
492
493 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 u32 len32)
495 {
496 struct dmae_command dmae;
497
498 if (!bp->dmae_ready) {
499 u32 *data = bnx2x_sp(bp, wb_data[0]);
500
501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
502 " using indirect\n", dst_addr, len32);
503 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
504 return;
505 }
506
507 /* set opcode and fixed command fields */
508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509
510 /* fill in addresses and len */
511 dmae.src_addr_lo = U64_LO(dma_addr);
512 dmae.src_addr_hi = U64_HI(dma_addr);
513 dmae.dst_addr_lo = dst_addr >> 2;
514 dmae.dst_addr_hi = 0;
515 dmae.len = len32;
516
517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518
519 /* issue the command and wait for completion */
520 bnx2x_issue_dmae_with_comp(bp, &dmae);
521 }
522
523 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 {
525 struct dmae_command dmae;
526
527 if (!bp->dmae_ready) {
528 u32 *data = bnx2x_sp(bp, wb_data[0]);
529 int i;
530
531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
532 " using indirect\n", src_addr, len32);
533 for (i = 0; i < len32; i++)
534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
535 return;
536 }
537
538 /* set opcode and fixed command fields */
539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540
541 /* fill in addresses and len */
542 dmae.src_addr_lo = src_addr >> 2;
543 dmae.src_addr_hi = 0;
544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
546 dmae.len = len32;
547
548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549
550 /* issue the command and wait for completion */
551 bnx2x_issue_dmae_with_comp(bp, &dmae);
552 }
553
554 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
555 u32 addr, u32 len)
556 {
557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
558 int offset = 0;
559
560 while (len > dmae_wr_max) {
561 bnx2x_write_dmae(bp, phys_addr + offset,
562 addr + offset, dmae_wr_max);
563 offset += dmae_wr_max * 4;
564 len -= dmae_wr_max;
565 }
566
567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
568 }
569
570 /* used only for slowpath so not inlined */
571 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
572 {
573 u32 wb_write[2];
574
575 wb_write[0] = val_hi;
576 wb_write[1] = val_lo;
577 REG_WR_DMAE(bp, reg, wb_write, 2);
578 }
579
580 #ifdef USE_WB_RD
581 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
582 {
583 u32 wb_data[2];
584
585 REG_RD_DMAE(bp, reg, wb_data, 2);
586
587 return HILO_U64(wb_data[0], wb_data[1]);
588 }
589 #endif
590
591 static int bnx2x_mc_assert(struct bnx2x *bp)
592 {
593 char last_idx;
594 int i, rc = 0;
595 u32 row0, row1, row2, row3;
596
597 /* XSTORM */
598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
599 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 if (last_idx)
601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602
603 /* print the asserts */
604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605
606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i));
608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
613 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614
615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617 " 0x%08x 0x%08x 0x%08x\n",
618 i, row3, row2, row1, row0);
619 rc++;
620 } else {
621 break;
622 }
623 }
624
625 /* TSTORM */
626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
627 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 if (last_idx)
629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630
631 /* print the asserts */
632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633
634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i));
636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642
643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645 " 0x%08x 0x%08x 0x%08x\n",
646 i, row3, row2, row1, row0);
647 rc++;
648 } else {
649 break;
650 }
651 }
652
653 /* CSTORM */
654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
655 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 if (last_idx)
657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658
659 /* print the asserts */
660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661
662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i));
664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
669 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670
671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673 " 0x%08x 0x%08x 0x%08x\n",
674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* USTORM */
682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
683 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701 " 0x%08x 0x%08x 0x%08x\n",
702 i, row3, row2, row1, row0);
703 rc++;
704 } else {
705 break;
706 }
707 }
708
709 return rc;
710 }
711
712 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
713 {
714 u32 addr, val;
715 u32 mark, offset;
716 __be32 data[9];
717 int word;
718 u32 trace_shmem_base;
719 if (BP_NOMCP(bp)) {
720 BNX2X_ERR("NO MCP - can not dump\n");
721 return;
722 }
723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
724 (bp->common.bc_ver & 0xff0000) >> 16,
725 (bp->common.bc_ver & 0xff00) >> 8,
726 (bp->common.bc_ver & 0xff));
727
728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
730 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731
732 if (BP_PATH(bp) == 0)
733 trace_shmem_base = bp->common.shmem_base;
734 else
735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
736 addr = trace_shmem_base - 0x0800 + 4;
737 mark = REG_RD(bp, addr);
738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
739 + ((mark + 0x3) & ~0x3) - 0x08000000;
740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
741
742 printk("%s", lvl);
743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
744 for (word = 0; word < 8; word++)
745 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 data[8] = 0x0;
747 pr_cont("%s", (char *)data);
748 }
749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
750 for (word = 0; word < 8; word++)
751 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 data[8] = 0x0;
753 pr_cont("%s", (char *)data);
754 }
755 printk("%s" "end of fw dump\n", lvl);
756 }
757
758 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 {
760 bnx2x_fw_dump_lvl(bp, KERN_ERR);
761 }
762
763 void bnx2x_panic_dump(struct bnx2x *bp)
764 {
765 int i;
766 u16 j;
767 struct hc_sp_status_block_data sp_sb_data;
768 int func = BP_FUNC(bp);
769 #ifdef BNX2X_STOP_ON_ERROR
770 u16 start = 0, end = 0;
771 u8 cos;
772 #endif
773
774 bp->stats_state = STATS_STATE_DISABLED;
775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776
777 BNX2X_ERR("begin crash dump -----------------\n");
778
779 /* Indices */
780 /* Common */
781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783 bp->def_idx, bp->def_att_idx, bp->attn_state,
784 bp->spq_prod_idx, bp->stats_counter);
785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786 bp->def_status_blk->atten_status_block.attn_bits,
787 bp->def_status_blk->atten_status_block.attn_bits_ack,
788 bp->def_status_blk->atten_status_block.status_block_id,
789 bp->def_status_blk->atten_status_block.attn_bits_index);
790 BNX2X_ERR(" def (");
791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 pr_cont("0x%x%s",
793 bp->def_status_blk->sp_sb.index_values[i],
794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795
796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
799 i*sizeof(u32));
800
801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state);
809
810
811 for_each_eth_queue(bp, i) {
812 struct bnx2x_fastpath *fp = &bp->fp[i];
813 int loop;
814 struct hc_status_block_data_e2 sb_data_e2;
815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
820 struct hc_index_data *hc_index_p =
821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
824 u8 data_size, cos;
825 u32 *sb_data_p;
826 struct bnx2x_fp_txdata txdata;
827
828 /* Rx */
829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
830 " rx_comp_prod(0x%x)"
831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
832 i, fp->rx_bd_prod, fp->rx_bd_cons,
833 fp->rx_comp_prod,
834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
836 " fp_hc_idx(0x%x)\n",
837 fp->rx_sge_prod, fp->last_max_sge,
838 le16_to_cpu(fp->fp_hc_idx));
839
840 /* Tx */
841 for_each_cos_in_tx_queue(fp, cos)
842 {
843 txdata = fp->txdata[cos];
844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846 " *tx_cons_sb(0x%x)\n",
847 i, txdata.tx_pkt_prod,
848 txdata.tx_pkt_cons, txdata.tx_bd_prod,
849 txdata.tx_bd_cons,
850 le16_to_cpu(*txdata.tx_cons_sb));
851 }
852
853 loop = CHIP_IS_E1x(bp) ?
854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
855
856 /* host sb data */
857
858 #ifdef BCM_CNIC
859 if (IS_FCOE_FP(fp))
860 continue;
861 #endif
862 BNX2X_ERR(" run indexes (");
863 for (j = 0; j < HC_SB_MAX_SM; j++)
864 pr_cont("0x%x%s",
865 fp->sb_running_index[j],
866 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
867
868 BNX2X_ERR(" indexes (");
869 for (j = 0; j < loop; j++)
870 pr_cont("0x%x%s",
871 fp->sb_index_values[j],
872 (j == loop - 1) ? ")" : " ");
873 /* fw sb data */
874 data_size = CHIP_IS_E1x(bp) ?
875 sizeof(struct hc_status_block_data_e1x) :
876 sizeof(struct hc_status_block_data_e2);
877 data_size /= sizeof(u32);
878 sb_data_p = CHIP_IS_E1x(bp) ?
879 (u32 *)&sb_data_e1x :
880 (u32 *)&sb_data_e2;
881 /* copy sb data in here */
882 for (j = 0; j < data_size; j++)
883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
885 j * sizeof(u32));
886
887 if (!CHIP_IS_E1x(bp)) {
888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
890 "state(0x%x)\n",
891 sb_data_e2.common.p_func.pf_id,
892 sb_data_e2.common.p_func.vf_id,
893 sb_data_e2.common.p_func.vf_valid,
894 sb_data_e2.common.p_func.vnic_id,
895 sb_data_e2.common.same_igu_sb_1b,
896 sb_data_e2.common.state);
897 } else {
898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
900 "state(0x%x)\n",
901 sb_data_e1x.common.p_func.pf_id,
902 sb_data_e1x.common.p_func.vf_id,
903 sb_data_e1x.common.p_func.vf_valid,
904 sb_data_e1x.common.p_func.vnic_id,
905 sb_data_e1x.common.same_igu_sb_1b,
906 sb_data_e1x.common.state);
907 }
908
909 /* SB_SMs data */
910 for (j = 0; j < HC_SB_MAX_SM; j++) {
911 pr_cont("SM[%d] __flags (0x%x) "
912 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
913 "time_to_expire (0x%x) "
914 "timer_value(0x%x)\n", j,
915 hc_sm_p[j].__flags,
916 hc_sm_p[j].igu_sb_id,
917 hc_sm_p[j].igu_seg_id,
918 hc_sm_p[j].time_to_expire,
919 hc_sm_p[j].timer_value);
920 }
921
922 /* Indecies data */
923 for (j = 0; j < loop; j++) {
924 pr_cont("INDEX[%d] flags (0x%x) "
925 "timeout (0x%x)\n", j,
926 hc_index_p[j].flags,
927 hc_index_p[j].timeout);
928 }
929 }
930
931 #ifdef BNX2X_STOP_ON_ERROR
932 /* Rings */
933 /* Rx */
934 for_each_rx_queue(bp, i) {
935 struct bnx2x_fastpath *fp = &bp->fp[i];
936
937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
939 for (j = start; j != end; j = RX_BD(j + 1)) {
940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
942
943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
945 }
946
947 start = RX_SGE(fp->rx_sge_prod);
948 end = RX_SGE(fp->last_max_sge);
949 for (j = start; j != end; j = RX_SGE(j + 1)) {
950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
952
953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954 i, j, rx_sge[1], rx_sge[0], sw_page->page);
955 }
956
957 start = RCQ_BD(fp->rx_comp_cons - 10);
958 end = RCQ_BD(fp->rx_comp_cons + 503);
959 for (j = start; j != end; j = RCQ_BD(j + 1)) {
960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
961
962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
964 }
965 }
966
967 /* Tx */
968 for_each_tx_queue(bp, i) {
969 struct bnx2x_fastpath *fp = &bp->fp[i];
970 for_each_cos_in_tx_queue(fp, cos) {
971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
972
973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 struct sw_tx_bd *sw_bd =
977 &txdata->tx_buf_ring[j];
978
979 BNX2X_ERR("fp%d: txdata %d, "
980 "packet[%x]=[%p,%x]\n",
981 i, cos, j, sw_bd->skb,
982 sw_bd->first_bd);
983 }
984
985 start = TX_BD(txdata->tx_bd_cons - 10);
986 end = TX_BD(txdata->tx_bd_cons + 254);
987 for (j = start; j != end; j = TX_BD(j + 1)) {
988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
989
990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
991 "[%x:%x:%x:%x]\n",
992 i, cos, j, tx_bd[0], tx_bd[1],
993 tx_bd[2], tx_bd[3]);
994 }
995 }
996 }
997 #endif
998 bnx2x_fw_dump(bp);
999 bnx2x_mc_assert(bp);
1000 BNX2X_ERR("end crash dump -----------------\n");
1001 }
1002
1003 /*
1004 * FLR Support for E2
1005 *
1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1007 * initialization.
1008 */
1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010 #define FLR_WAIT_INTERAVAL 50 /* usec */
1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1012
1013 struct pbf_pN_buf_regs {
1014 int pN;
1015 u32 init_crd;
1016 u32 crd;
1017 u32 crd_freed;
1018 };
1019
1020 struct pbf_pN_cmd_regs {
1021 int pN;
1022 u32 lines_occup;
1023 u32 lines_freed;
1024 };
1025
1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1027 struct pbf_pN_buf_regs *regs,
1028 u32 poll_count)
1029 {
1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1031 u32 cur_cnt = poll_count;
1032
1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1034 crd = crd_start = REG_RD(bp, regs->crd);
1035 init_crd = REG_RD(bp, regs->init_crd);
1036
1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1040
1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1042 (init_crd - crd_start))) {
1043 if (cur_cnt--) {
1044 udelay(FLR_WAIT_INTERAVAL);
1045 crd = REG_RD(bp, regs->crd);
1046 crd_freed = REG_RD(bp, regs->crd_freed);
1047 } else {
1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1049 regs->pN);
1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1051 regs->pN, crd);
1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1053 regs->pN, crd_freed);
1054 break;
1055 }
1056 }
1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1059 }
1060
1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1062 struct pbf_pN_cmd_regs *regs,
1063 u32 poll_count)
1064 {
1065 u32 occup, to_free, freed, freed_start;
1066 u32 cur_cnt = poll_count;
1067
1068 occup = to_free = REG_RD(bp, regs->lines_occup);
1069 freed = freed_start = REG_RD(bp, regs->lines_freed);
1070
1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1073
1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1075 if (cur_cnt--) {
1076 udelay(FLR_WAIT_INTERAVAL);
1077 occup = REG_RD(bp, regs->lines_occup);
1078 freed = REG_RD(bp, regs->lines_freed);
1079 } else {
1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1081 regs->pN);
1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1083 regs->pN, occup);
1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1085 regs->pN, freed);
1086 break;
1087 }
1088 }
1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1091 }
1092
1093 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1094 u32 expected, u32 poll_count)
1095 {
1096 u32 cur_cnt = poll_count;
1097 u32 val;
1098
1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1100 udelay(FLR_WAIT_INTERAVAL);
1101
1102 return val;
1103 }
1104
1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1106 char *msg, u32 poll_cnt)
1107 {
1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1109 if (val != 0) {
1110 BNX2X_ERR("%s usage count=%d\n", msg, val);
1111 return 1;
1112 }
1113 return 0;
1114 }
1115
1116 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1117 {
1118 /* adjust polling timeout */
1119 if (CHIP_REV_IS_EMUL(bp))
1120 return FLR_POLL_CNT * 2000;
1121
1122 if (CHIP_REV_IS_FPGA(bp))
1123 return FLR_POLL_CNT * 120;
1124
1125 return FLR_POLL_CNT;
1126 }
1127
1128 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1129 {
1130 struct pbf_pN_cmd_regs cmd_regs[] = {
1131 {0, (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_OCCUPANCY_Q0 :
1133 PBF_REG_P0_TQ_OCCUPANCY,
1134 (CHIP_IS_E3B0(bp)) ?
1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1136 PBF_REG_P0_TQ_LINES_FREED_CNT},
1137 {1, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_TQ_OCCUPANCY_Q1 :
1139 PBF_REG_P1_TQ_OCCUPANCY,
1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1142 PBF_REG_P1_TQ_LINES_FREED_CNT},
1143 {4, (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_TQ_OCCUPANCY_LB_Q :
1145 PBF_REG_P4_TQ_OCCUPANCY,
1146 (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1148 PBF_REG_P4_TQ_LINES_FREED_CNT}
1149 };
1150
1151 struct pbf_pN_buf_regs buf_regs[] = {
1152 {0, (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INIT_CRD_Q0 :
1154 PBF_REG_P0_INIT_CRD ,
1155 (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_CREDIT_Q0 :
1157 PBF_REG_P0_CREDIT,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1161 {1, (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INIT_CRD_Q1 :
1163 PBF_REG_P1_INIT_CRD,
1164 (CHIP_IS_E3B0(bp)) ?
1165 PBF_REG_CREDIT_Q1 :
1166 PBF_REG_P1_CREDIT,
1167 (CHIP_IS_E3B0(bp)) ?
1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1170 {4, (CHIP_IS_E3B0(bp)) ?
1171 PBF_REG_INIT_CRD_LB_Q :
1172 PBF_REG_P4_INIT_CRD,
1173 (CHIP_IS_E3B0(bp)) ?
1174 PBF_REG_CREDIT_LB_Q :
1175 PBF_REG_P4_CREDIT,
1176 (CHIP_IS_E3B0(bp)) ?
1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1179 };
1180
1181 int i;
1182
1183 /* Verify the command queues are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1186
1187
1188 /* Verify the transmission buffers are flushed P0, P1, P4 */
1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1191 }
1192
1193 #define OP_GEN_PARAM(param) \
1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1195
1196 #define OP_GEN_TYPE(type) \
1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1198
1199 #define OP_GEN_AGG_VECT(index) \
1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1201
1202
1203 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1204 u32 poll_cnt)
1205 {
1206 struct sdm_op_gen op_gen = {0};
1207
1208 u32 comp_addr = BAR_CSTRORM_INTMEM +
1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1210 int ret = 0;
1211
1212 if (REG_RD(bp, comp_addr)) {
1213 BNX2X_ERR("Cleanup complete is not 0\n");
1214 return 1;
1215 }
1216
1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1221
1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1224
1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1226 BNX2X_ERR("FW final cleanup did not succeed\n");
1227 ret = 1;
1228 }
1229 /* Zero completion for nxt FLR */
1230 REG_WR(bp, comp_addr, 0);
1231
1232 return ret;
1233 }
1234
1235 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1236 {
1237 int pos;
1238 u16 status;
1239
1240 pos = pci_pcie_cap(dev);
1241 if (!pos)
1242 return false;
1243
1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1245 return status & PCI_EXP_DEVSTA_TRPND;
1246 }
1247
1248 /* PF FLR specific routines
1249 */
1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1251 {
1252
1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 CFC_REG_NUM_LCIDS_INSIDE_PF,
1256 "CFC PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260
1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1263 DORQ_REG_PF_USAGE_CNT,
1264 "DQ PF usage counter timed out",
1265 poll_cnt))
1266 return 1;
1267
1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1271 "QM PF usage counter timed out",
1272 poll_cnt))
1273 return 1;
1274
1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1278 "Timers VNIC usage counter timed out",
1279 poll_cnt))
1280 return 1;
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1283 "Timers NUM_SCANS usage counter timed out",
1284 poll_cnt))
1285 return 1;
1286
1287 /* Wait DMAE PF usage counter to zero */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289 dmae_reg_go_c[INIT_DMAE_C(bp)],
1290 "DMAE dommand register timed out",
1291 poll_cnt))
1292 return 1;
1293
1294 return 0;
1295 }
1296
1297 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1298 {
1299 u32 val;
1300
1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1303
1304 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1306
1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1309
1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1312
1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1315
1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1318
1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1321
1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1324 val);
1325 }
1326
1327 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1328 {
1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1330
1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1332
1333 /* Re-enable PF target read access */
1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1335
1336 /* Poll HW usage counters */
1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1338 return -EBUSY;
1339
1340 /* Zero the igu 'trailing edge' and 'leading edge' */
1341
1342 /* Send the FW cleanup command */
1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1344 return -EBUSY;
1345
1346 /* ATC cleanup */
1347
1348 /* Verify TX hw is flushed */
1349 bnx2x_tx_hw_flushed(bp, poll_cnt);
1350
1351 /* Wait 100ms (not adjusted according to platform) */
1352 msleep(100);
1353
1354 /* Verify no pending pci transactions */
1355 if (bnx2x_is_pcie_pending(bp->pdev))
1356 BNX2X_ERR("PCIE Transactions still pending\n");
1357
1358 /* Debug */
1359 bnx2x_hw_enable_status(bp);
1360
1361 /*
1362 * Master enable - Due to WB DMAE writes performed before this
1363 * register is re-initialized as part of the regular function init
1364 */
1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1366
1367 return 0;
1368 }
1369
1370 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1371 {
1372 int port = BP_PORT(bp);
1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1374 u32 val = REG_RD(bp, addr);
1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1377
1378 if (msix) {
1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1380 HC_CONFIG_0_REG_INT_LINE_EN_0);
1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1383 } else if (msi) {
1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1388 } else {
1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1391 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1393
1394 if (!CHIP_IS_E1(bp)) {
1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1396 val, port, addr);
1397
1398 REG_WR(bp, addr, val);
1399
1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1401 }
1402 }
1403
1404 if (CHIP_IS_E1(bp))
1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1406
1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1409
1410 REG_WR(bp, addr, val);
1411 /*
1412 * Ensure that HC_CONFIG is written before leading/trailing edge config
1413 */
1414 mmiowb();
1415 barrier();
1416
1417 if (!CHIP_IS_E1(bp)) {
1418 /* init leading/trailing edge */
1419 if (IS_MF(bp)) {
1420 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1421 if (bp->port.pmf)
1422 /* enable nig and gpio3 attention */
1423 val |= 0x1100;
1424 } else
1425 val = 0xffff;
1426
1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1429 }
1430
1431 /* Make sure that interrupts are indeed enabled from here on */
1432 mmiowb();
1433 }
1434
1435 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1436 {
1437 u32 val;
1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1440
1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1442
1443 if (msix) {
1444 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 val |= (IGU_PF_CONF_FUNC_EN |
1447 IGU_PF_CONF_MSI_MSIX_EN |
1448 IGU_PF_CONF_ATTN_BIT_EN);
1449 } else if (msi) {
1450 val &= ~IGU_PF_CONF_INT_LINE_EN;
1451 val |= (IGU_PF_CONF_FUNC_EN |
1452 IGU_PF_CONF_MSI_MSIX_EN |
1453 IGU_PF_CONF_ATTN_BIT_EN |
1454 IGU_PF_CONF_SINGLE_ISR_EN);
1455 } else {
1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1457 val |= (IGU_PF_CONF_FUNC_EN |
1458 IGU_PF_CONF_INT_LINE_EN |
1459 IGU_PF_CONF_ATTN_BIT_EN |
1460 IGU_PF_CONF_SINGLE_ISR_EN);
1461 }
1462
1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1465
1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1467
1468 barrier();
1469
1470 /* init leading/trailing edge */
1471 if (IS_MF(bp)) {
1472 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1473 if (bp->port.pmf)
1474 /* enable nig and gpio3 attention */
1475 val |= 0x1100;
1476 } else
1477 val = 0xffff;
1478
1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1481
1482 /* Make sure that interrupts are indeed enabled from here on */
1483 mmiowb();
1484 }
1485
1486 void bnx2x_int_enable(struct bnx2x *bp)
1487 {
1488 if (bp->common.int_block == INT_BLOCK_HC)
1489 bnx2x_hc_int_enable(bp);
1490 else
1491 bnx2x_igu_int_enable(bp);
1492 }
1493
1494 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1495 {
1496 int port = BP_PORT(bp);
1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1498 u32 val = REG_RD(bp, addr);
1499
1500 /*
1501 * in E1 we must use only PCI configuration space to disable
1502 * MSI/MSIX capablility
1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1504 */
1505 if (CHIP_IS_E1(bp)) {
1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507 * Use mask register to prevent from HC sending interrupts
1508 * after we exit the function
1509 */
1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1511
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1515 } else
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1520
1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1522 val, port, addr);
1523
1524 /* flush all outstanding writes */
1525 mmiowb();
1526
1527 REG_WR(bp, addr, val);
1528 if (REG_RD(bp, addr) != val)
1529 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1530 }
1531
1532 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1533 {
1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1535
1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1537 IGU_PF_CONF_INT_LINE_EN |
1538 IGU_PF_CONF_ATTN_BIT_EN);
1539
1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1541
1542 /* flush all outstanding writes */
1543 mmiowb();
1544
1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1547 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1548 }
1549
1550 void bnx2x_int_disable(struct bnx2x *bp)
1551 {
1552 if (bp->common.int_block == INT_BLOCK_HC)
1553 bnx2x_hc_int_disable(bp);
1554 else
1555 bnx2x_igu_int_disable(bp);
1556 }
1557
1558 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1559 {
1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1561 int i, offset;
1562
1563 if (disable_hw)
1564 /* prevent the HW from sending interrupts */
1565 bnx2x_int_disable(bp);
1566
1567 /* make sure all ISRs are done */
1568 if (msix) {
1569 synchronize_irq(bp->msix_table[0].vector);
1570 offset = 1;
1571 #ifdef BCM_CNIC
1572 offset++;
1573 #endif
1574 for_each_eth_queue(bp, i)
1575 synchronize_irq(bp->msix_table[offset++].vector);
1576 } else
1577 synchronize_irq(bp->pdev->irq);
1578
1579 /* make sure sp_task is not running */
1580 cancel_delayed_work(&bp->sp_task);
1581 cancel_delayed_work(&bp->period_task);
1582 flush_workqueue(bnx2x_wq);
1583 }
1584
1585 /* fast path */
1586
1587 /*
1588 * General service functions
1589 */
1590
1591 /* Return true if succeeded to acquire the lock */
1592 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1593 {
1594 u32 lock_status;
1595 u32 resource_bit = (1 << resource);
1596 int func = BP_FUNC(bp);
1597 u32 hw_lock_control_reg;
1598
1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1600
1601 /* Validating that the resource is within range */
1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1603 DP(NETIF_MSG_HW,
1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1606 return false;
1607 }
1608
1609 if (func <= 5)
1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1611 else
1612 hw_lock_control_reg =
1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1614
1615 /* Try to acquire the lock */
1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1617 lock_status = REG_RD(bp, hw_lock_control_reg);
1618 if (lock_status & resource_bit)
1619 return true;
1620
1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1622 return false;
1623 }
1624
1625 /**
1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1627 *
1628 * @bp: driver handle
1629 *
1630 * Returns the recovery leader resource id according to the engine this function
1631 * belongs to. Currently only only 2 engines is supported.
1632 */
1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1634 {
1635 if (BP_PATH(bp))
1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1637 else
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1639 }
1640
1641 /**
1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1643 *
1644 * @bp: driver handle
1645 *
1646 * Tries to aquire a leader lock for cuurent engine.
1647 */
1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1649 {
1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1651 }
1652
1653 #ifdef BCM_CNIC
1654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1655 #endif
1656
1657 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1658 {
1659 struct bnx2x *bp = fp->bp;
1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1664
1665 DP(BNX2X_MSG_SP,
1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1667 fp->index, cid, command, bp->state,
1668 rr_cqe->ramrod_cqe.ramrod_type);
1669
1670 switch (command) {
1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1673 drv_cmd = BNX2X_Q_CMD_UPDATE;
1674 break;
1675
1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1678 drv_cmd = BNX2X_Q_CMD_SETUP;
1679 break;
1680
1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1684 break;
1685
1686 case (RAMROD_CMD_ID_ETH_HALT):
1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1688 drv_cmd = BNX2X_Q_CMD_HALT;
1689 break;
1690
1691 case (RAMROD_CMD_ID_ETH_TERMINATE):
1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1693 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1694 break;
1695
1696 case (RAMROD_CMD_ID_ETH_EMPTY):
1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1698 drv_cmd = BNX2X_Q_CMD_EMPTY;
1699 break;
1700
1701 default:
1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703 command, fp->index);
1704 return;
1705 }
1706
1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1708 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1709 /* q_obj->complete_cmd() failure means that this was
1710 * an unexpected completion.
1711 *
1712 * In this case we don't want to increase the bp->spq_left
1713 * because apparently we haven't sent this command the first
1714 * place.
1715 */
1716 #ifdef BNX2X_STOP_ON_ERROR
1717 bnx2x_panic();
1718 #else
1719 return;
1720 #endif
1721
1722 smp_mb__before_atomic_inc();
1723 atomic_inc(&bp->cq_spq_left);
1724 /* push the change in bp->spq_left and towards the memory */
1725 smp_mb__after_atomic_inc();
1726
1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1728
1729 return;
1730 }
1731
1732 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734 {
1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736
1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1738 start);
1739 }
1740
1741 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1742 {
1743 struct bnx2x *bp = netdev_priv(dev_instance);
1744 u16 status = bnx2x_ack_int(bp);
1745 u16 mask;
1746 int i;
1747 u8 cos;
1748
1749 /* Return here if interrupt is shared and it's not for us */
1750 if (unlikely(status == 0)) {
1751 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1752 return IRQ_NONE;
1753 }
1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1755
1756 #ifdef BNX2X_STOP_ON_ERROR
1757 if (unlikely(bp->panic))
1758 return IRQ_HANDLED;
1759 #endif
1760
1761 for_each_eth_queue(bp, i) {
1762 struct bnx2x_fastpath *fp = &bp->fp[i];
1763
1764 mask = 0x2 << (fp->index + CNIC_PRESENT);
1765 if (status & mask) {
1766 /* Handle Rx or Tx according to SB id */
1767 prefetch(fp->rx_cons_sb);
1768 for_each_cos_in_tx_queue(fp, cos)
1769 prefetch(fp->txdata[cos].tx_cons_sb);
1770 prefetch(&fp->sb_running_index[SM_RX_ID]);
1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1772 status &= ~mask;
1773 }
1774 }
1775
1776 #ifdef BCM_CNIC
1777 mask = 0x2;
1778 if (status & (mask | 0x1)) {
1779 struct cnic_ops *c_ops = NULL;
1780
1781 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 rcu_read_lock();
1783 c_ops = rcu_dereference(bp->cnic_ops);
1784 if (c_ops)
1785 c_ops->cnic_handler(bp->cnic_data, NULL);
1786 rcu_read_unlock();
1787 }
1788
1789 status &= ~mask;
1790 }
1791 #endif
1792
1793 if (unlikely(status & 0x1)) {
1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795
1796 status &= ~0x1;
1797 if (!status)
1798 return IRQ_HANDLED;
1799 }
1800
1801 if (unlikely(status))
1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1803 status);
1804
1805 return IRQ_HANDLED;
1806 }
1807
1808 /* Link */
1809
1810 /*
1811 * General service functions
1812 */
1813
1814 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1815 {
1816 u32 lock_status;
1817 u32 resource_bit = (1 << resource);
1818 int func = BP_FUNC(bp);
1819 u32 hw_lock_control_reg;
1820 int cnt;
1821
1822 /* Validating that the resource is within range */
1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 DP(NETIF_MSG_HW,
1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1827 return -EINVAL;
1828 }
1829
1830 if (func <= 5) {
1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 } else {
1833 hw_lock_control_reg =
1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1835 }
1836
1837 /* Validating that the resource is not already taken */
1838 lock_status = REG_RD(bp, hw_lock_control_reg);
1839 if (lock_status & resource_bit) {
1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1841 lock_status, resource_bit);
1842 return -EEXIST;
1843 }
1844
1845 /* Try for 5 second every 5ms */
1846 for (cnt = 0; cnt < 1000; cnt++) {
1847 /* Try to acquire the lock */
1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (lock_status & resource_bit)
1851 return 0;
1852
1853 msleep(5);
1854 }
1855 DP(NETIF_MSG_HW, "Timeout\n");
1856 return -EAGAIN;
1857 }
1858
1859 int bnx2x_release_leader_lock(struct bnx2x *bp)
1860 {
1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1862 }
1863
1864 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1865 {
1866 u32 lock_status;
1867 u32 resource_bit = (1 << resource);
1868 int func = BP_FUNC(bp);
1869 u32 hw_lock_control_reg;
1870
1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872
1873 /* Validating that the resource is within range */
1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 DP(NETIF_MSG_HW,
1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1878 return -EINVAL;
1879 }
1880
1881 if (func <= 5) {
1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 } else {
1884 hw_lock_control_reg =
1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1886 }
1887
1888 /* Validating that the resource is currently taken */
1889 lock_status = REG_RD(bp, hw_lock_control_reg);
1890 if (!(lock_status & resource_bit)) {
1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1892 lock_status, resource_bit);
1893 return -EFAULT;
1894 }
1895
1896 REG_WR(bp, hw_lock_control_reg, resource_bit);
1897 return 0;
1898 }
1899
1900
1901 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902 {
1903 /* The GPIO should be swapped if swap register is set and active */
1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1906 int gpio_shift = gpio_num +
1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1908 u32 gpio_mask = (1 << gpio_shift);
1909 u32 gpio_reg;
1910 int value;
1911
1912 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1914 return -EINVAL;
1915 }
1916
1917 /* read GPIO value */
1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919
1920 /* get the requested pin value */
1921 if ((gpio_reg & gpio_mask) == gpio_mask)
1922 value = 1;
1923 else
1924 value = 0;
1925
1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1927
1928 return value;
1929 }
1930
1931 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1932 {
1933 /* The GPIO should be swapped if swap register is set and active */
1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1936 int gpio_shift = gpio_num +
1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1938 u32 gpio_mask = (1 << gpio_shift);
1939 u32 gpio_reg;
1940
1941 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1943 return -EINVAL;
1944 }
1945
1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947 /* read GPIO and mask except the float bits */
1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1949
1950 switch (mode) {
1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1953 gpio_num, gpio_shift);
1954 /* clear FLOAT and set CLR */
1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1957 break;
1958
1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1961 gpio_num, gpio_shift);
1962 /* clear FLOAT and set SET */
1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1965 break;
1966
1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1969 gpio_num, gpio_shift);
1970 /* set FLOAT */
1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 break;
1973
1974 default:
1975 break;
1976 }
1977
1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1980
1981 return 0;
1982 }
1983
1984 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1985 {
1986 u32 gpio_reg = 0;
1987 int rc = 0;
1988
1989 /* Any port swapping should be handled by caller. */
1990
1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1997
1998 switch (mode) {
1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 /* set CLR */
2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2003 break;
2004
2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 /* set SET */
2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2009 break;
2010
2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 /* set FLOAT */
2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2015 break;
2016
2017 default:
2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2019 rc = -EINVAL;
2020 break;
2021 }
2022
2023 if (rc == 0)
2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025
2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2027
2028 return rc;
2029 }
2030
2031 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 {
2033 /* The GPIO should be swapped if swap register is set and active */
2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2036 int gpio_shift = gpio_num +
2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2038 u32 gpio_mask = (1 << gpio_shift);
2039 u32 gpio_reg;
2040
2041 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2043 return -EINVAL;
2044 }
2045
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 /* read GPIO int */
2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2049
2050 switch (mode) {
2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2053 "output low\n", gpio_num, gpio_shift);
2054 /* clear SET and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2057 break;
2058
2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2061 "output high\n", gpio_num, gpio_shift);
2062 /* clear CLR and set SET */
2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2065 break;
2066
2067 default:
2068 break;
2069 }
2070
2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2073
2074 return 0;
2075 }
2076
2077 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2078 {
2079 u32 spio_mask = (1 << spio_num);
2080 u32 spio_reg;
2081
2082 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2083 (spio_num > MISC_REGISTERS_SPIO_7)) {
2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2085 return -EINVAL;
2086 }
2087
2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2089 /* read SPIO and mask except the float bits */
2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2091
2092 switch (mode) {
2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2095 /* clear FLOAT and set CLR */
2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2098 break;
2099
2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2102 /* clear FLOAT and set SET */
2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2105 break;
2106
2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 /* set FLOAT */
2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2111 break;
2112
2113 default:
2114 break;
2115 }
2116
2117 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2119
2120 return 0;
2121 }
2122
2123 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2124 {
2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2126 switch (bp->link_vars.ieee_fc &
2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2130 ADVERTISED_Pause);
2131 break;
2132
2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2135 ADVERTISED_Pause);
2136 break;
2137
2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2140 break;
2141
2142 default:
2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2144 ADVERTISED_Pause);
2145 break;
2146 }
2147 }
2148
2149 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2150 {
2151 if (!BP_NOMCP(bp)) {
2152 u8 rc;
2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2155 /*
2156 * Initialize link parameters structure variables
2157 * It is recommended to turn off RX FC for jumbo frames
2158 * for better performance
2159 */
2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2162 else
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2164
2165 bnx2x_acquire_phy_lock(bp);
2166
2167 if (load_mode == LOAD_DIAG) {
2168 struct link_params *lp = &bp->link_params;
2169 lp->loopback_mode = LOOPBACK_XGXS;
2170 /* do PHY loopback at 10G speed, if possible */
2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2172 if (lp->speed_cap_mask[cfx_idx] &
2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2174 lp->req_line_speed[cfx_idx] =
2175 SPEED_10000;
2176 else
2177 lp->req_line_speed[cfx_idx] =
2178 SPEED_1000;
2179 }
2180 }
2181
2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2183
2184 bnx2x_release_phy_lock(bp);
2185
2186 bnx2x_calc_fc_adv(bp);
2187
2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2190 bnx2x_link_report(bp);
2191 } else
2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2194 return rc;
2195 }
2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2197 return -EINVAL;
2198 }
2199
2200 void bnx2x_link_set(struct bnx2x *bp)
2201 {
2202 if (!BP_NOMCP(bp)) {
2203 bnx2x_acquire_phy_lock(bp);
2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2206 bnx2x_release_phy_lock(bp);
2207
2208 bnx2x_calc_fc_adv(bp);
2209 } else
2210 BNX2X_ERR("Bootcode is missing - can not set link\n");
2211 }
2212
2213 static void bnx2x__link_reset(struct bnx2x *bp)
2214 {
2215 if (!BP_NOMCP(bp)) {
2216 bnx2x_acquire_phy_lock(bp);
2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2218 bnx2x_release_phy_lock(bp);
2219 } else
2220 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2221 }
2222
2223 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2224 {
2225 u8 rc = 0;
2226
2227 if (!BP_NOMCP(bp)) {
2228 bnx2x_acquire_phy_lock(bp);
2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2230 is_serdes);
2231 bnx2x_release_phy_lock(bp);
2232 } else
2233 BNX2X_ERR("Bootcode is missing - can not test link\n");
2234
2235 return rc;
2236 }
2237
2238 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2239 {
2240 u32 r_param = bp->link_vars.line_speed / 8;
2241 u32 fair_periodic_timeout_usec;
2242 u32 t_fair;
2243
2244 memset(&(bp->cmng.rs_vars), 0,
2245 sizeof(struct rate_shaping_vars_per_port));
2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2247
2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2250
2251 /* this is the threshold below which no timer arming will occur
2252 1.25 coefficient is for the threshold to be a little bigger
2253 than the real time, to compensate for timer in-accuracy */
2254 bp->cmng.rs_vars.rs_threshold =
2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2256
2257 /* resolution of fairness timer */
2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2261
2262 /* this is the threshold below which we won't arm the timer anymore */
2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2264
2265 /* we multiply by 1e3/8 to get bytes/msec.
2266 We don't want the credits to pass a credit
2267 of the t_fair*FAIR_MEM (algorithm resolution) */
2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2269 /* since each tick is 4 usec */
2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2271 }
2272
2273 /* Calculates the sum of vn_min_rates.
2274 It's needed for further normalizing of the min_rates.
2275 Returns:
2276 sum of vn_min_rates.
2277 or
2278 0 - if all the min_rates are 0.
2279 In the later case fainess algorithm should be deactivated.
2280 If not all min_rates are zero then those that are zeroes will be set to 1.
2281 */
2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2283 {
2284 int all_zero = 1;
2285 int vn;
2286
2287 bp->vn_weight_sum = 0;
2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2289 u32 vn_cfg = bp->mf_config[vn];
2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2292
2293 /* Skip hidden vns */
2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2295 continue;
2296
2297 /* If min rate is zero - set it to 1 */
2298 if (!vn_min_rate)
2299 vn_min_rate = DEF_MIN_RATE;
2300 else
2301 all_zero = 0;
2302
2303 bp->vn_weight_sum += vn_min_rate;
2304 }
2305
2306 /* if ETS or all min rates are zeros - disable fairness */
2307 if (BNX2X_IS_ETS_ENABLED(bp)) {
2308 bp->cmng.flags.cmng_enables &=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2311 } else if (all_zero) {
2312 bp->cmng.flags.cmng_enables &=
2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2315 " fairness will be disabled\n");
2316 } else
2317 bp->cmng.flags.cmng_enables |=
2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2319 }
2320
2321 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2322 {
2323 struct rate_shaping_vars_per_vn m_rs_vn;
2324 struct fairness_vars_per_vn m_fair_vn;
2325 u32 vn_cfg = bp->mf_config[vn];
2326 int func = func_by_vn(bp, vn);
2327 u16 vn_min_rate, vn_max_rate;
2328 int i;
2329
2330 /* If function is hidden - set min and max to zeroes */
2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2332 vn_min_rate = 0;
2333 vn_max_rate = 0;
2334
2335 } else {
2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2337
2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2340 /* If fairness is enabled (not all min rates are zeroes) and
2341 if current min rate is zero - set it to 1.
2342 This is a requirement of the algorithm. */
2343 if (bp->vn_weight_sum && (vn_min_rate == 0))
2344 vn_min_rate = DEF_MIN_RATE;
2345
2346 if (IS_MF_SI(bp))
2347 /* maxCfg in percents of linkspeed */
2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2349 else
2350 /* maxCfg is absolute in 100Mb units */
2351 vn_max_rate = maxCfg * 100;
2352 }
2353
2354 DP(NETIF_MSG_IFUP,
2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2357
2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2360
2361 /* global vn counter - maximal Mbps for this vn */
2362 m_rs_vn.vn_counter.rate = vn_max_rate;
2363
2364 /* quota - number of bytes transmitted in this period */
2365 m_rs_vn.vn_counter.quota =
2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2367
2368 if (bp->vn_weight_sum) {
2369 /* credit for each period of the fairness algorithm:
2370 number of bytes in T_FAIR (the vn share the port rate).
2371 vn_weight_sum should not be larger than 10000, thus
2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2373 than zero */
2374 m_fair_vn.vn_credit_delta =
2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2376 (8 * bp->vn_weight_sum))),
2377 (bp->cmng.fair_vars.fair_threshold +
2378 MIN_ABOVE_THRESH));
2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2380 m_fair_vn.vn_credit_delta);
2381 }
2382
2383 /* Store it to internal memory */
2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2385 REG_WR(bp, BAR_XSTRORM_INTMEM +
2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2387 ((u32 *)(&m_rs_vn))[i]);
2388
2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2390 REG_WR(bp, BAR_XSTRORM_INTMEM +
2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2392 ((u32 *)(&m_fair_vn))[i]);
2393 }
2394
2395 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2396 {
2397 if (CHIP_REV_IS_SLOW(bp))
2398 return CMNG_FNS_NONE;
2399 if (IS_MF(bp))
2400 return CMNG_FNS_MINMAX;
2401
2402 return CMNG_FNS_NONE;
2403 }
2404
2405 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2406 {
2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2408
2409 if (BP_NOMCP(bp))
2410 return; /* what should be the default bvalue in this case */
2411
2412 /* For 2 port configuration the absolute function number formula
2413 * is:
2414 * abs_func = 2 * vn + BP_PORT + BP_PATH
2415 *
2416 * and there are 4 functions per port
2417 *
2418 * For 4 port configuration it is
2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2420 *
2421 * and there are 2 functions per port
2422 */
2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2425
2426 if (func >= E1H_FUNC_MAX)
2427 break;
2428
2429 bp->mf_config[vn] =
2430 MF_CFG_RD(bp, func_mf_config[func].config);
2431 }
2432 }
2433
2434 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2435 {
2436
2437 if (cmng_type == CMNG_FNS_MINMAX) {
2438 int vn;
2439
2440 /* clear cmng_enables */
2441 bp->cmng.flags.cmng_enables = 0;
2442
2443 /* read mf conf from shmem */
2444 if (read_cfg)
2445 bnx2x_read_mf_cfg(bp);
2446
2447 /* Init rate shaping and fairness contexts */
2448 bnx2x_init_port_minmax(bp);
2449
2450 /* vn_weight_sum and enable fairness if not 0 */
2451 bnx2x_calc_vn_weight_sum(bp);
2452
2453 /* calculate and set min-max rate for each vn */
2454 if (bp->port.pmf)
2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2456 bnx2x_init_vn_minmax(bp, vn);
2457
2458 /* always enable rate shaping and fairness */
2459 bp->cmng.flags.cmng_enables |=
2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2461 if (!bp->vn_weight_sum)
2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2463 " fairness will be disabled\n");
2464 return;
2465 }
2466
2467 /* rate shaping and fairness are disabled */
2468 DP(NETIF_MSG_IFUP,
2469 "rate shaping and fairness are disabled\n");
2470 }
2471
2472 /* This function is called upon link interrupt */
2473 static void bnx2x_link_attn(struct bnx2x *bp)
2474 {
2475 /* Make sure that we are synced with the current statistics */
2476 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2477
2478 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2479
2480 if (bp->link_vars.link_up) {
2481
2482 /* dropless flow control */
2483 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2484 int port = BP_PORT(bp);
2485 u32 pause_enabled = 0;
2486
2487 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2488 pause_enabled = 1;
2489
2490 REG_WR(bp, BAR_USTRORM_INTMEM +
2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2492 pause_enabled);
2493 }
2494
2495 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2496 struct host_port_stats *pstats;
2497
2498 pstats = bnx2x_sp(bp, port_stats);
2499 /* reset old mac stats */
2500 memset(&(pstats->mac_stx[0]), 0,
2501 sizeof(struct mac_stx));
2502 }
2503 if (bp->state == BNX2X_STATE_OPEN)
2504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2505 }
2506
2507 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2508 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2509
2510 if (cmng_fns != CMNG_FNS_NONE) {
2511 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2512 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2513 } else
2514 /* rate shaping and fairness are disabled */
2515 DP(NETIF_MSG_IFUP,
2516 "single function mode without fairness\n");
2517 }
2518
2519 __bnx2x_link_report(bp);
2520
2521 if (IS_MF(bp))
2522 bnx2x_link_sync_notify(bp);
2523 }
2524
2525 void bnx2x__link_status_update(struct bnx2x *bp)
2526 {
2527 if (bp->state != BNX2X_STATE_OPEN)
2528 return;
2529
2530 /* read updated dcb configuration */
2531 bnx2x_dcbx_pmf_update(bp);
2532
2533 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2534
2535 if (bp->link_vars.link_up)
2536 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2537 else
2538 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2539
2540 /* indicate link status */
2541 bnx2x_link_report(bp);
2542 }
2543
2544 static void bnx2x_pmf_update(struct bnx2x *bp)
2545 {
2546 int port = BP_PORT(bp);
2547 u32 val;
2548
2549 bp->port.pmf = 1;
2550 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2551
2552 /*
2553 * We need the mb() to ensure the ordering between the writing to
2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2555 */
2556 smp_mb();
2557
2558 /* queue a periodic task */
2559 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2560
2561 bnx2x_dcbx_pmf_update(bp);
2562
2563 /* enable nig attention */
2564 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2565 if (bp->common.int_block == INT_BLOCK_HC) {
2566 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2567 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2568 } else if (!CHIP_IS_E1x(bp)) {
2569 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2570 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2571 }
2572
2573 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2574 }
2575
2576 /* end of Link */
2577
2578 /* slow path */
2579
2580 /*
2581 * General service functions
2582 */
2583
2584 /* send the MCP a request, block until there is a reply */
2585 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2586 {
2587 int mb_idx = BP_FW_MB_IDX(bp);
2588 u32 seq;
2589 u32 rc = 0;
2590 u32 cnt = 1;
2591 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2592
2593 mutex_lock(&bp->fw_mb_mutex);
2594 seq = ++bp->fw_seq;
2595 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2597
2598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2599 (command | seq), param);
2600
2601 do {
2602 /* let the FW do it's magic ... */
2603 msleep(delay);
2604
2605 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2606
2607 /* Give the FW up to 5 second (500*10ms) */
2608 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2609
2610 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2611 cnt*delay, rc, seq);
2612
2613 /* is this a reply to our command? */
2614 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2615 rc &= FW_MSG_CODE_MASK;
2616 else {
2617 /* FW BUG! */
2618 BNX2X_ERR("FW failed to respond!\n");
2619 bnx2x_fw_dump(bp);
2620 rc = 0;
2621 }
2622 mutex_unlock(&bp->fw_mb_mutex);
2623
2624 return rc;
2625 }
2626
2627 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2628 {
2629 #ifdef BCM_CNIC
2630 /* Statistics are not supported for CNIC Clients at the moment */
2631 if (IS_FCOE_FP(fp))
2632 return false;
2633 #endif
2634 return true;
2635 }
2636
2637 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2638 {
2639 if (CHIP_IS_E1x(bp)) {
2640 struct tstorm_eth_function_common_config tcfg = {0};
2641
2642 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2643 }
2644
2645 /* Enable the function in the FW */
2646 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2647 storm_memset_func_en(bp, p->func_id, 1);
2648
2649 /* spq */
2650 if (p->func_flgs & FUNC_FLG_SPQ) {
2651 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2652 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2653 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2654 }
2655 }
2656
2657 /**
2658 * bnx2x_get_tx_only_flags - Return common flags
2659 *
2660 * @bp device handle
2661 * @fp queue handle
2662 * @zero_stats TRUE if statistics zeroing is needed
2663 *
2664 * Return the flags that are common for the Tx-only and not normal connections.
2665 */
2666 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2667 struct bnx2x_fastpath *fp,
2668 bool zero_stats)
2669 {
2670 unsigned long flags = 0;
2671
2672 /* PF driver will always initialize the Queue to an ACTIVE state */
2673 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2674
2675 /* tx only connections collect statistics (on the same index as the
2676 * parent connection). The statistics are zeroed when the parent
2677 * connection is initialized.
2678 */
2679 if (stat_counter_valid(bp, fp)) {
2680 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2681 if (zero_stats)
2682 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2683 }
2684
2685 return flags;
2686 }
2687
2688 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2689 struct bnx2x_fastpath *fp,
2690 bool leading)
2691 {
2692 unsigned long flags = 0;
2693
2694 /* calculate other queue flags */
2695 if (IS_MF_SD(bp))
2696 __set_bit(BNX2X_Q_FLG_OV, &flags);
2697
2698 if (IS_FCOE_FP(fp))
2699 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2700
2701 if (!fp->disable_tpa) {
2702 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2703 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2704 }
2705
2706 if (leading) {
2707 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2708 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2709 }
2710
2711 /* Always set HW VLAN stripping */
2712 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2713
2714
2715 return flags | bnx2x_get_common_flags(bp, fp, true);
2716 }
2717
2718 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2719 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2720 u8 cos)
2721 {
2722 gen_init->stat_id = bnx2x_stats_id(fp);
2723 gen_init->spcl_id = fp->cl_id;
2724
2725 /* Always use mini-jumbo MTU for FCoE L2 ring */
2726 if (IS_FCOE_FP(fp))
2727 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2728 else
2729 gen_init->mtu = bp->dev->mtu;
2730
2731 gen_init->cos = cos;
2732 }
2733
2734 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2735 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2736 struct bnx2x_rxq_setup_params *rxq_init)
2737 {
2738 u8 max_sge = 0;
2739 u16 sge_sz = 0;
2740 u16 tpa_agg_size = 0;
2741
2742 if (!fp->disable_tpa) {
2743 pause->sge_th_lo = SGE_TH_LO(bp);
2744 pause->sge_th_hi = SGE_TH_HI(bp);
2745
2746 /* validate SGE ring has enough to cross high threshold */
2747 WARN_ON(bp->dropless_fc &&
2748 pause->sge_th_hi + FW_PREFETCH_CNT >
2749 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2750
2751 tpa_agg_size = min_t(u32,
2752 (min_t(u32, 8, MAX_SKB_FRAGS) *
2753 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2754 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2755 SGE_PAGE_SHIFT;
2756 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2757 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2758 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2759 0xffff);
2760 }
2761
2762 /* pause - not for e1 */
2763 if (!CHIP_IS_E1(bp)) {
2764 pause->bd_th_lo = BD_TH_LO(bp);
2765 pause->bd_th_hi = BD_TH_HI(bp);
2766
2767 pause->rcq_th_lo = RCQ_TH_LO(bp);
2768 pause->rcq_th_hi = RCQ_TH_HI(bp);
2769 /*
2770 * validate that rings have enough entries to cross
2771 * high thresholds
2772 */
2773 WARN_ON(bp->dropless_fc &&
2774 pause->bd_th_hi + FW_PREFETCH_CNT >
2775 bp->rx_ring_size);
2776 WARN_ON(bp->dropless_fc &&
2777 pause->rcq_th_hi + FW_PREFETCH_CNT >
2778 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2779
2780 pause->pri_map = 1;
2781 }
2782
2783 /* rxq setup */
2784 rxq_init->dscr_map = fp->rx_desc_mapping;
2785 rxq_init->sge_map = fp->rx_sge_mapping;
2786 rxq_init->rcq_map = fp->rx_comp_mapping;
2787 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2788
2789 /* This should be a maximum number of data bytes that may be
2790 * placed on the BD (not including paddings).
2791 */
2792 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2793 IP_HEADER_ALIGNMENT_PADDING;
2794
2795 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2796 rxq_init->tpa_agg_sz = tpa_agg_size;
2797 rxq_init->sge_buf_sz = sge_sz;
2798 rxq_init->max_sges_pkt = max_sge;
2799 rxq_init->rss_engine_id = BP_FUNC(bp);
2800
2801 /* Maximum number or simultaneous TPA aggregation for this Queue.
2802 *
2803 * For PF Clients it should be the maximum avaliable number.
2804 * VF driver(s) may want to define it to a smaller value.
2805 */
2806 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2807
2808 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2809 rxq_init->fw_sb_id = fp->fw_sb_id;
2810
2811 if (IS_FCOE_FP(fp))
2812 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2813 else
2814 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2815 }
2816
2817 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2818 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2819 u8 cos)
2820 {
2821 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2822 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2823 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2824 txq_init->fw_sb_id = fp->fw_sb_id;
2825
2826 /*
2827 * set the tss leading client id for TX classfication ==
2828 * leading RSS client id
2829 */
2830 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2831
2832 if (IS_FCOE_FP(fp)) {
2833 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2834 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2835 }
2836 }
2837
2838 static void bnx2x_pf_init(struct bnx2x *bp)
2839 {
2840 struct bnx2x_func_init_params func_init = {0};
2841 struct event_ring_data eq_data = { {0} };
2842 u16 flags;
2843
2844 if (!CHIP_IS_E1x(bp)) {
2845 /* reset IGU PF statistics: MSIX + ATTN */
2846 /* PF */
2847 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2848 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2849 (CHIP_MODE_IS_4_PORT(bp) ?
2850 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2851 /* ATTN */
2852 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2853 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2854 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2855 (CHIP_MODE_IS_4_PORT(bp) ?
2856 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2857 }
2858
2859 /* function setup flags */
2860 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2861
2862 /* This flag is relevant for E1x only.
2863 * E2 doesn't have a TPA configuration in a function level.
2864 */
2865 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2866
2867 func_init.func_flgs = flags;
2868 func_init.pf_id = BP_FUNC(bp);
2869 func_init.func_id = BP_FUNC(bp);
2870 func_init.spq_map = bp->spq_mapping;
2871 func_init.spq_prod = bp->spq_prod_idx;
2872
2873 bnx2x_func_init(bp, &func_init);
2874
2875 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2876
2877 /*
2878 * Congestion management values depend on the link rate
2879 * There is no active link so initial link rate is set to 10 Gbps.
2880 * When the link comes up The congestion management values are
2881 * re-calculated according to the actual link rate.
2882 */
2883 bp->link_vars.line_speed = SPEED_10000;
2884 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2885
2886 /* Only the PMF sets the HW */
2887 if (bp->port.pmf)
2888 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2889
2890 /* init Event Queue */
2891 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2892 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2893 eq_data.producer = bp->eq_prod;
2894 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2895 eq_data.sb_id = DEF_SB_ID;
2896 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2897 }
2898
2899
2900 static void bnx2x_e1h_disable(struct bnx2x *bp)
2901 {
2902 int port = BP_PORT(bp);
2903
2904 bnx2x_tx_disable(bp);
2905
2906 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2907 }
2908
2909 static void bnx2x_e1h_enable(struct bnx2x *bp)
2910 {
2911 int port = BP_PORT(bp);
2912
2913 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2914
2915 /* Tx queue should be only reenabled */
2916 netif_tx_wake_all_queues(bp->dev);
2917
2918 /*
2919 * Should not call netif_carrier_on since it will be called if the link
2920 * is up when checking for link state
2921 */
2922 }
2923
2924 /* called due to MCP event (on pmf):
2925 * reread new bandwidth configuration
2926 * configure FW
2927 * notify others function about the change
2928 */
2929 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2930 {
2931 if (bp->link_vars.link_up) {
2932 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2933 bnx2x_link_sync_notify(bp);
2934 }
2935 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2936 }
2937
2938 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2939 {
2940 bnx2x_config_mf_bw(bp);
2941 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2942 }
2943
2944 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2945 {
2946 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2947
2948 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2949
2950 /*
2951 * This is the only place besides the function initialization
2952 * where the bp->flags can change so it is done without any
2953 * locks
2954 */
2955 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2956 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2957 bp->flags |= MF_FUNC_DIS;
2958
2959 bnx2x_e1h_disable(bp);
2960 } else {
2961 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2962 bp->flags &= ~MF_FUNC_DIS;
2963
2964 bnx2x_e1h_enable(bp);
2965 }
2966 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2967 }
2968 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2969 bnx2x_config_mf_bw(bp);
2970 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2971 }
2972
2973 /* Report results to MCP */
2974 if (dcc_event)
2975 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2976 else
2977 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2978 }
2979
2980 /* must be called under the spq lock */
2981 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2982 {
2983 struct eth_spe *next_spe = bp->spq_prod_bd;
2984
2985 if (bp->spq_prod_bd == bp->spq_last_bd) {
2986 bp->spq_prod_bd = bp->spq;
2987 bp->spq_prod_idx = 0;
2988 DP(NETIF_MSG_TIMER, "end of spq\n");
2989 } else {
2990 bp->spq_prod_bd++;
2991 bp->spq_prod_idx++;
2992 }
2993 return next_spe;
2994 }
2995
2996 /* must be called under the spq lock */
2997 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2998 {
2999 int func = BP_FUNC(bp);
3000
3001 /*
3002 * Make sure that BD data is updated before writing the producer:
3003 * BD data is written to the memory, the producer is read from the
3004 * memory, thus we need a full memory barrier to ensure the ordering.
3005 */
3006 mb();
3007
3008 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3009 bp->spq_prod_idx);
3010 mmiowb();
3011 }
3012
3013 /**
3014 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3015 *
3016 * @cmd: command to check
3017 * @cmd_type: command type
3018 */
3019 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3020 {
3021 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3022 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3023 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3024 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3025 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3026 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3027 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3028 return true;
3029 else
3030 return false;
3031
3032 }
3033
3034
3035 /**
3036 * bnx2x_sp_post - place a single command on an SP ring
3037 *
3038 * @bp: driver handle
3039 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3040 * @cid: SW CID the command is related to
3041 * @data_hi: command private data address (high 32 bits)
3042 * @data_lo: command private data address (low 32 bits)
3043 * @cmd_type: command type (e.g. NONE, ETH)
3044 *
3045 * SP data is handled as if it's always an address pair, thus data fields are
3046 * not swapped to little endian in upper functions. Instead this function swaps
3047 * data as if it's two u32 fields.
3048 */
3049 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3050 u32 data_hi, u32 data_lo, int cmd_type)
3051 {
3052 struct eth_spe *spe;
3053 u16 type;
3054 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3055
3056 #ifdef BNX2X_STOP_ON_ERROR
3057 if (unlikely(bp->panic))
3058 return -EIO;
3059 #endif
3060
3061 spin_lock_bh(&bp->spq_lock);
3062
3063 if (common) {
3064 if (!atomic_read(&bp->eq_spq_left)) {
3065 BNX2X_ERR("BUG! EQ ring full!\n");
3066 spin_unlock_bh(&bp->spq_lock);
3067 bnx2x_panic();
3068 return -EBUSY;
3069 }
3070 } else if (!atomic_read(&bp->cq_spq_left)) {
3071 BNX2X_ERR("BUG! SPQ ring full!\n");
3072 spin_unlock_bh(&bp->spq_lock);
3073 bnx2x_panic();
3074 return -EBUSY;
3075 }
3076
3077 spe = bnx2x_sp_get_next(bp);
3078
3079 /* CID needs port number to be encoded int it */
3080 spe->hdr.conn_and_cmd_data =
3081 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3082 HW_CID(bp, cid));
3083
3084 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3085
3086 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3087 SPE_HDR_FUNCTION_ID);
3088
3089 spe->hdr.type = cpu_to_le16(type);
3090
3091 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3092 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3093
3094 /*
3095 * It's ok if the actual decrement is issued towards the memory
3096 * somewhere between the spin_lock and spin_unlock. Thus no
3097 * more explict memory barrier is needed.
3098 */
3099 if (common)
3100 atomic_dec(&bp->eq_spq_left);
3101 else
3102 atomic_dec(&bp->cq_spq_left);
3103
3104
3105 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3107 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3108 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3109 (u32)(U64_LO(bp->spq_mapping) +
3110 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3111 HW_CID(bp, cid), data_hi, data_lo, type,
3112 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3113
3114 bnx2x_sp_prod_update(bp);
3115 spin_unlock_bh(&bp->spq_lock);
3116 return 0;
3117 }
3118
3119 /* acquire split MCP access lock register */
3120 static int bnx2x_acquire_alr(struct bnx2x *bp)
3121 {
3122 u32 j, val;
3123 int rc = 0;
3124
3125 might_sleep();
3126 for (j = 0; j < 1000; j++) {
3127 val = (1UL << 31);
3128 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3129 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3130 if (val & (1L << 31))
3131 break;
3132
3133 msleep(5);
3134 }
3135 if (!(val & (1L << 31))) {
3136 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3137 rc = -EBUSY;
3138 }
3139
3140 return rc;
3141 }
3142
3143 /* release split MCP access lock register */
3144 static void bnx2x_release_alr(struct bnx2x *bp)
3145 {
3146 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3147 }
3148
3149 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3150 #define BNX2X_DEF_SB_IDX 0x0002
3151
3152 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3153 {
3154 struct host_sp_status_block *def_sb = bp->def_status_blk;
3155 u16 rc = 0;
3156
3157 barrier(); /* status block is written to by the chip */
3158 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3159 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3160 rc |= BNX2X_DEF_SB_ATT_IDX;
3161 }
3162
3163 if (bp->def_idx != def_sb->sp_sb.running_index) {
3164 bp->def_idx = def_sb->sp_sb.running_index;
3165 rc |= BNX2X_DEF_SB_IDX;
3166 }
3167
3168 /* Do not reorder: indecies reading should complete before handling */
3169 barrier();
3170 return rc;
3171 }
3172
3173 /*
3174 * slow path service functions
3175 */
3176
3177 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3178 {
3179 int port = BP_PORT(bp);
3180 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3181 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3182 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3183 NIG_REG_MASK_INTERRUPT_PORT0;
3184 u32 aeu_mask;
3185 u32 nig_mask = 0;
3186 u32 reg_addr;
3187
3188 if (bp->attn_state & asserted)
3189 BNX2X_ERR("IGU ERROR\n");
3190
3191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3192 aeu_mask = REG_RD(bp, aeu_addr);
3193
3194 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3195 aeu_mask, asserted);
3196 aeu_mask &= ~(asserted & 0x3ff);
3197 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3198
3199 REG_WR(bp, aeu_addr, aeu_mask);
3200 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3201
3202 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3203 bp->attn_state |= asserted;
3204 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3205
3206 if (asserted & ATTN_HARD_WIRED_MASK) {
3207 if (asserted & ATTN_NIG_FOR_FUNC) {
3208
3209 bnx2x_acquire_phy_lock(bp);
3210
3211 /* save nig interrupt mask */
3212 nig_mask = REG_RD(bp, nig_int_mask_addr);
3213
3214 /* If nig_mask is not set, no need to call the update
3215 * function.
3216 */
3217 if (nig_mask) {
3218 REG_WR(bp, nig_int_mask_addr, 0);
3219
3220 bnx2x_link_attn(bp);
3221 }
3222
3223 /* handle unicore attn? */
3224 }
3225 if (asserted & ATTN_SW_TIMER_4_FUNC)
3226 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3227
3228 if (asserted & GPIO_2_FUNC)
3229 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3230
3231 if (asserted & GPIO_3_FUNC)
3232 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3233
3234 if (asserted & GPIO_4_FUNC)
3235 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3236
3237 if (port == 0) {
3238 if (asserted & ATTN_GENERAL_ATTN_1) {
3239 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3240 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3241 }
3242 if (asserted & ATTN_GENERAL_ATTN_2) {
3243 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3244 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3245 }
3246 if (asserted & ATTN_GENERAL_ATTN_3) {
3247 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3248 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3249 }
3250 } else {
3251 if (asserted & ATTN_GENERAL_ATTN_4) {
3252 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3253 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3254 }
3255 if (asserted & ATTN_GENERAL_ATTN_5) {
3256 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3257 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3258 }
3259 if (asserted & ATTN_GENERAL_ATTN_6) {
3260 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3262 }
3263 }
3264
3265 } /* if hardwired */
3266
3267 if (bp->common.int_block == INT_BLOCK_HC)
3268 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3269 COMMAND_REG_ATTN_BITS_SET);
3270 else
3271 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3272
3273 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3274 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3275 REG_WR(bp, reg_addr, asserted);
3276
3277 /* now set back the mask */
3278 if (asserted & ATTN_NIG_FOR_FUNC) {
3279 REG_WR(bp, nig_int_mask_addr, nig_mask);
3280 bnx2x_release_phy_lock(bp);
3281 }
3282 }
3283
3284 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3285 {
3286 int port = BP_PORT(bp);
3287 u32 ext_phy_config;
3288 /* mark the failure */
3289 ext_phy_config =
3290 SHMEM_RD(bp,
3291 dev_info.port_hw_config[port].external_phy_config);
3292
3293 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3294 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3295 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3296 ext_phy_config);
3297
3298 /* log the failure */
3299 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3300 " the driver to shutdown the card to prevent permanent"
3301 " damage. Please contact OEM Support for assistance\n");
3302 }
3303
3304 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3305 {
3306 int port = BP_PORT(bp);
3307 int reg_offset;
3308 u32 val;
3309
3310 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3311 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3312
3313 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3314
3315 val = REG_RD(bp, reg_offset);
3316 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3317 REG_WR(bp, reg_offset, val);
3318
3319 BNX2X_ERR("SPIO5 hw attention\n");
3320
3321 /* Fan failure attention */
3322 bnx2x_hw_reset_phy(&bp->link_params);
3323 bnx2x_fan_failure(bp);
3324 }
3325
3326 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3327 bnx2x_acquire_phy_lock(bp);
3328 bnx2x_handle_module_detect_int(&bp->link_params);
3329 bnx2x_release_phy_lock(bp);
3330 }
3331
3332 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3333
3334 val = REG_RD(bp, reg_offset);
3335 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3336 REG_WR(bp, reg_offset, val);
3337
3338 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3339 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3340 bnx2x_panic();
3341 }
3342 }
3343
3344 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3345 {
3346 u32 val;
3347
3348 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3349
3350 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3351 BNX2X_ERR("DB hw attention 0x%x\n", val);
3352 /* DORQ discard attention */
3353 if (val & 0x2)
3354 BNX2X_ERR("FATAL error from DORQ\n");
3355 }
3356
3357 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3358
3359 int port = BP_PORT(bp);
3360 int reg_offset;
3361
3362 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3363 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3364
3365 val = REG_RD(bp, reg_offset);
3366 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3367 REG_WR(bp, reg_offset, val);
3368
3369 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3370 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3371 bnx2x_panic();
3372 }
3373 }
3374
3375 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3376 {
3377 u32 val;
3378
3379 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3380
3381 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3382 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3383 /* CFC error attention */
3384 if (val & 0x2)
3385 BNX2X_ERR("FATAL error from CFC\n");
3386 }
3387
3388 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3389 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3390 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3391 /* RQ_USDMDP_FIFO_OVERFLOW */
3392 if (val & 0x18000)
3393 BNX2X_ERR("FATAL error from PXP\n");
3394
3395 if (!CHIP_IS_E1x(bp)) {
3396 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3397 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3398 }
3399 }
3400
3401 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3402
3403 int port = BP_PORT(bp);
3404 int reg_offset;
3405
3406 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3407 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3408
3409 val = REG_RD(bp, reg_offset);
3410 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3411 REG_WR(bp, reg_offset, val);
3412
3413 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3414 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3415 bnx2x_panic();
3416 }
3417 }
3418
3419 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3420 {
3421 u32 val;
3422
3423 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3424
3425 if (attn & BNX2X_PMF_LINK_ASSERT) {
3426 int func = BP_FUNC(bp);
3427
3428 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3429 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3430 func_mf_config[BP_ABS_FUNC(bp)].config);
3431 val = SHMEM_RD(bp,
3432 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3433 if (val & DRV_STATUS_DCC_EVENT_MASK)
3434 bnx2x_dcc_event(bp,
3435 (val & DRV_STATUS_DCC_EVENT_MASK));
3436
3437 if (val & DRV_STATUS_SET_MF_BW)
3438 bnx2x_set_mf_bw(bp);
3439
3440 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3441 bnx2x_pmf_update(bp);
3442
3443 if (bp->port.pmf &&
3444 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3445 bp->dcbx_enabled > 0)
3446 /* start dcbx state machine */
3447 bnx2x_dcbx_set_params(bp,
3448 BNX2X_DCBX_STATE_NEG_RECEIVED);
3449 if (bp->link_vars.periodic_flags &
3450 PERIODIC_FLAGS_LINK_EVENT) {
3451 /* sync with link */
3452 bnx2x_acquire_phy_lock(bp);
3453 bp->link_vars.periodic_flags &=
3454 ~PERIODIC_FLAGS_LINK_EVENT;
3455 bnx2x_release_phy_lock(bp);
3456 if (IS_MF(bp))
3457 bnx2x_link_sync_notify(bp);
3458 bnx2x_link_report(bp);
3459 }
3460 /* Always call it here: bnx2x_link_report() will
3461 * prevent the link indication duplication.
3462 */
3463 bnx2x__link_status_update(bp);
3464 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3465
3466 BNX2X_ERR("MC assert!\n");
3467 bnx2x_mc_assert(bp);
3468 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3470 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3472 bnx2x_panic();
3473
3474 } else if (attn & BNX2X_MCP_ASSERT) {
3475
3476 BNX2X_ERR("MCP assert!\n");
3477 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3478 bnx2x_fw_dump(bp);
3479
3480 } else
3481 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3482 }
3483
3484 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3485 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3486 if (attn & BNX2X_GRC_TIMEOUT) {
3487 val = CHIP_IS_E1(bp) ? 0 :
3488 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3489 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3490 }
3491 if (attn & BNX2X_GRC_RSV) {
3492 val = CHIP_IS_E1(bp) ? 0 :
3493 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3494 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3495 }
3496 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3497 }
3498 }
3499
3500 /*
3501 * Bits map:
3502 * 0-7 - Engine0 load counter.
3503 * 8-15 - Engine1 load counter.
3504 * 16 - Engine0 RESET_IN_PROGRESS bit.
3505 * 17 - Engine1 RESET_IN_PROGRESS bit.
3506 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3507 * on the engine
3508 * 19 - Engine1 ONE_IS_LOADED.
3509 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3510 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3511 * just the one belonging to its engine).
3512 *
3513 */
3514 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3515
3516 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3517 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3518 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3519 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3520 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3521 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3522 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3523
3524 /*
3525 * Set the GLOBAL_RESET bit.
3526 *
3527 * Should be run under rtnl lock
3528 */
3529 void bnx2x_set_reset_global(struct bnx2x *bp)
3530 {
3531 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3532
3533 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3534 barrier();
3535 mmiowb();
3536 }
3537
3538 /*
3539 * Clear the GLOBAL_RESET bit.
3540 *
3541 * Should be run under rtnl lock
3542 */
3543 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3544 {
3545 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3546
3547 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3548 barrier();
3549 mmiowb();
3550 }
3551
3552 /*
3553 * Checks the GLOBAL_RESET bit.
3554 *
3555 * should be run under rtnl lock
3556 */
3557 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3558 {
3559 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3560
3561 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3562 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3563 }
3564
3565 /*
3566 * Clear RESET_IN_PROGRESS bit for the current engine.
3567 *
3568 * Should be run under rtnl lock
3569 */
3570 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3571 {
3572 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3573 u32 bit = BP_PATH(bp) ?
3574 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3575
3576 /* Clear the bit */
3577 val &= ~bit;
3578 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3579 barrier();
3580 mmiowb();
3581 }
3582
3583 /*
3584 * Set RESET_IN_PROGRESS for the current engine.
3585 *
3586 * should be run under rtnl lock
3587 */
3588 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3589 {
3590 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3591 u32 bit = BP_PATH(bp) ?
3592 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3593
3594 /* Set the bit */
3595 val |= bit;
3596 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3597 barrier();
3598 mmiowb();
3599 }
3600
3601 /*
3602 * Checks the RESET_IN_PROGRESS bit for the given engine.
3603 * should be run under rtnl lock
3604 */
3605 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3606 {
3607 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3608 u32 bit = engine ?
3609 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3610
3611 /* return false if bit is set */
3612 return (val & bit) ? false : true;
3613 }
3614
3615 /*
3616 * Increment the load counter for the current engine.
3617 *
3618 * should be run under rtnl lock
3619 */
3620 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3621 {
3622 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3623 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3624 BNX2X_PATH0_LOAD_CNT_MASK;
3625 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3626 BNX2X_PATH0_LOAD_CNT_SHIFT;
3627
3628 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3629
3630 /* get the current counter value */
3631 val1 = (val & mask) >> shift;
3632
3633 /* increment... */
3634 val1++;
3635
3636 /* clear the old value */
3637 val &= ~mask;
3638
3639 /* set the new one */
3640 val |= ((val1 << shift) & mask);
3641
3642 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3643 barrier();
3644 mmiowb();
3645 }
3646
3647 /**
3648 * bnx2x_dec_load_cnt - decrement the load counter
3649 *
3650 * @bp: driver handle
3651 *
3652 * Should be run under rtnl lock.
3653 * Decrements the load counter for the current engine. Returns
3654 * the new counter value.
3655 */
3656 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3657 {
3658 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3659 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3660 BNX2X_PATH0_LOAD_CNT_MASK;
3661 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3662 BNX2X_PATH0_LOAD_CNT_SHIFT;
3663
3664 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3665
3666 /* get the current counter value */
3667 val1 = (val & mask) >> shift;
3668
3669 /* decrement... */
3670 val1--;
3671
3672 /* clear the old value */
3673 val &= ~mask;
3674
3675 /* set the new one */
3676 val |= ((val1 << shift) & mask);
3677
3678 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3679 barrier();
3680 mmiowb();
3681
3682 return val1;
3683 }
3684
3685 /*
3686 * Read the load counter for the current engine.
3687 *
3688 * should be run under rtnl lock
3689 */
3690 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3691 {
3692 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3693 BNX2X_PATH0_LOAD_CNT_MASK);
3694 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3695 BNX2X_PATH0_LOAD_CNT_SHIFT);
3696 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3697
3698 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3699
3700 val = (val & mask) >> shift;
3701
3702 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3703
3704 return val;
3705 }
3706
3707 /*
3708 * Reset the load counter for the current engine.
3709 *
3710 * should be run under rtnl lock
3711 */
3712 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3713 {
3714 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3715 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3716 BNX2X_PATH0_LOAD_CNT_MASK);
3717
3718 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3719 }
3720
3721 static inline void _print_next_block(int idx, const char *blk)
3722 {
3723 pr_cont("%s%s", idx ? ", " : "", blk);
3724 }
3725
3726 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3727 bool print)
3728 {
3729 int i = 0;
3730 u32 cur_bit = 0;
3731 for (i = 0; sig; i++) {
3732 cur_bit = ((u32)0x1 << i);
3733 if (sig & cur_bit) {
3734 switch (cur_bit) {
3735 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3736 if (print)
3737 _print_next_block(par_num++, "BRB");
3738 break;
3739 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3740 if (print)
3741 _print_next_block(par_num++, "PARSER");
3742 break;
3743 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3744 if (print)
3745 _print_next_block(par_num++, "TSDM");
3746 break;
3747 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3748 if (print)
3749 _print_next_block(par_num++,
3750 "SEARCHER");
3751 break;
3752 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3753 if (print)
3754 _print_next_block(par_num++, "TCM");
3755 break;
3756 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3757 if (print)
3758 _print_next_block(par_num++, "TSEMI");
3759 break;
3760 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3761 if (print)
3762 _print_next_block(par_num++, "XPB");
3763 break;
3764 }
3765
3766 /* Clear the bit */
3767 sig &= ~cur_bit;
3768 }
3769 }
3770
3771 return par_num;
3772 }
3773
3774 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3775 bool *global, bool print)
3776 {
3777 int i = 0;
3778 u32 cur_bit = 0;
3779 for (i = 0; sig; i++) {
3780 cur_bit = ((u32)0x1 << i);
3781 if (sig & cur_bit) {
3782 switch (cur_bit) {
3783 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3784 if (print)
3785 _print_next_block(par_num++, "PBF");
3786 break;
3787 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3788 if (print)
3789 _print_next_block(par_num++, "QM");
3790 break;
3791 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3792 if (print)
3793 _print_next_block(par_num++, "TM");
3794 break;
3795 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3796 if (print)
3797 _print_next_block(par_num++, "XSDM");
3798 break;
3799 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3800 if (print)
3801 _print_next_block(par_num++, "XCM");
3802 break;
3803 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3804 if (print)
3805 _print_next_block(par_num++, "XSEMI");
3806 break;
3807 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3808 if (print)
3809 _print_next_block(par_num++,
3810 "DOORBELLQ");
3811 break;
3812 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3813 if (print)
3814 _print_next_block(par_num++, "NIG");
3815 break;
3816 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3817 if (print)
3818 _print_next_block(par_num++,
3819 "VAUX PCI CORE");
3820 *global = true;
3821 break;
3822 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3823 if (print)
3824 _print_next_block(par_num++, "DEBUG");
3825 break;
3826 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3827 if (print)
3828 _print_next_block(par_num++, "USDM");
3829 break;
3830 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3831 if (print)
3832 _print_next_block(par_num++, "UCM");
3833 break;
3834 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3835 if (print)
3836 _print_next_block(par_num++, "USEMI");
3837 break;
3838 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3839 if (print)
3840 _print_next_block(par_num++, "UPB");
3841 break;
3842 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3843 if (print)
3844 _print_next_block(par_num++, "CSDM");
3845 break;
3846 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3847 if (print)
3848 _print_next_block(par_num++, "CCM");
3849 break;
3850 }
3851
3852 /* Clear the bit */
3853 sig &= ~cur_bit;
3854 }
3855 }
3856
3857 return par_num;
3858 }
3859
3860 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3861 bool print)
3862 {
3863 int i = 0;
3864 u32 cur_bit = 0;
3865 for (i = 0; sig; i++) {
3866 cur_bit = ((u32)0x1 << i);
3867 if (sig & cur_bit) {
3868 switch (cur_bit) {
3869 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3870 if (print)
3871 _print_next_block(par_num++, "CSEMI");
3872 break;
3873 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3874 if (print)
3875 _print_next_block(par_num++, "PXP");
3876 break;
3877 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3878 if (print)
3879 _print_next_block(par_num++,
3880 "PXPPCICLOCKCLIENT");
3881 break;
3882 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3883 if (print)
3884 _print_next_block(par_num++, "CFC");
3885 break;
3886 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3887 if (print)
3888 _print_next_block(par_num++, "CDU");
3889 break;
3890 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3891 if (print)
3892 _print_next_block(par_num++, "DMAE");
3893 break;
3894 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3895 if (print)
3896 _print_next_block(par_num++, "IGU");
3897 break;
3898 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3899 if (print)
3900 _print_next_block(par_num++, "MISC");
3901 break;
3902 }
3903
3904 /* Clear the bit */
3905 sig &= ~cur_bit;
3906 }
3907 }
3908
3909 return par_num;
3910 }
3911
3912 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3913 bool *global, bool print)
3914 {
3915 int i = 0;
3916 u32 cur_bit = 0;
3917 for (i = 0; sig; i++) {
3918 cur_bit = ((u32)0x1 << i);
3919 if (sig & cur_bit) {
3920 switch (cur_bit) {
3921 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3922 if (print)
3923 _print_next_block(par_num++, "MCP ROM");
3924 *global = true;
3925 break;
3926 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3927 if (print)
3928 _print_next_block(par_num++,
3929 "MCP UMP RX");
3930 *global = true;
3931 break;
3932 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3933 if (print)
3934 _print_next_block(par_num++,
3935 "MCP UMP TX");
3936 *global = true;
3937 break;
3938 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3939 if (print)
3940 _print_next_block(par_num++,
3941 "MCP SCPAD");
3942 *global = true;
3943 break;
3944 }
3945
3946 /* Clear the bit */
3947 sig &= ~cur_bit;
3948 }
3949 }
3950
3951 return par_num;
3952 }
3953
3954 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3955 bool print)
3956 {
3957 int i = 0;
3958 u32 cur_bit = 0;
3959 for (i = 0; sig; i++) {
3960 cur_bit = ((u32)0x1 << i);
3961 if (sig & cur_bit) {
3962 switch (cur_bit) {
3963 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3964 if (print)
3965 _print_next_block(par_num++, "PGLUE_B");
3966 break;
3967 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3968 if (print)
3969 _print_next_block(par_num++, "ATC");
3970 break;
3971 }
3972
3973 /* Clear the bit */
3974 sig &= ~cur_bit;
3975 }
3976 }
3977
3978 return par_num;
3979 }
3980
3981 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3982 u32 *sig)
3983 {
3984 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3985 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3986 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3987 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3988 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3989 int par_num = 0;
3990 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3991 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3992 "[4]:0x%08x\n",
3993 sig[0] & HW_PRTY_ASSERT_SET_0,
3994 sig[1] & HW_PRTY_ASSERT_SET_1,
3995 sig[2] & HW_PRTY_ASSERT_SET_2,
3996 sig[3] & HW_PRTY_ASSERT_SET_3,
3997 sig[4] & HW_PRTY_ASSERT_SET_4);
3998 if (print)
3999 netdev_err(bp->dev,
4000 "Parity errors detected in blocks: ");
4001 par_num = bnx2x_check_blocks_with_parity0(
4002 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4003 par_num = bnx2x_check_blocks_with_parity1(
4004 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4005 par_num = bnx2x_check_blocks_with_parity2(
4006 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4007 par_num = bnx2x_check_blocks_with_parity3(
4008 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4009 par_num = bnx2x_check_blocks_with_parity4(
4010 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4011
4012 if (print)
4013 pr_cont("\n");
4014
4015 return true;
4016 } else
4017 return false;
4018 }
4019
4020 /**
4021 * bnx2x_chk_parity_attn - checks for parity attentions.
4022 *
4023 * @bp: driver handle
4024 * @global: true if there was a global attention
4025 * @print: show parity attention in syslog
4026 */
4027 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4028 {
4029 struct attn_route attn = { {0} };
4030 int port = BP_PORT(bp);
4031
4032 attn.sig[0] = REG_RD(bp,
4033 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4034 port*4);
4035 attn.sig[1] = REG_RD(bp,
4036 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4037 port*4);
4038 attn.sig[2] = REG_RD(bp,
4039 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4040 port*4);
4041 attn.sig[3] = REG_RD(bp,
4042 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4043 port*4);
4044
4045 if (!CHIP_IS_E1x(bp))
4046 attn.sig[4] = REG_RD(bp,
4047 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4048 port*4);
4049
4050 return bnx2x_parity_attn(bp, global, print, attn.sig);
4051 }
4052
4053
4054 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4055 {
4056 u32 val;
4057 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4058
4059 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4060 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4061 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4062 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4063 "ADDRESS_ERROR\n");
4064 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4065 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4066 "INCORRECT_RCV_BEHAVIOR\n");
4067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4069 "WAS_ERROR_ATTN\n");
4070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4072 "VF_LENGTH_VIOLATION_ATTN\n");
4073 if (val &
4074 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4075 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4076 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4077 if (val &
4078 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4079 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4080 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4081 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4083 "TCPL_ERROR_ATTN\n");
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4086 "TCPL_IN_TWO_RCBS_ATTN\n");
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "CSSNOOP_FIFO_OVERFLOW\n");
4090 }
4091 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4092 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4093 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4094 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4095 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4096 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4097 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4098 "_ATC_TCPL_TO_NOT_PEND\n");
4099 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4100 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4101 "ATC_GPA_MULTIPLE_HITS\n");
4102 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4103 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4104 "ATC_RCPL_TO_EMPTY_CNT\n");
4105 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4107 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4108 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4109 "ATC_IREQ_LESS_THAN_STU\n");
4110 }
4111
4112 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4113 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4114 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4115 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4116 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4117 }
4118
4119 }
4120
4121 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4122 {
4123 struct attn_route attn, *group_mask;
4124 int port = BP_PORT(bp);
4125 int index;
4126 u32 reg_addr;
4127 u32 val;
4128 u32 aeu_mask;
4129 bool global = false;
4130
4131 /* need to take HW lock because MCP or other port might also
4132 try to handle this event */
4133 bnx2x_acquire_alr(bp);
4134
4135 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4136 #ifndef BNX2X_STOP_ON_ERROR
4137 bp->recovery_state = BNX2X_RECOVERY_INIT;
4138 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4139 /* Disable HW interrupts */
4140 bnx2x_int_disable(bp);
4141 /* In case of parity errors don't handle attentions so that
4142 * other function would "see" parity errors.
4143 */
4144 #else
4145 bnx2x_panic();
4146 #endif
4147 bnx2x_release_alr(bp);
4148 return;
4149 }
4150
4151 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4152 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4153 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4154 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4155 if (!CHIP_IS_E1x(bp))
4156 attn.sig[4] =
4157 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4158 else
4159 attn.sig[4] = 0;
4160
4161 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4162 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4163
4164 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4165 if (deasserted & (1 << index)) {
4166 group_mask = &bp->attn_group[index];
4167
4168 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4169 "%08x %08x %08x\n",
4170 index,
4171 group_mask->sig[0], group_mask->sig[1],
4172 group_mask->sig[2], group_mask->sig[3],
4173 group_mask->sig[4]);
4174
4175 bnx2x_attn_int_deasserted4(bp,
4176 attn.sig[4] & group_mask->sig[4]);
4177 bnx2x_attn_int_deasserted3(bp,
4178 attn.sig[3] & group_mask->sig[3]);
4179 bnx2x_attn_int_deasserted1(bp,
4180 attn.sig[1] & group_mask->sig[1]);
4181 bnx2x_attn_int_deasserted2(bp,
4182 attn.sig[2] & group_mask->sig[2]);
4183 bnx2x_attn_int_deasserted0(bp,
4184 attn.sig[0] & group_mask->sig[0]);
4185 }
4186 }
4187
4188 bnx2x_release_alr(bp);
4189
4190 if (bp->common.int_block == INT_BLOCK_HC)
4191 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4192 COMMAND_REG_ATTN_BITS_CLR);
4193 else
4194 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4195
4196 val = ~deasserted;
4197 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4198 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4199 REG_WR(bp, reg_addr, val);
4200
4201 if (~bp->attn_state & deasserted)
4202 BNX2X_ERR("IGU ERROR\n");
4203
4204 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4205 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4206
4207 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4208 aeu_mask = REG_RD(bp, reg_addr);
4209
4210 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4211 aeu_mask, deasserted);
4212 aeu_mask |= (deasserted & 0x3ff);
4213 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4214
4215 REG_WR(bp, reg_addr, aeu_mask);
4216 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4217
4218 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4219 bp->attn_state &= ~deasserted;
4220 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4221 }
4222
4223 static void bnx2x_attn_int(struct bnx2x *bp)
4224 {
4225 /* read local copy of bits */
4226 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4227 attn_bits);
4228 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4229 attn_bits_ack);
4230 u32 attn_state = bp->attn_state;
4231
4232 /* look for changed bits */
4233 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4234 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4235
4236 DP(NETIF_MSG_HW,
4237 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4238 attn_bits, attn_ack, asserted, deasserted);
4239
4240 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4241 BNX2X_ERR("BAD attention state\n");
4242
4243 /* handle bits that were raised */
4244 if (asserted)
4245 bnx2x_attn_int_asserted(bp, asserted);
4246
4247 if (deasserted)
4248 bnx2x_attn_int_deasserted(bp, deasserted);
4249 }
4250
4251 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4252 u16 index, u8 op, u8 update)
4253 {
4254 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4255
4256 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4257 igu_addr);
4258 }
4259
4260 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4261 {
4262 /* No memory barriers */
4263 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4264 mmiowb(); /* keep prod updates ordered */
4265 }
4266
4267 #ifdef BCM_CNIC
4268 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4269 union event_ring_elem *elem)
4270 {
4271 u8 err = elem->message.error;
4272
4273 if (!bp->cnic_eth_dev.starting_cid ||
4274 (cid < bp->cnic_eth_dev.starting_cid &&
4275 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4276 return 1;
4277
4278 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4279
4280 if (unlikely(err)) {
4281
4282 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4283 cid);
4284 bnx2x_panic_dump(bp);
4285 }
4286 bnx2x_cnic_cfc_comp(bp, cid, err);
4287 return 0;
4288 }
4289 #endif
4290
4291 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4292 {
4293 struct bnx2x_mcast_ramrod_params rparam;
4294 int rc;
4295
4296 memset(&rparam, 0, sizeof(rparam));
4297
4298 rparam.mcast_obj = &bp->mcast_obj;
4299
4300 netif_addr_lock_bh(bp->dev);
4301
4302 /* Clear pending state for the last command */
4303 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4304
4305 /* If there are pending mcast commands - send them */
4306 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4307 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4308 if (rc < 0)
4309 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4310 rc);
4311 }
4312
4313 netif_addr_unlock_bh(bp->dev);
4314 }
4315
4316 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4317 union event_ring_elem *elem)
4318 {
4319 unsigned long ramrod_flags = 0;
4320 int rc = 0;
4321 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4322 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4323
4324 /* Always push next commands out, don't wait here */
4325 __set_bit(RAMROD_CONT, &ramrod_flags);
4326
4327 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4328 case BNX2X_FILTER_MAC_PENDING:
4329 #ifdef BCM_CNIC
4330 if (cid == BNX2X_ISCSI_ETH_CID)
4331 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4332 else
4333 #endif
4334 vlan_mac_obj = &bp->fp[cid].mac_obj;
4335
4336 break;
4337 case BNX2X_FILTER_MCAST_PENDING:
4338 /* This is only relevant for 57710 where multicast MACs are
4339 * configured as unicast MACs using the same ramrod.
4340 */
4341 bnx2x_handle_mcast_eqe(bp);
4342 return;
4343 default:
4344 BNX2X_ERR("Unsupported classification command: %d\n",
4345 elem->message.data.eth_event.echo);
4346 return;
4347 }
4348
4349 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4350
4351 if (rc < 0)
4352 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4353 else if (rc > 0)
4354 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4355
4356 }
4357
4358 #ifdef BCM_CNIC
4359 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4360 #endif
4361
4362 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4363 {
4364 netif_addr_lock_bh(bp->dev);
4365
4366 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4367
4368 /* Send rx_mode command again if was requested */
4369 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4370 bnx2x_set_storm_rx_mode(bp);
4371 #ifdef BCM_CNIC
4372 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4373 &bp->sp_state))
4374 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4375 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4376 &bp->sp_state))
4377 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4378 #endif
4379
4380 netif_addr_unlock_bh(bp->dev);
4381 }
4382
4383 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4384 struct bnx2x *bp, u32 cid)
4385 {
4386 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4387 #ifdef BCM_CNIC
4388 if (cid == BNX2X_FCOE_ETH_CID)
4389 return &bnx2x_fcoe(bp, q_obj);
4390 else
4391 #endif
4392 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4393 }
4394
4395 static void bnx2x_eq_int(struct bnx2x *bp)
4396 {
4397 u16 hw_cons, sw_cons, sw_prod;
4398 union event_ring_elem *elem;
4399 u32 cid;
4400 u8 opcode;
4401 int spqe_cnt = 0;
4402 struct bnx2x_queue_sp_obj *q_obj;
4403 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4404 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4405
4406 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4407
4408 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4409 * when we get the the next-page we nned to adjust so the loop
4410 * condition below will be met. The next element is the size of a
4411 * regular element and hence incrementing by 1
4412 */
4413 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4414 hw_cons++;
4415
4416 /* This function may never run in parallel with itself for a
4417 * specific bp, thus there is no need in "paired" read memory
4418 * barrier here.
4419 */
4420 sw_cons = bp->eq_cons;
4421 sw_prod = bp->eq_prod;
4422
4423 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4424 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4425
4426 for (; sw_cons != hw_cons;
4427 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4428
4429
4430 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4431
4432 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4433 opcode = elem->message.opcode;
4434
4435
4436 /* handle eq element */
4437 switch (opcode) {
4438 case EVENT_RING_OPCODE_STAT_QUERY:
4439 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4440 bp->stats_comp++);
4441 /* nothing to do with stats comp */
4442 goto next_spqe;
4443
4444 case EVENT_RING_OPCODE_CFC_DEL:
4445 /* handle according to cid range */
4446 /*
4447 * we may want to verify here that the bp state is
4448 * HALTING
4449 */
4450 DP(BNX2X_MSG_SP,
4451 "got delete ramrod for MULTI[%d]\n", cid);
4452 #ifdef BCM_CNIC
4453 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4454 goto next_spqe;
4455 #endif
4456 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4457
4458 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4459 break;
4460
4461
4462
4463 goto next_spqe;
4464
4465 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4466 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4467 if (f_obj->complete_cmd(bp, f_obj,
4468 BNX2X_F_CMD_TX_STOP))
4469 break;
4470 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4471 goto next_spqe;
4472
4473 case EVENT_RING_OPCODE_START_TRAFFIC:
4474 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4475 if (f_obj->complete_cmd(bp, f_obj,
4476 BNX2X_F_CMD_TX_START))
4477 break;
4478 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4479 goto next_spqe;
4480 case EVENT_RING_OPCODE_FUNCTION_START:
4481 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4482 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4483 break;
4484
4485 goto next_spqe;
4486
4487 case EVENT_RING_OPCODE_FUNCTION_STOP:
4488 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4489 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4490 break;
4491
4492 goto next_spqe;
4493 }
4494
4495 switch (opcode | bp->state) {
4496 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4497 BNX2X_STATE_OPEN):
4498 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4499 BNX2X_STATE_OPENING_WAIT4_PORT):
4500 cid = elem->message.data.eth_event.echo &
4501 BNX2X_SWCID_MASK;
4502 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4503 cid);
4504 rss_raw->clear_pending(rss_raw);
4505 break;
4506
4507 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4508 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4509 case (EVENT_RING_OPCODE_SET_MAC |
4510 BNX2X_STATE_CLOSING_WAIT4_HALT):
4511 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4512 BNX2X_STATE_OPEN):
4513 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4514 BNX2X_STATE_DIAG):
4515 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4516 BNX2X_STATE_CLOSING_WAIT4_HALT):
4517 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4518 bnx2x_handle_classification_eqe(bp, elem);
4519 break;
4520
4521 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4522 BNX2X_STATE_OPEN):
4523 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4524 BNX2X_STATE_DIAG):
4525 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4526 BNX2X_STATE_CLOSING_WAIT4_HALT):
4527 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4528 bnx2x_handle_mcast_eqe(bp);
4529 break;
4530
4531 case (EVENT_RING_OPCODE_FILTERS_RULES |
4532 BNX2X_STATE_OPEN):
4533 case (EVENT_RING_OPCODE_FILTERS_RULES |
4534 BNX2X_STATE_DIAG):
4535 case (EVENT_RING_OPCODE_FILTERS_RULES |
4536 BNX2X_STATE_CLOSING_WAIT4_HALT):
4537 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4538 bnx2x_handle_rx_mode_eqe(bp);
4539 break;
4540 default:
4541 /* unknown event log error and continue */
4542 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4543 elem->message.opcode, bp->state);
4544 }
4545 next_spqe:
4546 spqe_cnt++;
4547 } /* for */
4548
4549 smp_mb__before_atomic_inc();
4550 atomic_add(spqe_cnt, &bp->eq_spq_left);
4551
4552 bp->eq_cons = sw_cons;
4553 bp->eq_prod = sw_prod;
4554 /* Make sure that above mem writes were issued towards the memory */
4555 smp_wmb();
4556
4557 /* update producer */
4558 bnx2x_update_eq_prod(bp, bp->eq_prod);
4559 }
4560
4561 static void bnx2x_sp_task(struct work_struct *work)
4562 {
4563 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4564 u16 status;
4565
4566 status = bnx2x_update_dsb_idx(bp);
4567 /* if (status == 0) */
4568 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4569
4570 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4571
4572 /* HW attentions */
4573 if (status & BNX2X_DEF_SB_ATT_IDX) {
4574 bnx2x_attn_int(bp);
4575 status &= ~BNX2X_DEF_SB_ATT_IDX;
4576 }
4577
4578 /* SP events: STAT_QUERY and others */
4579 if (status & BNX2X_DEF_SB_IDX) {
4580 #ifdef BCM_CNIC
4581 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4582
4583 if ((!NO_FCOE(bp)) &&
4584 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4585 /*
4586 * Prevent local bottom-halves from running as
4587 * we are going to change the local NAPI list.
4588 */
4589 local_bh_disable();
4590 napi_schedule(&bnx2x_fcoe(bp, napi));
4591 local_bh_enable();
4592 }
4593 #endif
4594 /* Handle EQ completions */
4595 bnx2x_eq_int(bp);
4596
4597 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4598 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4599
4600 status &= ~BNX2X_DEF_SB_IDX;
4601 }
4602
4603 if (unlikely(status))
4604 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4605 status);
4606
4607 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4608 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4609 }
4610
4611 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4612 {
4613 struct net_device *dev = dev_instance;
4614 struct bnx2x *bp = netdev_priv(dev);
4615
4616 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4617 IGU_INT_DISABLE, 0);
4618
4619 #ifdef BNX2X_STOP_ON_ERROR
4620 if (unlikely(bp->panic))
4621 return IRQ_HANDLED;
4622 #endif
4623
4624 #ifdef BCM_CNIC
4625 {
4626 struct cnic_ops *c_ops;
4627
4628 rcu_read_lock();
4629 c_ops = rcu_dereference(bp->cnic_ops);
4630 if (c_ops)
4631 c_ops->cnic_handler(bp->cnic_data, NULL);
4632 rcu_read_unlock();
4633 }
4634 #endif
4635 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4636
4637 return IRQ_HANDLED;
4638 }
4639
4640 /* end of slow path */
4641
4642
4643 void bnx2x_drv_pulse(struct bnx2x *bp)
4644 {
4645 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4646 bp->fw_drv_pulse_wr_seq);
4647 }
4648
4649
4650 static void bnx2x_timer(unsigned long data)
4651 {
4652 u8 cos;
4653 struct bnx2x *bp = (struct bnx2x *) data;
4654
4655 if (!netif_running(bp->dev))
4656 return;
4657
4658 if (poll) {
4659 struct bnx2x_fastpath *fp = &bp->fp[0];
4660
4661 for_each_cos_in_tx_queue(fp, cos)
4662 bnx2x_tx_int(bp, &fp->txdata[cos]);
4663 bnx2x_rx_int(fp, 1000);
4664 }
4665
4666 if (!BP_NOMCP(bp)) {
4667 int mb_idx = BP_FW_MB_IDX(bp);
4668 u32 drv_pulse;
4669 u32 mcp_pulse;
4670
4671 ++bp->fw_drv_pulse_wr_seq;
4672 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4673 /* TBD - add SYSTEM_TIME */
4674 drv_pulse = bp->fw_drv_pulse_wr_seq;
4675 bnx2x_drv_pulse(bp);
4676
4677 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4678 MCP_PULSE_SEQ_MASK);
4679 /* The delta between driver pulse and mcp response
4680 * should be 1 (before mcp response) or 0 (after mcp response)
4681 */
4682 if ((drv_pulse != mcp_pulse) &&
4683 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4684 /* someone lost a heartbeat... */
4685 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4686 drv_pulse, mcp_pulse);
4687 }
4688 }
4689
4690 if (bp->state == BNX2X_STATE_OPEN)
4691 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4692
4693 mod_timer(&bp->timer, jiffies + bp->current_interval);
4694 }
4695
4696 /* end of Statistics */
4697
4698 /* nic init */
4699
4700 /*
4701 * nic init service functions
4702 */
4703
4704 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4705 {
4706 u32 i;
4707 if (!(len%4) && !(addr%4))
4708 for (i = 0; i < len; i += 4)
4709 REG_WR(bp, addr + i, fill);
4710 else
4711 for (i = 0; i < len; i++)
4712 REG_WR8(bp, addr + i, fill);
4713
4714 }
4715
4716 /* helper: writes FP SP data to FW - data_size in dwords */
4717 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4718 int fw_sb_id,
4719 u32 *sb_data_p,
4720 u32 data_size)
4721 {
4722 int index;
4723 for (index = 0; index < data_size; index++)
4724 REG_WR(bp, BAR_CSTRORM_INTMEM +
4725 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4726 sizeof(u32)*index,
4727 *(sb_data_p + index));
4728 }
4729
4730 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4731 {
4732 u32 *sb_data_p;
4733 u32 data_size = 0;
4734 struct hc_status_block_data_e2 sb_data_e2;
4735 struct hc_status_block_data_e1x sb_data_e1x;
4736
4737 /* disable the function first */
4738 if (!CHIP_IS_E1x(bp)) {
4739 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4740 sb_data_e2.common.state = SB_DISABLED;
4741 sb_data_e2.common.p_func.vf_valid = false;
4742 sb_data_p = (u32 *)&sb_data_e2;
4743 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4744 } else {
4745 memset(&sb_data_e1x, 0,
4746 sizeof(struct hc_status_block_data_e1x));
4747 sb_data_e1x.common.state = SB_DISABLED;
4748 sb_data_e1x.common.p_func.vf_valid = false;
4749 sb_data_p = (u32 *)&sb_data_e1x;
4750 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4751 }
4752 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4753
4754 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4755 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4756 CSTORM_STATUS_BLOCK_SIZE);
4757 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4758 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4759 CSTORM_SYNC_BLOCK_SIZE);
4760 }
4761
4762 /* helper: writes SP SB data to FW */
4763 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4764 struct hc_sp_status_block_data *sp_sb_data)
4765 {
4766 int func = BP_FUNC(bp);
4767 int i;
4768 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4769 REG_WR(bp, BAR_CSTRORM_INTMEM +
4770 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4771 i*sizeof(u32),
4772 *((u32 *)sp_sb_data + i));
4773 }
4774
4775 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4776 {
4777 int func = BP_FUNC(bp);
4778 struct hc_sp_status_block_data sp_sb_data;
4779 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4780
4781 sp_sb_data.state = SB_DISABLED;
4782 sp_sb_data.p_func.vf_valid = false;
4783
4784 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4785
4786 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4787 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4788 CSTORM_SP_STATUS_BLOCK_SIZE);
4789 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4790 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4791 CSTORM_SP_SYNC_BLOCK_SIZE);
4792
4793 }
4794
4795
4796 static inline
4797 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4798 int igu_sb_id, int igu_seg_id)
4799 {
4800 hc_sm->igu_sb_id = igu_sb_id;
4801 hc_sm->igu_seg_id = igu_seg_id;
4802 hc_sm->timer_value = 0xFF;
4803 hc_sm->time_to_expire = 0xFFFFFFFF;
4804 }
4805
4806
4807 /* allocates state machine ids. */
4808 static inline
4809 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4810 {
4811 /* zero out state machine indices */
4812 /* rx indices */
4813 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4814
4815 /* tx indices */
4816 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4817 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4818 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4819 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4820
4821 /* map indices */
4822 /* rx indices */
4823 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4824 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4825
4826 /* tx indices */
4827 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4828 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4829 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4830 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4831 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4832 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4833 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4834 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4835 }
4836
4837 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4838 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4839 {
4840 int igu_seg_id;
4841
4842 struct hc_status_block_data_e2 sb_data_e2;
4843 struct hc_status_block_data_e1x sb_data_e1x;
4844 struct hc_status_block_sm *hc_sm_p;
4845 int data_size;
4846 u32 *sb_data_p;
4847
4848 if (CHIP_INT_MODE_IS_BC(bp))
4849 igu_seg_id = HC_SEG_ACCESS_NORM;
4850 else
4851 igu_seg_id = IGU_SEG_ACCESS_NORM;
4852
4853 bnx2x_zero_fp_sb(bp, fw_sb_id);
4854
4855 if (!CHIP_IS_E1x(bp)) {
4856 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4857 sb_data_e2.common.state = SB_ENABLED;
4858 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4859 sb_data_e2.common.p_func.vf_id = vfid;
4860 sb_data_e2.common.p_func.vf_valid = vf_valid;
4861 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4862 sb_data_e2.common.same_igu_sb_1b = true;
4863 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4864 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4865 hc_sm_p = sb_data_e2.common.state_machine;
4866 sb_data_p = (u32 *)&sb_data_e2;
4867 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4868 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4869 } else {
4870 memset(&sb_data_e1x, 0,
4871 sizeof(struct hc_status_block_data_e1x));
4872 sb_data_e1x.common.state = SB_ENABLED;
4873 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4874 sb_data_e1x.common.p_func.vf_id = 0xff;
4875 sb_data_e1x.common.p_func.vf_valid = false;
4876 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4877 sb_data_e1x.common.same_igu_sb_1b = true;
4878 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4879 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4880 hc_sm_p = sb_data_e1x.common.state_machine;
4881 sb_data_p = (u32 *)&sb_data_e1x;
4882 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4883 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4884 }
4885
4886 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4887 igu_sb_id, igu_seg_id);
4888 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4889 igu_sb_id, igu_seg_id);
4890
4891 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4892
4893 /* write indecies to HW */
4894 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4895 }
4896
4897 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4898 u16 tx_usec, u16 rx_usec)
4899 {
4900 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4901 false, rx_usec);
4902 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4903 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4904 tx_usec);
4905 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4906 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4907 tx_usec);
4908 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4909 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4910 tx_usec);
4911 }
4912
4913 static void bnx2x_init_def_sb(struct bnx2x *bp)
4914 {
4915 struct host_sp_status_block *def_sb = bp->def_status_blk;
4916 dma_addr_t mapping = bp->def_status_blk_mapping;
4917 int igu_sp_sb_index;
4918 int igu_seg_id;
4919 int port = BP_PORT(bp);
4920 int func = BP_FUNC(bp);
4921 int reg_offset, reg_offset_en5;
4922 u64 section;
4923 int index;
4924 struct hc_sp_status_block_data sp_sb_data;
4925 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4926
4927 if (CHIP_INT_MODE_IS_BC(bp)) {
4928 igu_sp_sb_index = DEF_SB_IGU_ID;
4929 igu_seg_id = HC_SEG_ACCESS_DEF;
4930 } else {
4931 igu_sp_sb_index = bp->igu_dsb_id;
4932 igu_seg_id = IGU_SEG_ACCESS_DEF;
4933 }
4934
4935 /* ATTN */
4936 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4937 atten_status_block);
4938 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4939
4940 bp->attn_state = 0;
4941
4942 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4943 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4944 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
4945 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
4946 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4947 int sindex;
4948 /* take care of sig[0]..sig[4] */
4949 for (sindex = 0; sindex < 4; sindex++)
4950 bp->attn_group[index].sig[sindex] =
4951 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4952
4953 if (!CHIP_IS_E1x(bp))
4954 /*
4955 * enable5 is separate from the rest of the registers,
4956 * and therefore the address skip is 4
4957 * and not 16 between the different groups
4958 */
4959 bp->attn_group[index].sig[4] = REG_RD(bp,
4960 reg_offset_en5 + 0x4*index);
4961 else
4962 bp->attn_group[index].sig[4] = 0;
4963 }
4964
4965 if (bp->common.int_block == INT_BLOCK_HC) {
4966 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4967 HC_REG_ATTN_MSG0_ADDR_L);
4968
4969 REG_WR(bp, reg_offset, U64_LO(section));
4970 REG_WR(bp, reg_offset + 4, U64_HI(section));
4971 } else if (!CHIP_IS_E1x(bp)) {
4972 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4973 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4974 }
4975
4976 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4977 sp_sb);
4978
4979 bnx2x_zero_sp_sb(bp);
4980
4981 sp_sb_data.state = SB_ENABLED;
4982 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4983 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4984 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4985 sp_sb_data.igu_seg_id = igu_seg_id;
4986 sp_sb_data.p_func.pf_id = func;
4987 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4988 sp_sb_data.p_func.vf_id = 0xff;
4989
4990 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4991
4992 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4993 }
4994
4995 void bnx2x_update_coalesce(struct bnx2x *bp)
4996 {
4997 int i;
4998
4999 for_each_eth_queue(bp, i)
5000 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5001 bp->tx_ticks, bp->rx_ticks);
5002 }
5003
5004 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5005 {
5006 spin_lock_init(&bp->spq_lock);
5007 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5008
5009 bp->spq_prod_idx = 0;
5010 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5011 bp->spq_prod_bd = bp->spq;
5012 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5013 }
5014
5015 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5016 {
5017 int i;
5018 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5019 union event_ring_elem *elem =
5020 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5021
5022 elem->next_page.addr.hi =
5023 cpu_to_le32(U64_HI(bp->eq_mapping +
5024 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5025 elem->next_page.addr.lo =
5026 cpu_to_le32(U64_LO(bp->eq_mapping +
5027 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5028 }
5029 bp->eq_cons = 0;
5030 bp->eq_prod = NUM_EQ_DESC;
5031 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5032 /* we want a warning message before it gets rought... */
5033 atomic_set(&bp->eq_spq_left,
5034 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5035 }
5036
5037
5038 /* called with netif_addr_lock_bh() */
5039 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5040 unsigned long rx_mode_flags,
5041 unsigned long rx_accept_flags,
5042 unsigned long tx_accept_flags,
5043 unsigned long ramrod_flags)
5044 {
5045 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5046 int rc;
5047
5048 memset(&ramrod_param, 0, sizeof(ramrod_param));
5049
5050 /* Prepare ramrod parameters */
5051 ramrod_param.cid = 0;
5052 ramrod_param.cl_id = cl_id;
5053 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5054 ramrod_param.func_id = BP_FUNC(bp);
5055
5056 ramrod_param.pstate = &bp->sp_state;
5057 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5058
5059 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5060 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5061
5062 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5063
5064 ramrod_param.ramrod_flags = ramrod_flags;
5065 ramrod_param.rx_mode_flags = rx_mode_flags;
5066
5067 ramrod_param.rx_accept_flags = rx_accept_flags;
5068 ramrod_param.tx_accept_flags = tx_accept_flags;
5069
5070 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5071 if (rc < 0) {
5072 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5073 return;
5074 }
5075 }
5076
5077 /* called with netif_addr_lock_bh() */
5078 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5079 {
5080 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5081 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5082
5083 #ifdef BCM_CNIC
5084 if (!NO_FCOE(bp))
5085
5086 /* Configure rx_mode of FCoE Queue */
5087 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5088 #endif
5089
5090 switch (bp->rx_mode) {
5091 case BNX2X_RX_MODE_NONE:
5092 /*
5093 * 'drop all' supersedes any accept flags that may have been
5094 * passed to the function.
5095 */
5096 break;
5097 case BNX2X_RX_MODE_NORMAL:
5098 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5099 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5100 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5101
5102 /* internal switching mode */
5103 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5104 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5105 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5106
5107 break;
5108 case BNX2X_RX_MODE_ALLMULTI:
5109 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5110 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5111 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5112
5113 /* internal switching mode */
5114 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5115 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5117
5118 break;
5119 case BNX2X_RX_MODE_PROMISC:
5120 /* According to deffinition of SI mode, iface in promisc mode
5121 * should receive matched and unmatched (in resolution of port)
5122 * unicast packets.
5123 */
5124 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5125 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5126 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5127 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5128
5129 /* internal switching mode */
5130 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5131 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5132
5133 if (IS_MF_SI(bp))
5134 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5135 else
5136 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5137
5138 break;
5139 default:
5140 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5141 return;
5142 }
5143
5144 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5145 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5146 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5147 }
5148
5149 __set_bit(RAMROD_RX, &ramrod_flags);
5150 __set_bit(RAMROD_TX, &ramrod_flags);
5151
5152 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5153 tx_accept_flags, ramrod_flags);
5154 }
5155
5156 static void bnx2x_init_internal_common(struct bnx2x *bp)
5157 {
5158 int i;
5159
5160 if (IS_MF_SI(bp))
5161 /*
5162 * In switch independent mode, the TSTORM needs to accept
5163 * packets that failed classification, since approximate match
5164 * mac addresses aren't written to NIG LLH
5165 */
5166 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5167 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5168 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5169 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5170 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5171
5172 /* Zero this manually as its initialization is
5173 currently missing in the initTool */
5174 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5175 REG_WR(bp, BAR_USTRORM_INTMEM +
5176 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5177 if (!CHIP_IS_E1x(bp)) {
5178 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5179 CHIP_INT_MODE_IS_BC(bp) ?
5180 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5181 }
5182 }
5183
5184 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5185 {
5186 switch (load_code) {
5187 case FW_MSG_CODE_DRV_LOAD_COMMON:
5188 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5189 bnx2x_init_internal_common(bp);
5190 /* no break */
5191
5192 case FW_MSG_CODE_DRV_LOAD_PORT:
5193 /* nothing to do */
5194 /* no break */
5195
5196 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5197 /* internal memory per function is
5198 initialized inside bnx2x_pf_init */
5199 break;
5200
5201 default:
5202 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5203 break;
5204 }
5205 }
5206
5207 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5208 {
5209 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5210 }
5211
5212 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5213 {
5214 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5215 }
5216
5217 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5218 {
5219 if (CHIP_IS_E1x(fp->bp))
5220 return BP_L_ID(fp->bp) + fp->index;
5221 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5222 return bnx2x_fp_igu_sb_id(fp);
5223 }
5224
5225 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5226 {
5227 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5228 u8 cos;
5229 unsigned long q_type = 0;
5230 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5231 fp->rx_queue = fp_idx;
5232 fp->cid = fp_idx;
5233 fp->cl_id = bnx2x_fp_cl_id(fp);
5234 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5235 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5236 /* qZone id equals to FW (per path) client id */
5237 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5238
5239 /* init shortcut */
5240 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5241 /* Setup SB indicies */
5242 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5243
5244 /* Configure Queue State object */
5245 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5246 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5247
5248 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5249
5250 /* init tx data */
5251 for_each_cos_in_tx_queue(fp, cos) {
5252 bnx2x_init_txdata(bp, &fp->txdata[cos],
5253 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5254 FP_COS_TO_TXQ(fp, cos),
5255 BNX2X_TX_SB_INDEX_BASE + cos);
5256 cids[cos] = fp->txdata[cos].cid;
5257 }
5258
5259 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5260 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5261 bnx2x_sp_mapping(bp, q_rdata), q_type);
5262
5263 /**
5264 * Configure classification DBs: Always enable Tx switching
5265 */
5266 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5267
5268 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5269 "cl_id %d fw_sb %d igu_sb %d\n",
5270 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5271 fp->igu_sb_id);
5272 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5273 fp->fw_sb_id, fp->igu_sb_id);
5274
5275 bnx2x_update_fpsb_idx(fp);
5276 }
5277
5278 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5279 {
5280 int i;
5281
5282 for_each_eth_queue(bp, i)
5283 bnx2x_init_eth_fp(bp, i);
5284 #ifdef BCM_CNIC
5285 if (!NO_FCOE(bp))
5286 bnx2x_init_fcoe_fp(bp);
5287
5288 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5289 BNX2X_VF_ID_INVALID, false,
5290 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5291
5292 #endif
5293
5294 /* Initialize MOD_ABS interrupts */
5295 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5296 bp->common.shmem_base, bp->common.shmem2_base,
5297 BP_PORT(bp));
5298 /* ensure status block indices were read */
5299 rmb();
5300
5301 bnx2x_init_def_sb(bp);
5302 bnx2x_update_dsb_idx(bp);
5303 bnx2x_init_rx_rings(bp);
5304 bnx2x_init_tx_rings(bp);
5305 bnx2x_init_sp_ring(bp);
5306 bnx2x_init_eq_ring(bp);
5307 bnx2x_init_internal(bp, load_code);
5308 bnx2x_pf_init(bp);
5309 bnx2x_stats_init(bp);
5310
5311 /* flush all before enabling interrupts */
5312 mb();
5313 mmiowb();
5314
5315 bnx2x_int_enable(bp);
5316
5317 /* Check for SPIO5 */
5318 bnx2x_attn_int_deasserted0(bp,
5319 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5320 AEU_INPUTS_ATTN_BITS_SPIO5);
5321 }
5322
5323 /* end of nic init */
5324
5325 /*
5326 * gzip service functions
5327 */
5328
5329 static int bnx2x_gunzip_init(struct bnx2x *bp)
5330 {
5331 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5332 &bp->gunzip_mapping, GFP_KERNEL);
5333 if (bp->gunzip_buf == NULL)
5334 goto gunzip_nomem1;
5335
5336 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5337 if (bp->strm == NULL)
5338 goto gunzip_nomem2;
5339
5340 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5341 if (bp->strm->workspace == NULL)
5342 goto gunzip_nomem3;
5343
5344 return 0;
5345
5346 gunzip_nomem3:
5347 kfree(bp->strm);
5348 bp->strm = NULL;
5349
5350 gunzip_nomem2:
5351 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5352 bp->gunzip_mapping);
5353 bp->gunzip_buf = NULL;
5354
5355 gunzip_nomem1:
5356 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5357 " un-compression\n");
5358 return -ENOMEM;
5359 }
5360
5361 static void bnx2x_gunzip_end(struct bnx2x *bp)
5362 {
5363 if (bp->strm) {
5364 vfree(bp->strm->workspace);
5365 kfree(bp->strm);
5366 bp->strm = NULL;
5367 }
5368
5369 if (bp->gunzip_buf) {
5370 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5371 bp->gunzip_mapping);
5372 bp->gunzip_buf = NULL;
5373 }
5374 }
5375
5376 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5377 {
5378 int n, rc;
5379
5380 /* check gzip header */
5381 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5382 BNX2X_ERR("Bad gzip header\n");
5383 return -EINVAL;
5384 }
5385
5386 n = 10;
5387
5388 #define FNAME 0x8
5389
5390 if (zbuf[3] & FNAME)
5391 while ((zbuf[n++] != 0) && (n < len));
5392
5393 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5394 bp->strm->avail_in = len - n;
5395 bp->strm->next_out = bp->gunzip_buf;
5396 bp->strm->avail_out = FW_BUF_SIZE;
5397
5398 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5399 if (rc != Z_OK)
5400 return rc;
5401
5402 rc = zlib_inflate(bp->strm, Z_FINISH);
5403 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5404 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5405 bp->strm->msg);
5406
5407 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5408 if (bp->gunzip_outlen & 0x3)
5409 netdev_err(bp->dev, "Firmware decompression error:"
5410 " gunzip_outlen (%d) not aligned\n",
5411 bp->gunzip_outlen);
5412 bp->gunzip_outlen >>= 2;
5413
5414 zlib_inflateEnd(bp->strm);
5415
5416 if (rc == Z_STREAM_END)
5417 return 0;
5418
5419 return rc;
5420 }
5421
5422 /* nic load/unload */
5423
5424 /*
5425 * General service functions
5426 */
5427
5428 /* send a NIG loopback debug packet */
5429 static void bnx2x_lb_pckt(struct bnx2x *bp)
5430 {
5431 u32 wb_write[3];
5432
5433 /* Ethernet source and destination addresses */
5434 wb_write[0] = 0x55555555;
5435 wb_write[1] = 0x55555555;
5436 wb_write[2] = 0x20; /* SOP */
5437 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5438
5439 /* NON-IP protocol */
5440 wb_write[0] = 0x09000000;
5441 wb_write[1] = 0x55555555;
5442 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5443 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5444 }
5445
5446 /* some of the internal memories
5447 * are not directly readable from the driver
5448 * to test them we send debug packets
5449 */
5450 static int bnx2x_int_mem_test(struct bnx2x *bp)
5451 {
5452 int factor;
5453 int count, i;
5454 u32 val = 0;
5455
5456 if (CHIP_REV_IS_FPGA(bp))
5457 factor = 120;
5458 else if (CHIP_REV_IS_EMUL(bp))
5459 factor = 200;
5460 else
5461 factor = 1;
5462
5463 /* Disable inputs of parser neighbor blocks */
5464 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5465 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5466 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5467 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5468
5469 /* Write 0 to parser credits for CFC search request */
5470 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5471
5472 /* send Ethernet packet */
5473 bnx2x_lb_pckt(bp);
5474
5475 /* TODO do i reset NIG statistic? */
5476 /* Wait until NIG register shows 1 packet of size 0x10 */
5477 count = 1000 * factor;
5478 while (count) {
5479
5480 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5481 val = *bnx2x_sp(bp, wb_data[0]);
5482 if (val == 0x10)
5483 break;
5484
5485 msleep(10);
5486 count--;
5487 }
5488 if (val != 0x10) {
5489 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5490 return -1;
5491 }
5492
5493 /* Wait until PRS register shows 1 packet */
5494 count = 1000 * factor;
5495 while (count) {
5496 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5497 if (val == 1)
5498 break;
5499
5500 msleep(10);
5501 count--;
5502 }
5503 if (val != 0x1) {
5504 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5505 return -2;
5506 }
5507
5508 /* Reset and init BRB, PRS */
5509 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5510 msleep(50);
5511 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5512 msleep(50);
5513 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5514 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5515
5516 DP(NETIF_MSG_HW, "part2\n");
5517
5518 /* Disable inputs of parser neighbor blocks */
5519 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5520 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5521 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5522 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5523
5524 /* Write 0 to parser credits for CFC search request */
5525 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5526
5527 /* send 10 Ethernet packets */
5528 for (i = 0; i < 10; i++)
5529 bnx2x_lb_pckt(bp);
5530
5531 /* Wait until NIG register shows 10 + 1
5532 packets of size 11*0x10 = 0xb0 */
5533 count = 1000 * factor;
5534 while (count) {
5535
5536 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5537 val = *bnx2x_sp(bp, wb_data[0]);
5538 if (val == 0xb0)
5539 break;
5540
5541 msleep(10);
5542 count--;
5543 }
5544 if (val != 0xb0) {
5545 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5546 return -3;
5547 }
5548
5549 /* Wait until PRS register shows 2 packets */
5550 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5551 if (val != 2)
5552 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5553
5554 /* Write 1 to parser credits for CFC search request */
5555 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5556
5557 /* Wait until PRS register shows 3 packets */
5558 msleep(10 * factor);
5559 /* Wait until NIG register shows 1 packet of size 0x10 */
5560 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5561 if (val != 3)
5562 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5563
5564 /* clear NIG EOP FIFO */
5565 for (i = 0; i < 11; i++)
5566 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5567 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5568 if (val != 1) {
5569 BNX2X_ERR("clear of NIG failed\n");
5570 return -4;
5571 }
5572
5573 /* Reset and init BRB, PRS, NIG */
5574 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5575 msleep(50);
5576 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5577 msleep(50);
5578 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5579 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5580 #ifndef BCM_CNIC
5581 /* set NIC mode */
5582 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5583 #endif
5584
5585 /* Enable inputs of parser neighbor blocks */
5586 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5587 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5588 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5589 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5590
5591 DP(NETIF_MSG_HW, "done\n");
5592
5593 return 0; /* OK */
5594 }
5595
5596 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5597 {
5598 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5599 if (!CHIP_IS_E1x(bp))
5600 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5601 else
5602 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5603 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5604 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5605 /*
5606 * mask read length error interrupts in brb for parser
5607 * (parsing unit and 'checksum and crc' unit)
5608 * these errors are legal (PU reads fixed length and CAC can cause
5609 * read length error on truncated packets)
5610 */
5611 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5612 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5613 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5614 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5615 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5616 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5617 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5618 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5619 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5620 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5621 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5622 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5623 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5624 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5625 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5626 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5627 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5628 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5629 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5630
5631 if (CHIP_REV_IS_FPGA(bp))
5632 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5633 else if (!CHIP_IS_E1x(bp))
5634 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5635 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5636 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5637 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5638 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5639 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5640 else
5641 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5642 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5643 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5644 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5645 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5646
5647 if (!CHIP_IS_E1x(bp))
5648 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5649 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5650
5651 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5652 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5653 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5654 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5655 }
5656
5657 static void bnx2x_reset_common(struct bnx2x *bp)
5658 {
5659 u32 val = 0x1400;
5660
5661 /* reset_common */
5662 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5663 0xd3ffff7f);
5664
5665 if (CHIP_IS_E3(bp)) {
5666 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5667 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5668 }
5669
5670 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5671 }
5672
5673 static void bnx2x_setup_dmae(struct bnx2x *bp)
5674 {
5675 bp->dmae_ready = 0;
5676 spin_lock_init(&bp->dmae_lock);
5677 }
5678
5679 static void bnx2x_init_pxp(struct bnx2x *bp)
5680 {
5681 u16 devctl;
5682 int r_order, w_order;
5683
5684 pci_read_config_word(bp->pdev,
5685 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5686 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5687 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5688 if (bp->mrrs == -1)
5689 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5690 else {
5691 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5692 r_order = bp->mrrs;
5693 }
5694
5695 bnx2x_init_pxp_arb(bp, r_order, w_order);
5696 }
5697
5698 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5699 {
5700 int is_required;
5701 u32 val;
5702 int port;
5703
5704 if (BP_NOMCP(bp))
5705 return;
5706
5707 is_required = 0;
5708 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5709 SHARED_HW_CFG_FAN_FAILURE_MASK;
5710
5711 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5712 is_required = 1;
5713
5714 /*
5715 * The fan failure mechanism is usually related to the PHY type since
5716 * the power consumption of the board is affected by the PHY. Currently,
5717 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5718 */
5719 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5720 for (port = PORT_0; port < PORT_MAX; port++) {
5721 is_required |=
5722 bnx2x_fan_failure_det_req(
5723 bp,
5724 bp->common.shmem_base,
5725 bp->common.shmem2_base,
5726 port);
5727 }
5728
5729 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5730
5731 if (is_required == 0)
5732 return;
5733
5734 /* Fan failure is indicated by SPIO 5 */
5735 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5736 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5737
5738 /* set to active low mode */
5739 val = REG_RD(bp, MISC_REG_SPIO_INT);
5740 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5741 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5742 REG_WR(bp, MISC_REG_SPIO_INT, val);
5743
5744 /* enable interrupt to signal the IGU */
5745 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5746 val |= (1 << MISC_REGISTERS_SPIO_5);
5747 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5748 }
5749
5750 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5751 {
5752 u32 offset = 0;
5753
5754 if (CHIP_IS_E1(bp))
5755 return;
5756 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5757 return;
5758
5759 switch (BP_ABS_FUNC(bp)) {
5760 case 0:
5761 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5762 break;
5763 case 1:
5764 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5765 break;
5766 case 2:
5767 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5768 break;
5769 case 3:
5770 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5771 break;
5772 case 4:
5773 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5774 break;
5775 case 5:
5776 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5777 break;
5778 case 6:
5779 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5780 break;
5781 case 7:
5782 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5783 break;
5784 default:
5785 return;
5786 }
5787
5788 REG_WR(bp, offset, pretend_func_num);
5789 REG_RD(bp, offset);
5790 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5791 }
5792
5793 void bnx2x_pf_disable(struct bnx2x *bp)
5794 {
5795 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5796 val &= ~IGU_PF_CONF_FUNC_EN;
5797
5798 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5799 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5800 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5801 }
5802
5803 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5804 {
5805 u32 shmem_base[2], shmem2_base[2];
5806 shmem_base[0] = bp->common.shmem_base;
5807 shmem2_base[0] = bp->common.shmem2_base;
5808 if (!CHIP_IS_E1x(bp)) {
5809 shmem_base[1] =
5810 SHMEM2_RD(bp, other_shmem_base_addr);
5811 shmem2_base[1] =
5812 SHMEM2_RD(bp, other_shmem2_base_addr);
5813 }
5814 bnx2x_acquire_phy_lock(bp);
5815 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5816 bp->common.chip_id);
5817 bnx2x_release_phy_lock(bp);
5818 }
5819
5820 /**
5821 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5822 *
5823 * @bp: driver handle
5824 */
5825 static int bnx2x_init_hw_common(struct bnx2x *bp)
5826 {
5827 u32 val;
5828
5829 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5830
5831 /*
5832 * take the UNDI lock to protect undi_unload flow from accessing
5833 * registers while we're resetting the chip
5834 */
5835 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5836
5837 bnx2x_reset_common(bp);
5838 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5839
5840 val = 0xfffc;
5841 if (CHIP_IS_E3(bp)) {
5842 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5843 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5844 }
5845 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5846
5847 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5848
5849 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5850
5851 if (!CHIP_IS_E1x(bp)) {
5852 u8 abs_func_id;
5853
5854 /**
5855 * 4-port mode or 2-port mode we need to turn of master-enable
5856 * for everyone, after that, turn it back on for self.
5857 * so, we disregard multi-function or not, and always disable
5858 * for all functions on the given path, this means 0,2,4,6 for
5859 * path 0 and 1,3,5,7 for path 1
5860 */
5861 for (abs_func_id = BP_PATH(bp);
5862 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5863 if (abs_func_id == BP_ABS_FUNC(bp)) {
5864 REG_WR(bp,
5865 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5866 1);
5867 continue;
5868 }
5869
5870 bnx2x_pretend_func(bp, abs_func_id);
5871 /* clear pf enable */
5872 bnx2x_pf_disable(bp);
5873 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5874 }
5875 }
5876
5877 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5878 if (CHIP_IS_E1(bp)) {
5879 /* enable HW interrupt from PXP on USDM overflow
5880 bit 16 on INT_MASK_0 */
5881 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5882 }
5883
5884 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5885 bnx2x_init_pxp(bp);
5886
5887 #ifdef __BIG_ENDIAN
5888 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5889 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5890 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5891 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5892 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5893 /* make sure this value is 0 */
5894 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5895
5896 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5897 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5898 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5899 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5900 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5901 #endif
5902
5903 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5904
5905 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5906 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5907
5908 /* let the HW do it's magic ... */
5909 msleep(100);
5910 /* finish PXP init */
5911 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5912 if (val != 1) {
5913 BNX2X_ERR("PXP2 CFG failed\n");
5914 return -EBUSY;
5915 }
5916 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5917 if (val != 1) {
5918 BNX2X_ERR("PXP2 RD_INIT failed\n");
5919 return -EBUSY;
5920 }
5921
5922 /* Timers bug workaround E2 only. We need to set the entire ILT to
5923 * have entries with value "0" and valid bit on.
5924 * This needs to be done by the first PF that is loaded in a path
5925 * (i.e. common phase)
5926 */
5927 if (!CHIP_IS_E1x(bp)) {
5928 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5929 * (i.e. vnic3) to start even if it is marked as "scan-off".
5930 * This occurs when a different function (func2,3) is being marked
5931 * as "scan-off". Real-life scenario for example: if a driver is being
5932 * load-unloaded while func6,7 are down. This will cause the timer to access
5933 * the ilt, translate to a logical address and send a request to read/write.
5934 * Since the ilt for the function that is down is not valid, this will cause
5935 * a translation error which is unrecoverable.
5936 * The Workaround is intended to make sure that when this happens nothing fatal
5937 * will occur. The workaround:
5938 * 1. First PF driver which loads on a path will:
5939 * a. After taking the chip out of reset, by using pretend,
5940 * it will write "0" to the following registers of
5941 * the other vnics.
5942 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5943 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5944 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5945 * And for itself it will write '1' to
5946 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5947 * dmae-operations (writing to pram for example.)
5948 * note: can be done for only function 6,7 but cleaner this
5949 * way.
5950 * b. Write zero+valid to the entire ILT.
5951 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5952 * VNIC3 (of that port). The range allocated will be the
5953 * entire ILT. This is needed to prevent ILT range error.
5954 * 2. Any PF driver load flow:
5955 * a. ILT update with the physical addresses of the allocated
5956 * logical pages.
5957 * b. Wait 20msec. - note that this timeout is needed to make
5958 * sure there are no requests in one of the PXP internal
5959 * queues with "old" ILT addresses.
5960 * c. PF enable in the PGLC.
5961 * d. Clear the was_error of the PF in the PGLC. (could have
5962 * occured while driver was down)
5963 * e. PF enable in the CFC (WEAK + STRONG)
5964 * f. Timers scan enable
5965 * 3. PF driver unload flow:
5966 * a. Clear the Timers scan_en.
5967 * b. Polling for scan_on=0 for that PF.
5968 * c. Clear the PF enable bit in the PXP.
5969 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5970 * e. Write zero+valid to all ILT entries (The valid bit must
5971 * stay set)
5972 * f. If this is VNIC 3 of a port then also init
5973 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5974 * to the last enrty in the ILT.
5975 *
5976 * Notes:
5977 * Currently the PF error in the PGLC is non recoverable.
5978 * In the future the there will be a recovery routine for this error.
5979 * Currently attention is masked.
5980 * Having an MCP lock on the load/unload process does not guarantee that
5981 * there is no Timer disable during Func6/7 enable. This is because the
5982 * Timers scan is currently being cleared by the MCP on FLR.
5983 * Step 2.d can be done only for PF6/7 and the driver can also check if
5984 * there is error before clearing it. But the flow above is simpler and
5985 * more general.
5986 * All ILT entries are written by zero+valid and not just PF6/7
5987 * ILT entries since in the future the ILT entries allocation for
5988 * PF-s might be dynamic.
5989 */
5990 struct ilt_client_info ilt_cli;
5991 struct bnx2x_ilt ilt;
5992 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5993 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5994
5995 /* initialize dummy TM client */
5996 ilt_cli.start = 0;
5997 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5998 ilt_cli.client_num = ILT_CLIENT_TM;
5999
6000 /* Step 1: set zeroes to all ilt page entries with valid bit on
6001 * Step 2: set the timers first/last ilt entry to point
6002 * to the entire range to prevent ILT range error for 3rd/4th
6003 * vnic (this code assumes existance of the vnic)
6004 *
6005 * both steps performed by call to bnx2x_ilt_client_init_op()
6006 * with dummy TM client
6007 *
6008 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6009 * and his brother are split registers
6010 */
6011 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6012 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6013 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6014
6015 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6016 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6017 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6018 }
6019
6020
6021 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6022 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6023
6024 if (!CHIP_IS_E1x(bp)) {
6025 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6026 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6027 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6028
6029 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6030
6031 /* let the HW do it's magic ... */
6032 do {
6033 msleep(200);
6034 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6035 } while (factor-- && (val != 1));
6036
6037 if (val != 1) {
6038 BNX2X_ERR("ATC_INIT failed\n");
6039 return -EBUSY;
6040 }
6041 }
6042
6043 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6044
6045 /* clean the DMAE memory */
6046 bp->dmae_ready = 1;
6047 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6048
6049 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6050
6051 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6052
6053 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6054
6055 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6056
6057 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6058 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6059 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6060 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6061
6062 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6063
6064
6065 /* QM queues pointers table */
6066 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6067
6068 /* soft reset pulse */
6069 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6070 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6071
6072 #ifdef BCM_CNIC
6073 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6074 #endif
6075
6076 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6077 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6078 if (!CHIP_REV_IS_SLOW(bp))
6079 /* enable hw interrupt from doorbell Q */
6080 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6081
6082 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6083
6084 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6085 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6086
6087 if (!CHIP_IS_E1(bp))
6088 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6089
6090 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6091 /* Bit-map indicating which L2 hdrs may appear
6092 * after the basic Ethernet header
6093 */
6094 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6095 bp->path_has_ovlan ? 7 : 6);
6096
6097 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6098 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6099 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6100 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6101
6102 if (!CHIP_IS_E1x(bp)) {
6103 /* reset VFC memories */
6104 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6105 VFC_MEMORIES_RST_REG_CAM_RST |
6106 VFC_MEMORIES_RST_REG_RAM_RST);
6107 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6108 VFC_MEMORIES_RST_REG_CAM_RST |
6109 VFC_MEMORIES_RST_REG_RAM_RST);
6110
6111 msleep(20);
6112 }
6113
6114 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6115 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6116 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6117 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6118
6119 /* sync semi rtc */
6120 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6121 0x80000000);
6122 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6123 0x80000000);
6124
6125 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6126 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6127 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6128
6129 if (!CHIP_IS_E1x(bp))
6130 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6131 bp->path_has_ovlan ? 7 : 6);
6132
6133 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6134
6135 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6136
6137 #ifdef BCM_CNIC
6138 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6139 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6140 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6141 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6142 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6143 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6144 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6145 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6146 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6147 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6148 #endif
6149 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6150
6151 if (sizeof(union cdu_context) != 1024)
6152 /* we currently assume that a context is 1024 bytes */
6153 dev_alert(&bp->pdev->dev, "please adjust the size "
6154 "of cdu_context(%ld)\n",
6155 (long)sizeof(union cdu_context));
6156
6157 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6158 val = (4 << 24) + (0 << 12) + 1024;
6159 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6160
6161 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6162 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6163 /* enable context validation interrupt from CFC */
6164 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6165
6166 /* set the thresholds to prevent CFC/CDU race */
6167 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6168
6169 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6170
6171 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6172 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6173
6174 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6175 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6176
6177 /* Reset PCIE errors for debug */
6178 REG_WR(bp, 0x2814, 0xffffffff);
6179 REG_WR(bp, 0x3820, 0xffffffff);
6180
6181 if (!CHIP_IS_E1x(bp)) {
6182 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6183 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6184 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6185 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6186 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6187 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6188 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6189 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6190 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6191 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6192 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6193 }
6194
6195 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6196 if (!CHIP_IS_E1(bp)) {
6197 /* in E3 this done in per-port section */
6198 if (!CHIP_IS_E3(bp))
6199 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6200 }
6201 if (CHIP_IS_E1H(bp))
6202 /* not applicable for E2 (and above ...) */
6203 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6204
6205 if (CHIP_REV_IS_SLOW(bp))
6206 msleep(200);
6207
6208 /* finish CFC init */
6209 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6210 if (val != 1) {
6211 BNX2X_ERR("CFC LL_INIT failed\n");
6212 return -EBUSY;
6213 }
6214 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6215 if (val != 1) {
6216 BNX2X_ERR("CFC AC_INIT failed\n");
6217 return -EBUSY;
6218 }
6219 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6220 if (val != 1) {
6221 BNX2X_ERR("CFC CAM_INIT failed\n");
6222 return -EBUSY;
6223 }
6224 REG_WR(bp, CFC_REG_DEBUG0, 0);
6225
6226 if (CHIP_IS_E1(bp)) {
6227 /* read NIG statistic
6228 to see if this is our first up since powerup */
6229 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6230 val = *bnx2x_sp(bp, wb_data[0]);
6231
6232 /* do internal memory self test */
6233 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6234 BNX2X_ERR("internal mem self test failed\n");
6235 return -EBUSY;
6236 }
6237 }
6238
6239 bnx2x_setup_fan_failure_detection(bp);
6240
6241 /* clear PXP2 attentions */
6242 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6243
6244 bnx2x_enable_blocks_attention(bp);
6245 bnx2x_enable_blocks_parity(bp);
6246
6247 if (!BP_NOMCP(bp)) {
6248 if (CHIP_IS_E1x(bp))
6249 bnx2x__common_init_phy(bp);
6250 } else
6251 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6252
6253 return 0;
6254 }
6255
6256 /**
6257 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6258 *
6259 * @bp: driver handle
6260 */
6261 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6262 {
6263 int rc = bnx2x_init_hw_common(bp);
6264
6265 if (rc)
6266 return rc;
6267
6268 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6269 if (!BP_NOMCP(bp))
6270 bnx2x__common_init_phy(bp);
6271
6272 return 0;
6273 }
6274
6275 static int bnx2x_init_hw_port(struct bnx2x *bp)
6276 {
6277 int port = BP_PORT(bp);
6278 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6279 u32 low, high;
6280 u32 val;
6281
6282 bnx2x__link_reset(bp);
6283
6284 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6285
6286 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6287
6288 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6289 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6290 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6291
6292 /* Timers bug workaround: disables the pf_master bit in pglue at
6293 * common phase, we need to enable it here before any dmae access are
6294 * attempted. Therefore we manually added the enable-master to the
6295 * port phase (it also happens in the function phase)
6296 */
6297 if (!CHIP_IS_E1x(bp))
6298 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6299
6300 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6301 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6302 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6303 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6304
6305 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6306 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6307 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6308 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6309
6310 /* QM cid (connection) count */
6311 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6312
6313 #ifdef BCM_CNIC
6314 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6315 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6316 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6317 #endif
6318
6319 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6320
6321 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6322 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6323
6324 if (IS_MF(bp))
6325 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6326 else if (bp->dev->mtu > 4096) {
6327 if (bp->flags & ONE_PORT_FLAG)
6328 low = 160;
6329 else {
6330 val = bp->dev->mtu;
6331 /* (24*1024 + val*4)/256 */
6332 low = 96 + (val/64) +
6333 ((val % 64) ? 1 : 0);
6334 }
6335 } else
6336 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6337 high = low + 56; /* 14*1024/256 */
6338 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6339 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6340 }
6341
6342 if (CHIP_MODE_IS_4_PORT(bp))
6343 REG_WR(bp, (BP_PORT(bp) ?
6344 BRB1_REG_MAC_GUARANTIED_1 :
6345 BRB1_REG_MAC_GUARANTIED_0), 40);
6346
6347
6348 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6349 if (CHIP_IS_E3B0(bp))
6350 /* Ovlan exists only if we are in multi-function +
6351 * switch-dependent mode, in switch-independent there
6352 * is no ovlan headers
6353 */
6354 REG_WR(bp, BP_PORT(bp) ?
6355 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6356 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6357 (bp->path_has_ovlan ? 7 : 6));
6358
6359 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6360 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6361 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6362 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6363
6364 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6365 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6366 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6367 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6368
6369 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6370 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6371
6372 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6373
6374 if (CHIP_IS_E1x(bp)) {
6375 /* configure PBF to work without PAUSE mtu 9000 */
6376 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6377
6378 /* update threshold */
6379 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6380 /* update init credit */
6381 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6382
6383 /* probe changes */
6384 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6385 udelay(50);
6386 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6387 }
6388
6389 #ifdef BCM_CNIC
6390 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6391 #endif
6392 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6393 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6394
6395 if (CHIP_IS_E1(bp)) {
6396 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6397 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6398 }
6399 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6400
6401 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6402
6403 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6404 /* init aeu_mask_attn_func_0/1:
6405 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6406 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6407 * bits 4-7 are used for "per vn group attention" */
6408 val = IS_MF(bp) ? 0xF7 : 0x7;
6409 /* Enable DCBX attention for all but E1 */
6410 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6411 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6412
6413 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6414
6415 if (!CHIP_IS_E1x(bp)) {
6416 /* Bit-map indicating which L2 hdrs may appear after the
6417 * basic Ethernet header
6418 */
6419 REG_WR(bp, BP_PORT(bp) ?
6420 NIG_REG_P1_HDRS_AFTER_BASIC :
6421 NIG_REG_P0_HDRS_AFTER_BASIC,
6422 IS_MF_SD(bp) ? 7 : 6);
6423
6424 if (CHIP_IS_E3(bp))
6425 REG_WR(bp, BP_PORT(bp) ?
6426 NIG_REG_LLH1_MF_MODE :
6427 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6428 }
6429 if (!CHIP_IS_E3(bp))
6430 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6431
6432 if (!CHIP_IS_E1(bp)) {
6433 /* 0x2 disable mf_ov, 0x1 enable */
6434 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6435 (IS_MF_SD(bp) ? 0x1 : 0x2));
6436
6437 if (!CHIP_IS_E1x(bp)) {
6438 val = 0;
6439 switch (bp->mf_mode) {
6440 case MULTI_FUNCTION_SD:
6441 val = 1;
6442 break;
6443 case MULTI_FUNCTION_SI:
6444 val = 2;
6445 break;
6446 }
6447
6448 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6449 NIG_REG_LLH0_CLS_TYPE), val);
6450 }
6451 {
6452 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6453 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6454 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6455 }
6456 }
6457
6458
6459 /* If SPIO5 is set to generate interrupts, enable it for this port */
6460 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6461 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6462 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6463 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6464 val = REG_RD(bp, reg_addr);
6465 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6466 REG_WR(bp, reg_addr, val);
6467 }
6468
6469 return 0;
6470 }
6471
6472 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6473 {
6474 int reg;
6475
6476 if (CHIP_IS_E1(bp))
6477 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6478 else
6479 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6480
6481 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6482 }
6483
6484 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6485 {
6486 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6487 }
6488
6489 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6490 {
6491 u32 i, base = FUNC_ILT_BASE(func);
6492 for (i = base; i < base + ILT_PER_FUNC; i++)
6493 bnx2x_ilt_wr(bp, i, 0);
6494 }
6495
6496 static int bnx2x_init_hw_func(struct bnx2x *bp)
6497 {
6498 int port = BP_PORT(bp);
6499 int func = BP_FUNC(bp);
6500 int init_phase = PHASE_PF0 + func;
6501 struct bnx2x_ilt *ilt = BP_ILT(bp);
6502 u16 cdu_ilt_start;
6503 u32 addr, val;
6504 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6505 int i, main_mem_width;
6506
6507 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6508
6509 /* FLR cleanup - hmmm */
6510 if (!CHIP_IS_E1x(bp))
6511 bnx2x_pf_flr_clnup(bp);
6512
6513 /* set MSI reconfigure capability */
6514 if (bp->common.int_block == INT_BLOCK_HC) {
6515 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6516 val = REG_RD(bp, addr);
6517 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6518 REG_WR(bp, addr, val);
6519 }
6520
6521 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6522 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6523
6524 ilt = BP_ILT(bp);
6525 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6526
6527 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6528 ilt->lines[cdu_ilt_start + i].page =
6529 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6530 ilt->lines[cdu_ilt_start + i].page_mapping =
6531 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6532 /* cdu ilt pages are allocated manually so there's no need to
6533 set the size */
6534 }
6535 bnx2x_ilt_init_op(bp, INITOP_SET);
6536
6537 #ifdef BCM_CNIC
6538 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6539
6540 /* T1 hash bits value determines the T1 number of entries */
6541 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6542 #endif
6543
6544 #ifndef BCM_CNIC
6545 /* set NIC mode */
6546 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6547 #endif /* BCM_CNIC */
6548
6549 if (!CHIP_IS_E1x(bp)) {
6550 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6551
6552 /* Turn on a single ISR mode in IGU if driver is going to use
6553 * INT#x or MSI
6554 */
6555 if (!(bp->flags & USING_MSIX_FLAG))
6556 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6557 /*
6558 * Timers workaround bug: function init part.
6559 * Need to wait 20msec after initializing ILT,
6560 * needed to make sure there are no requests in
6561 * one of the PXP internal queues with "old" ILT addresses
6562 */
6563 msleep(20);
6564 /*
6565 * Master enable - Due to WB DMAE writes performed before this
6566 * register is re-initialized as part of the regular function
6567 * init
6568 */
6569 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6570 /* Enable the function in IGU */
6571 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6572 }
6573
6574 bp->dmae_ready = 1;
6575
6576 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6577
6578 if (!CHIP_IS_E1x(bp))
6579 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6580
6581 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6582 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6583 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6584 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6585 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6586 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6587 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6588 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6589 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6590 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6591 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6592 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6593 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6594
6595 if (!CHIP_IS_E1x(bp))
6596 REG_WR(bp, QM_REG_PF_EN, 1);
6597
6598 if (!CHIP_IS_E1x(bp)) {
6599 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6600 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6601 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6602 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6603 }
6604 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6605
6606 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6607 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6608 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6609 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6610 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6611 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6612 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6613 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6614 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6615 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6616 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6617 if (!CHIP_IS_E1x(bp))
6618 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6619
6620 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6621
6622 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6623
6624 if (!CHIP_IS_E1x(bp))
6625 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6626
6627 if (IS_MF(bp)) {
6628 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6629 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6630 }
6631
6632 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6633
6634 /* HC init per function */
6635 if (bp->common.int_block == INT_BLOCK_HC) {
6636 if (CHIP_IS_E1H(bp)) {
6637 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6638
6639 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6640 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6641 }
6642 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6643
6644 } else {
6645 int num_segs, sb_idx, prod_offset;
6646
6647 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6648
6649 if (!CHIP_IS_E1x(bp)) {
6650 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6651 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6652 }
6653
6654 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6655
6656 if (!CHIP_IS_E1x(bp)) {
6657 int dsb_idx = 0;
6658 /**
6659 * Producer memory:
6660 * E2 mode: address 0-135 match to the mapping memory;
6661 * 136 - PF0 default prod; 137 - PF1 default prod;
6662 * 138 - PF2 default prod; 139 - PF3 default prod;
6663 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6664 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6665 * 144-147 reserved.
6666 *
6667 * E1.5 mode - In backward compatible mode;
6668 * for non default SB; each even line in the memory
6669 * holds the U producer and each odd line hold
6670 * the C producer. The first 128 producers are for
6671 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6672 * producers are for the DSB for each PF.
6673 * Each PF has five segments: (the order inside each
6674 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6675 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6676 * 144-147 attn prods;
6677 */
6678 /* non-default-status-blocks */
6679 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6680 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6681 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6682 prod_offset = (bp->igu_base_sb + sb_idx) *
6683 num_segs;
6684
6685 for (i = 0; i < num_segs; i++) {
6686 addr = IGU_REG_PROD_CONS_MEMORY +
6687 (prod_offset + i) * 4;
6688 REG_WR(bp, addr, 0);
6689 }
6690 /* send consumer update with value 0 */
6691 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6692 USTORM_ID, 0, IGU_INT_NOP, 1);
6693 bnx2x_igu_clear_sb(bp,
6694 bp->igu_base_sb + sb_idx);
6695 }
6696
6697 /* default-status-blocks */
6698 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6699 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6700
6701 if (CHIP_MODE_IS_4_PORT(bp))
6702 dsb_idx = BP_FUNC(bp);
6703 else
6704 dsb_idx = BP_VN(bp);
6705
6706 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6707 IGU_BC_BASE_DSB_PROD + dsb_idx :
6708 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6709
6710 /*
6711 * igu prods come in chunks of E1HVN_MAX (4) -
6712 * does not matters what is the current chip mode
6713 */
6714 for (i = 0; i < (num_segs * E1HVN_MAX);
6715 i += E1HVN_MAX) {
6716 addr = IGU_REG_PROD_CONS_MEMORY +
6717 (prod_offset + i)*4;
6718 REG_WR(bp, addr, 0);
6719 }
6720 /* send consumer update with 0 */
6721 if (CHIP_INT_MODE_IS_BC(bp)) {
6722 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6723 USTORM_ID, 0, IGU_INT_NOP, 1);
6724 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6725 CSTORM_ID, 0, IGU_INT_NOP, 1);
6726 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6727 XSTORM_ID, 0, IGU_INT_NOP, 1);
6728 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6729 TSTORM_ID, 0, IGU_INT_NOP, 1);
6730 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6731 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6732 } else {
6733 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6734 USTORM_ID, 0, IGU_INT_NOP, 1);
6735 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6736 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6737 }
6738 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6739
6740 /* !!! these should become driver const once
6741 rf-tool supports split-68 const */
6742 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6744 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6745 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6746 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6747 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6748 }
6749 }
6750
6751 /* Reset PCIE errors for debug */
6752 REG_WR(bp, 0x2114, 0xffffffff);
6753 REG_WR(bp, 0x2120, 0xffffffff);
6754
6755 if (CHIP_IS_E1x(bp)) {
6756 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6757 main_mem_base = HC_REG_MAIN_MEMORY +
6758 BP_PORT(bp) * (main_mem_size * 4);
6759 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6760 main_mem_width = 8;
6761
6762 val = REG_RD(bp, main_mem_prty_clr);
6763 if (val)
6764 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6765 "block during "
6766 "function init (0x%x)!\n", val);
6767
6768 /* Clear "false" parity errors in MSI-X table */
6769 for (i = main_mem_base;
6770 i < main_mem_base + main_mem_size * 4;
6771 i += main_mem_width) {
6772 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6773 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6774 i, main_mem_width / 4);
6775 }
6776 /* Clear HC parity attention */
6777 REG_RD(bp, main_mem_prty_clr);
6778 }
6779
6780 #ifdef BNX2X_STOP_ON_ERROR
6781 /* Enable STORMs SP logging */
6782 REG_WR8(bp, BAR_USTRORM_INTMEM +
6783 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6784 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6785 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6786 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6787 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6788 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6789 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6790 #endif
6791
6792 bnx2x_phy_probe(&bp->link_params);
6793
6794 return 0;
6795 }
6796
6797
6798 void bnx2x_free_mem(struct bnx2x *bp)
6799 {
6800 /* fastpath */
6801 bnx2x_free_fp_mem(bp);
6802 /* end of fastpath */
6803
6804 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6805 sizeof(struct host_sp_status_block));
6806
6807 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6808 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6809
6810 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6811 sizeof(struct bnx2x_slowpath));
6812
6813 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6814 bp->context.size);
6815
6816 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6817
6818 BNX2X_FREE(bp->ilt->lines);
6819
6820 #ifdef BCM_CNIC
6821 if (!CHIP_IS_E1x(bp))
6822 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6823 sizeof(struct host_hc_status_block_e2));
6824 else
6825 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6826 sizeof(struct host_hc_status_block_e1x));
6827
6828 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6829 #endif
6830
6831 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6832
6833 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6834 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6835 }
6836
6837 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6838 {
6839 int num_groups;
6840
6841 /* number of eth_queues */
6842 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6843
6844 /* Total number of FW statistics requests =
6845 * 1 for port stats + 1 for PF stats + num_eth_queues */
6846 bp->fw_stats_num = 2 + num_queue_stats;
6847
6848
6849 /* Request is built from stats_query_header and an array of
6850 * stats_query_cmd_group each of which contains
6851 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6852 * configured in the stats_query_header.
6853 */
6854 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6855 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6856
6857 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6858 num_groups * sizeof(struct stats_query_cmd_group);
6859
6860 /* Data for statistics requests + stats_conter
6861 *
6862 * stats_counter holds per-STORM counters that are incremented
6863 * when STORM has finished with the current request.
6864 */
6865 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6866 sizeof(struct per_pf_stats) +
6867 sizeof(struct per_queue_stats) * num_queue_stats +
6868 sizeof(struct stats_counter);
6869
6870 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6871 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6872
6873 /* Set shortcuts */
6874 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6875 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6876
6877 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6878 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6879
6880 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6881 bp->fw_stats_req_sz;
6882 return 0;
6883
6884 alloc_mem_err:
6885 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6886 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6887 return -ENOMEM;
6888 }
6889
6890
6891 int bnx2x_alloc_mem(struct bnx2x *bp)
6892 {
6893 #ifdef BCM_CNIC
6894 if (!CHIP_IS_E1x(bp))
6895 /* size = the status block + ramrod buffers */
6896 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6897 sizeof(struct host_hc_status_block_e2));
6898 else
6899 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6900 sizeof(struct host_hc_status_block_e1x));
6901
6902 /* allocate searcher T2 table */
6903 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6904 #endif
6905
6906
6907 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6908 sizeof(struct host_sp_status_block));
6909
6910 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6911 sizeof(struct bnx2x_slowpath));
6912
6913 /* Allocated memory for FW statistics */
6914 if (bnx2x_alloc_fw_stats_mem(bp))
6915 goto alloc_mem_err;
6916
6917 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6918
6919 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6920 bp->context.size);
6921
6922 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6923
6924 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6925 goto alloc_mem_err;
6926
6927 /* Slow path ring */
6928 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6929
6930 /* EQ */
6931 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6932 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6933
6934
6935 /* fastpath */
6936 /* need to be done at the end, since it's self adjusting to amount
6937 * of memory available for RSS queues
6938 */
6939 if (bnx2x_alloc_fp_mem(bp))
6940 goto alloc_mem_err;
6941 return 0;
6942
6943 alloc_mem_err:
6944 bnx2x_free_mem(bp);
6945 return -ENOMEM;
6946 }
6947
6948 /*
6949 * Init service functions
6950 */
6951
6952 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6953 struct bnx2x_vlan_mac_obj *obj, bool set,
6954 int mac_type, unsigned long *ramrod_flags)
6955 {
6956 int rc;
6957 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6958
6959 memset(&ramrod_param, 0, sizeof(ramrod_param));
6960
6961 /* Fill general parameters */
6962 ramrod_param.vlan_mac_obj = obj;
6963 ramrod_param.ramrod_flags = *ramrod_flags;
6964
6965 /* Fill a user request section if needed */
6966 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6967 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6968
6969 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6970
6971 /* Set the command: ADD or DEL */
6972 if (set)
6973 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6974 else
6975 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6976 }
6977
6978 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6979 if (rc < 0)
6980 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6981 return rc;
6982 }
6983
6984 int bnx2x_del_all_macs(struct bnx2x *bp,
6985 struct bnx2x_vlan_mac_obj *mac_obj,
6986 int mac_type, bool wait_for_comp)
6987 {
6988 int rc;
6989 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6990
6991 /* Wait for completion of requested */
6992 if (wait_for_comp)
6993 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6994
6995 /* Set the mac type of addresses we want to clear */
6996 __set_bit(mac_type, &vlan_mac_flags);
6997
6998 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6999 if (rc < 0)
7000 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7001
7002 return rc;
7003 }
7004
7005 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7006 {
7007 unsigned long ramrod_flags = 0;
7008
7009 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7010
7011 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7012 /* Eth MAC is set on RSS leading client (fp[0]) */
7013 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7014 BNX2X_ETH_MAC, &ramrod_flags);
7015 }
7016
7017 int bnx2x_setup_leading(struct bnx2x *bp)
7018 {
7019 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7020 }
7021
7022 /**
7023 * bnx2x_set_int_mode - configure interrupt mode
7024 *
7025 * @bp: driver handle
7026 *
7027 * In case of MSI-X it will also try to enable MSI-X.
7028 */
7029 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7030 {
7031 switch (int_mode) {
7032 case INT_MODE_MSI:
7033 bnx2x_enable_msi(bp);
7034 /* falling through... */
7035 case INT_MODE_INTx:
7036 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7037 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7038 break;
7039 default:
7040 /* Set number of queues according to bp->multi_mode value */
7041 bnx2x_set_num_queues(bp);
7042
7043 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7044 bp->num_queues);
7045
7046 /* if we can't use MSI-X we only need one fp,
7047 * so try to enable MSI-X with the requested number of fp's
7048 * and fallback to MSI or legacy INTx with one fp
7049 */
7050 if (bnx2x_enable_msix(bp)) {
7051 /* failed to enable MSI-X */
7052 if (bp->multi_mode)
7053 DP(NETIF_MSG_IFUP,
7054 "Multi requested but failed to "
7055 "enable MSI-X (%d), "
7056 "set number of queues to %d\n",
7057 bp->num_queues,
7058 1 + NON_ETH_CONTEXT_USE);
7059 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7060
7061 /* Try to enable MSI */
7062 if (!(bp->flags & DISABLE_MSI_FLAG))
7063 bnx2x_enable_msi(bp);
7064 }
7065 break;
7066 }
7067 }
7068
7069 /* must be called prioir to any HW initializations */
7070 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7071 {
7072 return L2_ILT_LINES(bp);
7073 }
7074
7075 void bnx2x_ilt_set_info(struct bnx2x *bp)
7076 {
7077 struct ilt_client_info *ilt_client;
7078 struct bnx2x_ilt *ilt = BP_ILT(bp);
7079 u16 line = 0;
7080
7081 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7082 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7083
7084 /* CDU */
7085 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7086 ilt_client->client_num = ILT_CLIENT_CDU;
7087 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7088 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7089 ilt_client->start = line;
7090 line += bnx2x_cid_ilt_lines(bp);
7091 #ifdef BCM_CNIC
7092 line += CNIC_ILT_LINES;
7093 #endif
7094 ilt_client->end = line - 1;
7095
7096 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7097 "flags 0x%x, hw psz %d\n",
7098 ilt_client->start,
7099 ilt_client->end,
7100 ilt_client->page_size,
7101 ilt_client->flags,
7102 ilog2(ilt_client->page_size >> 12));
7103
7104 /* QM */
7105 if (QM_INIT(bp->qm_cid_count)) {
7106 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7107 ilt_client->client_num = ILT_CLIENT_QM;
7108 ilt_client->page_size = QM_ILT_PAGE_SZ;
7109 ilt_client->flags = 0;
7110 ilt_client->start = line;
7111
7112 /* 4 bytes for each cid */
7113 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7114 QM_ILT_PAGE_SZ);
7115
7116 ilt_client->end = line - 1;
7117
7118 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7119 "flags 0x%x, hw psz %d\n",
7120 ilt_client->start,
7121 ilt_client->end,
7122 ilt_client->page_size,
7123 ilt_client->flags,
7124 ilog2(ilt_client->page_size >> 12));
7125
7126 }
7127 /* SRC */
7128 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7129 #ifdef BCM_CNIC
7130 ilt_client->client_num = ILT_CLIENT_SRC;
7131 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7132 ilt_client->flags = 0;
7133 ilt_client->start = line;
7134 line += SRC_ILT_LINES;
7135 ilt_client->end = line - 1;
7136
7137 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7138 "flags 0x%x, hw psz %d\n",
7139 ilt_client->start,
7140 ilt_client->end,
7141 ilt_client->page_size,
7142 ilt_client->flags,
7143 ilog2(ilt_client->page_size >> 12));
7144
7145 #else
7146 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7147 #endif
7148
7149 /* TM */
7150 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7151 #ifdef BCM_CNIC
7152 ilt_client->client_num = ILT_CLIENT_TM;
7153 ilt_client->page_size = TM_ILT_PAGE_SZ;
7154 ilt_client->flags = 0;
7155 ilt_client->start = line;
7156 line += TM_ILT_LINES;
7157 ilt_client->end = line - 1;
7158
7159 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7160 "flags 0x%x, hw psz %d\n",
7161 ilt_client->start,
7162 ilt_client->end,
7163 ilt_client->page_size,
7164 ilt_client->flags,
7165 ilog2(ilt_client->page_size >> 12));
7166
7167 #else
7168 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7169 #endif
7170 BUG_ON(line > ILT_MAX_LINES);
7171 }
7172
7173 /**
7174 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7175 *
7176 * @bp: driver handle
7177 * @fp: pointer to fastpath
7178 * @init_params: pointer to parameters structure
7179 *
7180 * parameters configured:
7181 * - HC configuration
7182 * - Queue's CDU context
7183 */
7184 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7185 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7186 {
7187
7188 u8 cos;
7189 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7190 if (!IS_FCOE_FP(fp)) {
7191 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7192 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7193
7194 /* If HC is supporterd, enable host coalescing in the transition
7195 * to INIT state.
7196 */
7197 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7198 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7199
7200 /* HC rate */
7201 init_params->rx.hc_rate = bp->rx_ticks ?
7202 (1000000 / bp->rx_ticks) : 0;
7203 init_params->tx.hc_rate = bp->tx_ticks ?
7204 (1000000 / bp->tx_ticks) : 0;
7205
7206 /* FW SB ID */
7207 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7208 fp->fw_sb_id;
7209
7210 /*
7211 * CQ index among the SB indices: FCoE clients uses the default
7212 * SB, therefore it's different.
7213 */
7214 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7215 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7216 }
7217
7218 /* set maximum number of COSs supported by this queue */
7219 init_params->max_cos = fp->max_cos;
7220
7221 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
7222 fp->index, init_params->max_cos);
7223
7224 /* set the context pointers queue object */
7225 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7226 init_params->cxts[cos] =
7227 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7228 }
7229
7230 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7231 struct bnx2x_queue_state_params *q_params,
7232 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7233 int tx_index, bool leading)
7234 {
7235 memset(tx_only_params, 0, sizeof(*tx_only_params));
7236
7237 /* Set the command */
7238 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7239
7240 /* Set tx-only QUEUE flags: don't zero statistics */
7241 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7242
7243 /* choose the index of the cid to send the slow path on */
7244 tx_only_params->cid_index = tx_index;
7245
7246 /* Set general TX_ONLY_SETUP parameters */
7247 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7248
7249 /* Set Tx TX_ONLY_SETUP parameters */
7250 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7251
7252 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7253 "cos %d, primary cid %d, cid %d, "
7254 "client id %d, sp-client id %d, flags %lx\n",
7255 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7256 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7257 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7258
7259 /* send the ramrod */
7260 return bnx2x_queue_state_change(bp, q_params);
7261 }
7262
7263
7264 /**
7265 * bnx2x_setup_queue - setup queue
7266 *
7267 * @bp: driver handle
7268 * @fp: pointer to fastpath
7269 * @leading: is leading
7270 *
7271 * This function performs 2 steps in a Queue state machine
7272 * actually: 1) RESET->INIT 2) INIT->SETUP
7273 */
7274
7275 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7276 bool leading)
7277 {
7278 struct bnx2x_queue_state_params q_params = {0};
7279 struct bnx2x_queue_setup_params *setup_params =
7280 &q_params.params.setup;
7281 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7282 &q_params.params.tx_only;
7283 int rc;
7284 u8 tx_index;
7285
7286 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
7287
7288 /* reset IGU state skip FCoE L2 queue */
7289 if (!IS_FCOE_FP(fp))
7290 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7291 IGU_INT_ENABLE, 0);
7292
7293 q_params.q_obj = &fp->q_obj;
7294 /* We want to wait for completion in this context */
7295 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7296
7297 /* Prepare the INIT parameters */
7298 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7299
7300 /* Set the command */
7301 q_params.cmd = BNX2X_Q_CMD_INIT;
7302
7303 /* Change the state to INIT */
7304 rc = bnx2x_queue_state_change(bp, &q_params);
7305 if (rc) {
7306 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7307 return rc;
7308 }
7309
7310 DP(BNX2X_MSG_SP, "init complete\n");
7311
7312
7313 /* Now move the Queue to the SETUP state... */
7314 memset(setup_params, 0, sizeof(*setup_params));
7315
7316 /* Set QUEUE flags */
7317 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7318
7319 /* Set general SETUP parameters */
7320 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7321 FIRST_TX_COS_INDEX);
7322
7323 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7324 &setup_params->rxq_params);
7325
7326 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7327 FIRST_TX_COS_INDEX);
7328
7329 /* Set the command */
7330 q_params.cmd = BNX2X_Q_CMD_SETUP;
7331
7332 /* Change the state to SETUP */
7333 rc = bnx2x_queue_state_change(bp, &q_params);
7334 if (rc) {
7335 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7336 return rc;
7337 }
7338
7339 /* loop through the relevant tx-only indices */
7340 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7341 tx_index < fp->max_cos;
7342 tx_index++) {
7343
7344 /* prepare and send tx-only ramrod*/
7345 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7346 tx_only_params, tx_index, leading);
7347 if (rc) {
7348 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7349 fp->index, tx_index);
7350 return rc;
7351 }
7352 }
7353
7354 return rc;
7355 }
7356
7357 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7358 {
7359 struct bnx2x_fastpath *fp = &bp->fp[index];
7360 struct bnx2x_fp_txdata *txdata;
7361 struct bnx2x_queue_state_params q_params = {0};
7362 int rc, tx_index;
7363
7364 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
7365
7366 q_params.q_obj = &fp->q_obj;
7367 /* We want to wait for completion in this context */
7368 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7369
7370
7371 /* close tx-only connections */
7372 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7373 tx_index < fp->max_cos;
7374 tx_index++){
7375
7376 /* ascertain this is a normal queue*/
7377 txdata = &fp->txdata[tx_index];
7378
7379 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
7380 txdata->txq_index);
7381
7382 /* send halt terminate on tx-only connection */
7383 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7384 memset(&q_params.params.terminate, 0,
7385 sizeof(q_params.params.terminate));
7386 q_params.params.terminate.cid_index = tx_index;
7387
7388 rc = bnx2x_queue_state_change(bp, &q_params);
7389 if (rc)
7390 return rc;
7391
7392 /* send halt terminate on tx-only connection */
7393 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7394 memset(&q_params.params.cfc_del, 0,
7395 sizeof(q_params.params.cfc_del));
7396 q_params.params.cfc_del.cid_index = tx_index;
7397 rc = bnx2x_queue_state_change(bp, &q_params);
7398 if (rc)
7399 return rc;
7400 }
7401 /* Stop the primary connection: */
7402 /* ...halt the connection */
7403 q_params.cmd = BNX2X_Q_CMD_HALT;
7404 rc = bnx2x_queue_state_change(bp, &q_params);
7405 if (rc)
7406 return rc;
7407
7408 /* ...terminate the connection */
7409 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7410 memset(&q_params.params.terminate, 0,
7411 sizeof(q_params.params.terminate));
7412 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7413 rc = bnx2x_queue_state_change(bp, &q_params);
7414 if (rc)
7415 return rc;
7416 /* ...delete cfc entry */
7417 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7418 memset(&q_params.params.cfc_del, 0,
7419 sizeof(q_params.params.cfc_del));
7420 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7421 return bnx2x_queue_state_change(bp, &q_params);
7422 }
7423
7424
7425 static void bnx2x_reset_func(struct bnx2x *bp)
7426 {
7427 int port = BP_PORT(bp);
7428 int func = BP_FUNC(bp);
7429 int i;
7430
7431 /* Disable the function in the FW */
7432 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7433 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7434 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7435 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7436
7437 /* FP SBs */
7438 for_each_eth_queue(bp, i) {
7439 struct bnx2x_fastpath *fp = &bp->fp[i];
7440 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7441 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7442 SB_DISABLED);
7443 }
7444
7445 #ifdef BCM_CNIC
7446 /* CNIC SB */
7447 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7448 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7449 SB_DISABLED);
7450 #endif
7451 /* SP SB */
7452 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7453 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7454 SB_DISABLED);
7455
7456 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7457 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7458 0);
7459
7460 /* Configure IGU */
7461 if (bp->common.int_block == INT_BLOCK_HC) {
7462 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7463 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7464 } else {
7465 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7466 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7467 }
7468
7469 #ifdef BCM_CNIC
7470 /* Disable Timer scan */
7471 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7472 /*
7473 * Wait for at least 10ms and up to 2 second for the timers scan to
7474 * complete
7475 */
7476 for (i = 0; i < 200; i++) {
7477 msleep(10);
7478 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7479 break;
7480 }
7481 #endif
7482 /* Clear ILT */
7483 bnx2x_clear_func_ilt(bp, func);
7484
7485 /* Timers workaround bug for E2: if this is vnic-3,
7486 * we need to set the entire ilt range for this timers.
7487 */
7488 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7489 struct ilt_client_info ilt_cli;
7490 /* use dummy TM client */
7491 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7492 ilt_cli.start = 0;
7493 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7494 ilt_cli.client_num = ILT_CLIENT_TM;
7495
7496 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7497 }
7498
7499 /* this assumes that reset_port() called before reset_func()*/
7500 if (!CHIP_IS_E1x(bp))
7501 bnx2x_pf_disable(bp);
7502
7503 bp->dmae_ready = 0;
7504 }
7505
7506 static void bnx2x_reset_port(struct bnx2x *bp)
7507 {
7508 int port = BP_PORT(bp);
7509 u32 val;
7510
7511 /* Reset physical Link */
7512 bnx2x__link_reset(bp);
7513
7514 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7515
7516 /* Do not rcv packets to BRB */
7517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7518 /* Do not direct rcv packets that are not for MCP to the BRB */
7519 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7520 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7521
7522 /* Configure AEU */
7523 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7524
7525 msleep(100);
7526 /* Check for BRB port occupancy */
7527 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7528 if (val)
7529 DP(NETIF_MSG_IFDOWN,
7530 "BRB1 is not empty %d blocks are occupied\n", val);
7531
7532 /* TODO: Close Doorbell port? */
7533 }
7534
7535 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7536 {
7537 struct bnx2x_func_state_params func_params = {0};
7538
7539 /* Prepare parameters for function state transitions */
7540 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7541
7542 func_params.f_obj = &bp->func_obj;
7543 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7544
7545 func_params.params.hw_init.load_phase = load_code;
7546
7547 return bnx2x_func_state_change(bp, &func_params);
7548 }
7549
7550 static inline int bnx2x_func_stop(struct bnx2x *bp)
7551 {
7552 struct bnx2x_func_state_params func_params = {0};
7553 int rc;
7554
7555 /* Prepare parameters for function state transitions */
7556 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7557 func_params.f_obj = &bp->func_obj;
7558 func_params.cmd = BNX2X_F_CMD_STOP;
7559
7560 /*
7561 * Try to stop the function the 'good way'. If fails (in case
7562 * of a parity error during bnx2x_chip_cleanup()) and we are
7563 * not in a debug mode, perform a state transaction in order to
7564 * enable further HW_RESET transaction.
7565 */
7566 rc = bnx2x_func_state_change(bp, &func_params);
7567 if (rc) {
7568 #ifdef BNX2X_STOP_ON_ERROR
7569 return rc;
7570 #else
7571 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7572 "transaction\n");
7573 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7574 return bnx2x_func_state_change(bp, &func_params);
7575 #endif
7576 }
7577
7578 return 0;
7579 }
7580
7581 /**
7582 * bnx2x_send_unload_req - request unload mode from the MCP.
7583 *
7584 * @bp: driver handle
7585 * @unload_mode: requested function's unload mode
7586 *
7587 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7588 */
7589 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7590 {
7591 u32 reset_code = 0;
7592 int port = BP_PORT(bp);
7593
7594 /* Select the UNLOAD request mode */
7595 if (unload_mode == UNLOAD_NORMAL)
7596 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7597
7598 else if (bp->flags & NO_WOL_FLAG)
7599 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7600
7601 else if (bp->wol) {
7602 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7603 u8 *mac_addr = bp->dev->dev_addr;
7604 u32 val;
7605 u16 pmc;
7606
7607 /* The mac address is written to entries 1-4 to
7608 * preserve entry 0 which is used by the PMF
7609 */
7610 u8 entry = (BP_VN(bp) + 1)*8;
7611
7612 val = (mac_addr[0] << 8) | mac_addr[1];
7613 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7614
7615 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7616 (mac_addr[4] << 8) | mac_addr[5];
7617 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7618
7619 /* Enable the PME and clear the status */
7620 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7621 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7622 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7623
7624 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7625
7626 } else
7627 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7628
7629 /* Send the request to the MCP */
7630 if (!BP_NOMCP(bp))
7631 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7632 else {
7633 int path = BP_PATH(bp);
7634
7635 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7636 "%d, %d, %d\n",
7637 path, load_count[path][0], load_count[path][1],
7638 load_count[path][2]);
7639 load_count[path][0]--;
7640 load_count[path][1 + port]--;
7641 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7642 "%d, %d, %d\n",
7643 path, load_count[path][0], load_count[path][1],
7644 load_count[path][2]);
7645 if (load_count[path][0] == 0)
7646 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7647 else if (load_count[path][1 + port] == 0)
7648 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7649 else
7650 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7651 }
7652
7653 return reset_code;
7654 }
7655
7656 /**
7657 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7658 *
7659 * @bp: driver handle
7660 */
7661 void bnx2x_send_unload_done(struct bnx2x *bp)
7662 {
7663 /* Report UNLOAD_DONE to MCP */
7664 if (!BP_NOMCP(bp))
7665 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7666 }
7667
7668 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7669 {
7670 int tout = 50;
7671 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7672
7673 if (!bp->port.pmf)
7674 return 0;
7675
7676 /*
7677 * (assumption: No Attention from MCP at this stage)
7678 * PMF probably in the middle of TXdisable/enable transaction
7679 * 1. Sync IRS for default SB
7680 * 2. Sync SP queue - this guarantes us that attention handling started
7681 * 3. Wait, that TXdisable/enable transaction completes
7682 *
7683 * 1+2 guranty that if DCBx attention was scheduled it already changed
7684 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7685 * received complettion for the transaction the state is TX_STOPPED.
7686 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7687 * transaction.
7688 */
7689
7690 /* make sure default SB ISR is done */
7691 if (msix)
7692 synchronize_irq(bp->msix_table[0].vector);
7693 else
7694 synchronize_irq(bp->pdev->irq);
7695
7696 flush_workqueue(bnx2x_wq);
7697
7698 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7699 BNX2X_F_STATE_STARTED && tout--)
7700 msleep(20);
7701
7702 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7703 BNX2X_F_STATE_STARTED) {
7704 #ifdef BNX2X_STOP_ON_ERROR
7705 return -EBUSY;
7706 #else
7707 /*
7708 * Failed to complete the transaction in a "good way"
7709 * Force both transactions with CLR bit
7710 */
7711 struct bnx2x_func_state_params func_params = {0};
7712
7713 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7714 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7715
7716 func_params.f_obj = &bp->func_obj;
7717 __set_bit(RAMROD_DRV_CLR_ONLY,
7718 &func_params.ramrod_flags);
7719
7720 /* STARTED-->TX_ST0PPED */
7721 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7722 bnx2x_func_state_change(bp, &func_params);
7723
7724 /* TX_ST0PPED-->STARTED */
7725 func_params.cmd = BNX2X_F_CMD_TX_START;
7726 return bnx2x_func_state_change(bp, &func_params);
7727 #endif
7728 }
7729
7730 return 0;
7731 }
7732
7733 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7734 {
7735 int port = BP_PORT(bp);
7736 int i, rc = 0;
7737 u8 cos;
7738 struct bnx2x_mcast_ramrod_params rparam = {0};
7739 u32 reset_code;
7740
7741 /* Wait until tx fastpath tasks complete */
7742 for_each_tx_queue(bp, i) {
7743 struct bnx2x_fastpath *fp = &bp->fp[i];
7744
7745 for_each_cos_in_tx_queue(fp, cos)
7746 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7747 #ifdef BNX2X_STOP_ON_ERROR
7748 if (rc)
7749 return;
7750 #endif
7751 }
7752
7753 /* Give HW time to discard old tx messages */
7754 usleep_range(1000, 1000);
7755
7756 /* Clean all ETH MACs */
7757 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7758 if (rc < 0)
7759 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7760
7761 /* Clean up UC list */
7762 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7763 true);
7764 if (rc < 0)
7765 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7766 "%d\n", rc);
7767
7768 /* Disable LLH */
7769 if (!CHIP_IS_E1(bp))
7770 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7771
7772 /* Set "drop all" (stop Rx).
7773 * We need to take a netif_addr_lock() here in order to prevent
7774 * a race between the completion code and this code.
7775 */
7776 netif_addr_lock_bh(bp->dev);
7777 /* Schedule the rx_mode command */
7778 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7779 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7780 else
7781 bnx2x_set_storm_rx_mode(bp);
7782
7783 /* Cleanup multicast configuration */
7784 rparam.mcast_obj = &bp->mcast_obj;
7785 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7786 if (rc < 0)
7787 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7788
7789 netif_addr_unlock_bh(bp->dev);
7790
7791
7792
7793 /*
7794 * Send the UNLOAD_REQUEST to the MCP. This will return if
7795 * this function should perform FUNC, PORT or COMMON HW
7796 * reset.
7797 */
7798 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7799
7800 /*
7801 * (assumption: No Attention from MCP at this stage)
7802 * PMF probably in the middle of TXdisable/enable transaction
7803 */
7804 rc = bnx2x_func_wait_started(bp);
7805 if (rc) {
7806 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7807 #ifdef BNX2X_STOP_ON_ERROR
7808 return;
7809 #endif
7810 }
7811
7812 /* Close multi and leading connections
7813 * Completions for ramrods are collected in a synchronous way
7814 */
7815 for_each_queue(bp, i)
7816 if (bnx2x_stop_queue(bp, i))
7817 #ifdef BNX2X_STOP_ON_ERROR
7818 return;
7819 #else
7820 goto unload_error;
7821 #endif
7822 /* If SP settings didn't get completed so far - something
7823 * very wrong has happen.
7824 */
7825 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7826 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7827
7828 #ifndef BNX2X_STOP_ON_ERROR
7829 unload_error:
7830 #endif
7831 rc = bnx2x_func_stop(bp);
7832 if (rc) {
7833 BNX2X_ERR("Function stop failed!\n");
7834 #ifdef BNX2X_STOP_ON_ERROR
7835 return;
7836 #endif
7837 }
7838
7839 /* Disable HW interrupts, NAPI */
7840 bnx2x_netif_stop(bp, 1);
7841
7842 /* Release IRQs */
7843 bnx2x_free_irq(bp);
7844
7845 /* Reset the chip */
7846 rc = bnx2x_reset_hw(bp, reset_code);
7847 if (rc)
7848 BNX2X_ERR("HW_RESET failed\n");
7849
7850
7851 /* Report UNLOAD_DONE to MCP */
7852 bnx2x_send_unload_done(bp);
7853 }
7854
7855 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7856 {
7857 u32 val;
7858
7859 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7860
7861 if (CHIP_IS_E1(bp)) {
7862 int port = BP_PORT(bp);
7863 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7864 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7865
7866 val = REG_RD(bp, addr);
7867 val &= ~(0x300);
7868 REG_WR(bp, addr, val);
7869 } else {
7870 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7871 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7872 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7873 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7874 }
7875 }
7876
7877 /* Close gates #2, #3 and #4: */
7878 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7879 {
7880 u32 val;
7881
7882 /* Gates #2 and #4a are closed/opened for "not E1" only */
7883 if (!CHIP_IS_E1(bp)) {
7884 /* #4 */
7885 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7886 /* #2 */
7887 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7888 }
7889
7890 /* #3 */
7891 if (CHIP_IS_E1x(bp)) {
7892 /* Prevent interrupts from HC on both ports */
7893 val = REG_RD(bp, HC_REG_CONFIG_1);
7894 REG_WR(bp, HC_REG_CONFIG_1,
7895 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7896 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7897
7898 val = REG_RD(bp, HC_REG_CONFIG_0);
7899 REG_WR(bp, HC_REG_CONFIG_0,
7900 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7901 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7902 } else {
7903 /* Prevent incomming interrupts in IGU */
7904 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7905
7906 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7907 (!close) ?
7908 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7909 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7910 }
7911
7912 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7913 close ? "closing" : "opening");
7914 mmiowb();
7915 }
7916
7917 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7918
7919 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7920 {
7921 /* Do some magic... */
7922 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7923 *magic_val = val & SHARED_MF_CLP_MAGIC;
7924 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7925 }
7926
7927 /**
7928 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7929 *
7930 * @bp: driver handle
7931 * @magic_val: old value of the `magic' bit.
7932 */
7933 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7934 {
7935 /* Restore the `magic' bit value... */
7936 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7937 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7938 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7939 }
7940
7941 /**
7942 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7943 *
7944 * @bp: driver handle
7945 * @magic_val: old value of 'magic' bit.
7946 *
7947 * Takes care of CLP configurations.
7948 */
7949 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7950 {
7951 u32 shmem;
7952 u32 validity_offset;
7953
7954 DP(NETIF_MSG_HW, "Starting\n");
7955
7956 /* Set `magic' bit in order to save MF config */
7957 if (!CHIP_IS_E1(bp))
7958 bnx2x_clp_reset_prep(bp, magic_val);
7959
7960 /* Get shmem offset */
7961 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7962 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7963
7964 /* Clear validity map flags */
7965 if (shmem > 0)
7966 REG_WR(bp, shmem + validity_offset, 0);
7967 }
7968
7969 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7970 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7971
7972 /**
7973 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7974 *
7975 * @bp: driver handle
7976 */
7977 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7978 {
7979 /* special handling for emulation and FPGA,
7980 wait 10 times longer */
7981 if (CHIP_REV_IS_SLOW(bp))
7982 msleep(MCP_ONE_TIMEOUT*10);
7983 else
7984 msleep(MCP_ONE_TIMEOUT);
7985 }
7986
7987 /*
7988 * initializes bp->common.shmem_base and waits for validity signature to appear
7989 */
7990 static int bnx2x_init_shmem(struct bnx2x *bp)
7991 {
7992 int cnt = 0;
7993 u32 val = 0;
7994
7995 do {
7996 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7997 if (bp->common.shmem_base) {
7998 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7999 if (val & SHR_MEM_VALIDITY_MB)
8000 return 0;
8001 }
8002
8003 bnx2x_mcp_wait_one(bp);
8004
8005 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8006
8007 BNX2X_ERR("BAD MCP validity signature\n");
8008
8009 return -ENODEV;
8010 }
8011
8012 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8013 {
8014 int rc = bnx2x_init_shmem(bp);
8015
8016 /* Restore the `magic' bit value */
8017 if (!CHIP_IS_E1(bp))
8018 bnx2x_clp_reset_done(bp, magic_val);
8019
8020 return rc;
8021 }
8022
8023 static void bnx2x_pxp_prep(struct bnx2x *bp)
8024 {
8025 if (!CHIP_IS_E1(bp)) {
8026 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8027 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8028 mmiowb();
8029 }
8030 }
8031
8032 /*
8033 * Reset the whole chip except for:
8034 * - PCIE core
8035 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8036 * one reset bit)
8037 * - IGU
8038 * - MISC (including AEU)
8039 * - GRC
8040 * - RBCN, RBCP
8041 */
8042 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8043 {
8044 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8045 u32 global_bits2, stay_reset2;
8046
8047 /*
8048 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8049 * (per chip) blocks.
8050 */
8051 global_bits2 =
8052 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8053 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8054
8055 /* Don't reset the following blocks */
8056 not_reset_mask1 =
8057 MISC_REGISTERS_RESET_REG_1_RST_HC |
8058 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8059 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8060
8061 not_reset_mask2 =
8062 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8063 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8064 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8065 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8066 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8067 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8068 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8069 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8070 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8071 MISC_REGISTERS_RESET_REG_2_PGLC;
8072
8073 /*
8074 * Keep the following blocks in reset:
8075 * - all xxMACs are handled by the bnx2x_link code.
8076 */
8077 stay_reset2 =
8078 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8079 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8080 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8081 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8082 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8083 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8084 MISC_REGISTERS_RESET_REG_2_XMAC |
8085 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8086
8087 /* Full reset masks according to the chip */
8088 reset_mask1 = 0xffffffff;
8089
8090 if (CHIP_IS_E1(bp))
8091 reset_mask2 = 0xffff;
8092 else if (CHIP_IS_E1H(bp))
8093 reset_mask2 = 0x1ffff;
8094 else if (CHIP_IS_E2(bp))
8095 reset_mask2 = 0xfffff;
8096 else /* CHIP_IS_E3 */
8097 reset_mask2 = 0x3ffffff;
8098
8099 /* Don't reset global blocks unless we need to */
8100 if (!global)
8101 reset_mask2 &= ~global_bits2;
8102
8103 /*
8104 * In case of attention in the QM, we need to reset PXP
8105 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8106 * because otherwise QM reset would release 'close the gates' shortly
8107 * before resetting the PXP, then the PSWRQ would send a write
8108 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8109 * read the payload data from PSWWR, but PSWWR would not
8110 * respond. The write queue in PGLUE would stuck, dmae commands
8111 * would not return. Therefore it's important to reset the second
8112 * reset register (containing the
8113 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8114 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8115 * bit).
8116 */
8117 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8118 reset_mask2 & (~not_reset_mask2));
8119
8120 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8121 reset_mask1 & (~not_reset_mask1));
8122
8123 barrier();
8124 mmiowb();
8125
8126 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8127 reset_mask2 & (~stay_reset2));
8128
8129 barrier();
8130 mmiowb();
8131
8132 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8133 mmiowb();
8134 }
8135
8136 /**
8137 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8138 * It should get cleared in no more than 1s.
8139 *
8140 * @bp: driver handle
8141 *
8142 * It should get cleared in no more than 1s. Returns 0 if
8143 * pending writes bit gets cleared.
8144 */
8145 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8146 {
8147 u32 cnt = 1000;
8148 u32 pend_bits = 0;
8149
8150 do {
8151 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8152
8153 if (pend_bits == 0)
8154 break;
8155
8156 usleep_range(1000, 1000);
8157 } while (cnt-- > 0);
8158
8159 if (cnt <= 0) {
8160 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8161 pend_bits);
8162 return -EBUSY;
8163 }
8164
8165 return 0;
8166 }
8167
8168 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8169 {
8170 int cnt = 1000;
8171 u32 val = 0;
8172 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8173
8174
8175 /* Empty the Tetris buffer, wait for 1s */
8176 do {
8177 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8178 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8179 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8180 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8181 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8182 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8183 ((port_is_idle_0 & 0x1) == 0x1) &&
8184 ((port_is_idle_1 & 0x1) == 0x1) &&
8185 (pgl_exp_rom2 == 0xffffffff))
8186 break;
8187 usleep_range(1000, 1000);
8188 } while (cnt-- > 0);
8189
8190 if (cnt <= 0) {
8191 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8192 " are still"
8193 " outstanding read requests after 1s!\n");
8194 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8195 " port_is_idle_0=0x%08x,"
8196 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8197 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8198 pgl_exp_rom2);
8199 return -EAGAIN;
8200 }
8201
8202 barrier();
8203
8204 /* Close gates #2, #3 and #4 */
8205 bnx2x_set_234_gates(bp, true);
8206
8207 /* Poll for IGU VQs for 57712 and newer chips */
8208 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8209 return -EAGAIN;
8210
8211
8212 /* TBD: Indicate that "process kill" is in progress to MCP */
8213
8214 /* Clear "unprepared" bit */
8215 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8216 barrier();
8217
8218 /* Make sure all is written to the chip before the reset */
8219 mmiowb();
8220
8221 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8222 * PSWHST, GRC and PSWRD Tetris buffer.
8223 */
8224 usleep_range(1000, 1000);
8225
8226 /* Prepare to chip reset: */
8227 /* MCP */
8228 if (global)
8229 bnx2x_reset_mcp_prep(bp, &val);
8230
8231 /* PXP */
8232 bnx2x_pxp_prep(bp);
8233 barrier();
8234
8235 /* reset the chip */
8236 bnx2x_process_kill_chip_reset(bp, global);
8237 barrier();
8238
8239 /* Recover after reset: */
8240 /* MCP */
8241 if (global && bnx2x_reset_mcp_comp(bp, val))
8242 return -EAGAIN;
8243
8244 /* TBD: Add resetting the NO_MCP mode DB here */
8245
8246 /* PXP */
8247 bnx2x_pxp_prep(bp);
8248
8249 /* Open the gates #2, #3 and #4 */
8250 bnx2x_set_234_gates(bp, false);
8251
8252 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8253 * reset state, re-enable attentions. */
8254
8255 return 0;
8256 }
8257
8258 int bnx2x_leader_reset(struct bnx2x *bp)
8259 {
8260 int rc = 0;
8261 bool global = bnx2x_reset_is_global(bp);
8262
8263 /* Try to recover after the failure */
8264 if (bnx2x_process_kill(bp, global)) {
8265 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8266 "Aii!\n", BP_PATH(bp));
8267 rc = -EAGAIN;
8268 goto exit_leader_reset;
8269 }
8270
8271 /*
8272 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8273 * state.
8274 */
8275 bnx2x_set_reset_done(bp);
8276 if (global)
8277 bnx2x_clear_reset_global(bp);
8278
8279 exit_leader_reset:
8280 bp->is_leader = 0;
8281 bnx2x_release_leader_lock(bp);
8282 smp_mb();
8283 return rc;
8284 }
8285
8286 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8287 {
8288 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8289
8290 /* Disconnect this device */
8291 netif_device_detach(bp->dev);
8292
8293 /*
8294 * Block ifup for all function on this engine until "process kill"
8295 * or power cycle.
8296 */
8297 bnx2x_set_reset_in_progress(bp);
8298
8299 /* Shut down the power */
8300 bnx2x_set_power_state(bp, PCI_D3hot);
8301
8302 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8303
8304 smp_mb();
8305 }
8306
8307 /*
8308 * Assumption: runs under rtnl lock. This together with the fact
8309 * that it's called only from bnx2x_sp_rtnl() ensure that it
8310 * will never be called when netif_running(bp->dev) is false.
8311 */
8312 static void bnx2x_parity_recover(struct bnx2x *bp)
8313 {
8314 bool global = false;
8315
8316 DP(NETIF_MSG_HW, "Handling parity\n");
8317 while (1) {
8318 switch (bp->recovery_state) {
8319 case BNX2X_RECOVERY_INIT:
8320 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8321 bnx2x_chk_parity_attn(bp, &global, false);
8322
8323 /* Try to get a LEADER_LOCK HW lock */
8324 if (bnx2x_trylock_leader_lock(bp)) {
8325 bnx2x_set_reset_in_progress(bp);
8326 /*
8327 * Check if there is a global attention and if
8328 * there was a global attention, set the global
8329 * reset bit.
8330 */
8331
8332 if (global)
8333 bnx2x_set_reset_global(bp);
8334
8335 bp->is_leader = 1;
8336 }
8337
8338 /* Stop the driver */
8339 /* If interface has been removed - break */
8340 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8341 return;
8342
8343 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8344
8345 /*
8346 * Reset MCP command sequence number and MCP mail box
8347 * sequence as we are going to reset the MCP.
8348 */
8349 if (global) {
8350 bp->fw_seq = 0;
8351 bp->fw_drv_pulse_wr_seq = 0;
8352 }
8353
8354 /* Ensure "is_leader", MCP command sequence and
8355 * "recovery_state" update values are seen on other
8356 * CPUs.
8357 */
8358 smp_mb();
8359 break;
8360
8361 case BNX2X_RECOVERY_WAIT:
8362 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8363 if (bp->is_leader) {
8364 int other_engine = BP_PATH(bp) ? 0 : 1;
8365 u32 other_load_counter =
8366 bnx2x_get_load_cnt(bp, other_engine);
8367 u32 load_counter =
8368 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8369 global = bnx2x_reset_is_global(bp);
8370
8371 /*
8372 * In case of a parity in a global block, let
8373 * the first leader that performs a
8374 * leader_reset() reset the global blocks in
8375 * order to clear global attentions. Otherwise
8376 * the the gates will remain closed for that
8377 * engine.
8378 */
8379 if (load_counter ||
8380 (global && other_load_counter)) {
8381 /* Wait until all other functions get
8382 * down.
8383 */
8384 schedule_delayed_work(&bp->sp_rtnl_task,
8385 HZ/10);
8386 return;
8387 } else {
8388 /* If all other functions got down -
8389 * try to bring the chip back to
8390 * normal. In any case it's an exit
8391 * point for a leader.
8392 */
8393 if (bnx2x_leader_reset(bp)) {
8394 bnx2x_recovery_failed(bp);
8395 return;
8396 }
8397
8398 /* If we are here, means that the
8399 * leader has succeeded and doesn't
8400 * want to be a leader any more. Try
8401 * to continue as a none-leader.
8402 */
8403 break;
8404 }
8405 } else { /* non-leader */
8406 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8407 /* Try to get a LEADER_LOCK HW lock as
8408 * long as a former leader may have
8409 * been unloaded by the user or
8410 * released a leadership by another
8411 * reason.
8412 */
8413 if (bnx2x_trylock_leader_lock(bp)) {
8414 /* I'm a leader now! Restart a
8415 * switch case.
8416 */
8417 bp->is_leader = 1;
8418 break;
8419 }
8420
8421 schedule_delayed_work(&bp->sp_rtnl_task,
8422 HZ/10);
8423 return;
8424
8425 } else {
8426 /*
8427 * If there was a global attention, wait
8428 * for it to be cleared.
8429 */
8430 if (bnx2x_reset_is_global(bp)) {
8431 schedule_delayed_work(
8432 &bp->sp_rtnl_task,
8433 HZ/10);
8434 return;
8435 }
8436
8437 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8438 bnx2x_recovery_failed(bp);
8439 else {
8440 bp->recovery_state =
8441 BNX2X_RECOVERY_DONE;
8442 smp_mb();
8443 }
8444
8445 return;
8446 }
8447 }
8448 default:
8449 return;
8450 }
8451 }
8452 }
8453
8454 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8455 * scheduled on a general queue in order to prevent a dead lock.
8456 */
8457 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8458 {
8459 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8460
8461 rtnl_lock();
8462
8463 if (!netif_running(bp->dev))
8464 goto sp_rtnl_exit;
8465
8466 /* if stop on error is defined no recovery flows should be executed */
8467 #ifdef BNX2X_STOP_ON_ERROR
8468 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8469 "so reset not done to allow debug dump,\n"
8470 "you will need to reboot when done\n");
8471 goto sp_rtnl_not_reset;
8472 #endif
8473
8474 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8475 /*
8476 * Clear all pending SP commands as we are going to reset the
8477 * function anyway.
8478 */
8479 bp->sp_rtnl_state = 0;
8480 smp_mb();
8481
8482 bnx2x_parity_recover(bp);
8483
8484 goto sp_rtnl_exit;
8485 }
8486
8487 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8488 /*
8489 * Clear all pending SP commands as we are going to reset the
8490 * function anyway.
8491 */
8492 bp->sp_rtnl_state = 0;
8493 smp_mb();
8494
8495 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8496 bnx2x_nic_load(bp, LOAD_NORMAL);
8497
8498 goto sp_rtnl_exit;
8499 }
8500 #ifdef BNX2X_STOP_ON_ERROR
8501 sp_rtnl_not_reset:
8502 #endif
8503 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8504 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8505
8506 sp_rtnl_exit:
8507 rtnl_unlock();
8508 }
8509
8510 /* end of nic load/unload */
8511
8512 static void bnx2x_period_task(struct work_struct *work)
8513 {
8514 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8515
8516 if (!netif_running(bp->dev))
8517 goto period_task_exit;
8518
8519 if (CHIP_REV_IS_SLOW(bp)) {
8520 BNX2X_ERR("period task called on emulation, ignoring\n");
8521 goto period_task_exit;
8522 }
8523
8524 bnx2x_acquire_phy_lock(bp);
8525 /*
8526 * The barrier is needed to ensure the ordering between the writing to
8527 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8528 * the reading here.
8529 */
8530 smp_mb();
8531 if (bp->port.pmf) {
8532 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8533
8534 /* Re-queue task in 1 sec */
8535 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8536 }
8537
8538 bnx2x_release_phy_lock(bp);
8539 period_task_exit:
8540 return;
8541 }
8542
8543 /*
8544 * Init service functions
8545 */
8546
8547 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8548 {
8549 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8550 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8551 return base + (BP_ABS_FUNC(bp)) * stride;
8552 }
8553
8554 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8555 {
8556 u32 reg = bnx2x_get_pretend_reg(bp);
8557
8558 /* Flush all outstanding writes */
8559 mmiowb();
8560
8561 /* Pretend to be function 0 */
8562 REG_WR(bp, reg, 0);
8563 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8564
8565 /* From now we are in the "like-E1" mode */
8566 bnx2x_int_disable(bp);
8567
8568 /* Flush all outstanding writes */
8569 mmiowb();
8570
8571 /* Restore the original function */
8572 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8573 REG_RD(bp, reg);
8574 }
8575
8576 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8577 {
8578 if (CHIP_IS_E1(bp))
8579 bnx2x_int_disable(bp);
8580 else
8581 bnx2x_undi_int_disable_e1h(bp);
8582 }
8583
8584 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8585 {
8586 u32 val;
8587
8588 /* Check if there is any driver already loaded */
8589 val = REG_RD(bp, MISC_REG_UNPREPARED);
8590 if (val == 0x1) {
8591
8592 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8593 /*
8594 * Check if it is the UNDI driver
8595 * UNDI driver initializes CID offset for normal bell to 0x7
8596 */
8597 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8598 if (val == 0x7) {
8599 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8600 /* save our pf_num */
8601 int orig_pf_num = bp->pf_num;
8602 int port;
8603 u32 swap_en, swap_val, value;
8604
8605 /* clear the UNDI indication */
8606 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8607
8608 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8609
8610 /* try unload UNDI on port 0 */
8611 bp->pf_num = 0;
8612 bp->fw_seq =
8613 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8614 DRV_MSG_SEQ_NUMBER_MASK);
8615 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8616
8617 /* if UNDI is loaded on the other port */
8618 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8619
8620 /* send "DONE" for previous unload */
8621 bnx2x_fw_command(bp,
8622 DRV_MSG_CODE_UNLOAD_DONE, 0);
8623
8624 /* unload UNDI on port 1 */
8625 bp->pf_num = 1;
8626 bp->fw_seq =
8627 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8628 DRV_MSG_SEQ_NUMBER_MASK);
8629 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8630
8631 bnx2x_fw_command(bp, reset_code, 0);
8632 }
8633
8634 bnx2x_undi_int_disable(bp);
8635 port = BP_PORT(bp);
8636
8637 /* close input traffic and wait for it */
8638 /* Do not rcv packets to BRB */
8639 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8640 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8641 /* Do not direct rcv packets that are not for MCP to
8642 * the BRB */
8643 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8644 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8645 /* clear AEU */
8646 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8647 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8648 msleep(10);
8649
8650 /* save NIG port swap info */
8651 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8652 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8653 /* reset device */
8654 REG_WR(bp,
8655 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8656 0xd3ffffff);
8657
8658 value = 0x1400;
8659 if (CHIP_IS_E3(bp)) {
8660 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8661 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8662 }
8663
8664 REG_WR(bp,
8665 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8666 value);
8667
8668 /* take the NIG out of reset and restore swap values */
8669 REG_WR(bp,
8670 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8671 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8672 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8673 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8674
8675 /* send unload done to the MCP */
8676 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8677
8678 /* restore our func and fw_seq */
8679 bp->pf_num = orig_pf_num;
8680 bp->fw_seq =
8681 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8682 DRV_MSG_SEQ_NUMBER_MASK);
8683 }
8684
8685 /* now it's safe to release the lock */
8686 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8687 }
8688 }
8689
8690 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8691 {
8692 u32 val, val2, val3, val4, id;
8693 u16 pmc;
8694
8695 /* Get the chip revision id and number. */
8696 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8697 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8698 id = ((val & 0xffff) << 16);
8699 val = REG_RD(bp, MISC_REG_CHIP_REV);
8700 id |= ((val & 0xf) << 12);
8701 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8702 id |= ((val & 0xff) << 4);
8703 val = REG_RD(bp, MISC_REG_BOND_ID);
8704 id |= (val & 0xf);
8705 bp->common.chip_id = id;
8706
8707 /* Set doorbell size */
8708 bp->db_size = (1 << BNX2X_DB_SHIFT);
8709
8710 if (!CHIP_IS_E1x(bp)) {
8711 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8712 if ((val & 1) == 0)
8713 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8714 else
8715 val = (val >> 1) & 1;
8716 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8717 "2_PORT_MODE");
8718 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8719 CHIP_2_PORT_MODE;
8720
8721 if (CHIP_MODE_IS_4_PORT(bp))
8722 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8723 else
8724 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8725 } else {
8726 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8727 bp->pfid = bp->pf_num; /* 0..7 */
8728 }
8729
8730 bp->link_params.chip_id = bp->common.chip_id;
8731 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8732
8733 val = (REG_RD(bp, 0x2874) & 0x55);
8734 if ((bp->common.chip_id & 0x1) ||
8735 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8736 bp->flags |= ONE_PORT_FLAG;
8737 BNX2X_DEV_INFO("single port device\n");
8738 }
8739
8740 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8741 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8742 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8743 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8744 bp->common.flash_size, bp->common.flash_size);
8745
8746 bnx2x_init_shmem(bp);
8747
8748
8749
8750 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8751 MISC_REG_GENERIC_CR_1 :
8752 MISC_REG_GENERIC_CR_0));
8753
8754 bp->link_params.shmem_base = bp->common.shmem_base;
8755 bp->link_params.shmem2_base = bp->common.shmem2_base;
8756 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8757 bp->common.shmem_base, bp->common.shmem2_base);
8758
8759 if (!bp->common.shmem_base) {
8760 BNX2X_DEV_INFO("MCP not active\n");
8761 bp->flags |= NO_MCP_FLAG;
8762 return;
8763 }
8764
8765 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8766 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8767
8768 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8769 SHARED_HW_CFG_LED_MODE_MASK) >>
8770 SHARED_HW_CFG_LED_MODE_SHIFT);
8771
8772 bp->link_params.feature_config_flags = 0;
8773 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8774 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8775 bp->link_params.feature_config_flags |=
8776 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8777 else
8778 bp->link_params.feature_config_flags &=
8779 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8780
8781 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8782 bp->common.bc_ver = val;
8783 BNX2X_DEV_INFO("bc_ver %X\n", val);
8784 if (val < BNX2X_BC_VER) {
8785 /* for now only warn
8786 * later we might need to enforce this */
8787 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8788 "please upgrade BC\n", BNX2X_BC_VER, val);
8789 }
8790 bp->link_params.feature_config_flags |=
8791 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8792 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8793
8794 bp->link_params.feature_config_flags |=
8795 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8796 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8797
8798 bp->link_params.feature_config_flags |=
8799 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8800 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8801
8802 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8803 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8804
8805 BNX2X_DEV_INFO("%sWoL capable\n",
8806 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8807
8808 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8809 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8810 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8811 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8812
8813 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8814 val, val2, val3, val4);
8815 }
8816
8817 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8818 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8819
8820 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8821 {
8822 int pfid = BP_FUNC(bp);
8823 int igu_sb_id;
8824 u32 val;
8825 u8 fid, igu_sb_cnt = 0;
8826
8827 bp->igu_base_sb = 0xff;
8828 if (CHIP_INT_MODE_IS_BC(bp)) {
8829 int vn = BP_VN(bp);
8830 igu_sb_cnt = bp->igu_sb_cnt;
8831 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8832 FP_SB_MAX_E1x;
8833
8834 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8835 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8836
8837 return;
8838 }
8839
8840 /* IGU in normal mode - read CAM */
8841 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8842 igu_sb_id++) {
8843 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8844 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8845 continue;
8846 fid = IGU_FID(val);
8847 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8848 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8849 continue;
8850 if (IGU_VEC(val) == 0)
8851 /* default status block */
8852 bp->igu_dsb_id = igu_sb_id;
8853 else {
8854 if (bp->igu_base_sb == 0xff)
8855 bp->igu_base_sb = igu_sb_id;
8856 igu_sb_cnt++;
8857 }
8858 }
8859 }
8860
8861 #ifdef CONFIG_PCI_MSI
8862 /*
8863 * It's expected that number of CAM entries for this functions is equal
8864 * to the number evaluated based on the MSI-X table size. We want a
8865 * harsh warning if these values are different!
8866 */
8867 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8868 #endif
8869
8870 if (igu_sb_cnt == 0)
8871 BNX2X_ERR("CAM configuration error\n");
8872 }
8873
8874 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8875 u32 switch_cfg)
8876 {
8877 int cfg_size = 0, idx, port = BP_PORT(bp);
8878
8879 /* Aggregation of supported attributes of all external phys */
8880 bp->port.supported[0] = 0;
8881 bp->port.supported[1] = 0;
8882 switch (bp->link_params.num_phys) {
8883 case 1:
8884 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8885 cfg_size = 1;
8886 break;
8887 case 2:
8888 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8889 cfg_size = 1;
8890 break;
8891 case 3:
8892 if (bp->link_params.multi_phy_config &
8893 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8894 bp->port.supported[1] =
8895 bp->link_params.phy[EXT_PHY1].supported;
8896 bp->port.supported[0] =
8897 bp->link_params.phy[EXT_PHY2].supported;
8898 } else {
8899 bp->port.supported[0] =
8900 bp->link_params.phy[EXT_PHY1].supported;
8901 bp->port.supported[1] =
8902 bp->link_params.phy[EXT_PHY2].supported;
8903 }
8904 cfg_size = 2;
8905 break;
8906 }
8907
8908 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8909 BNX2X_ERR("NVRAM config error. BAD phy config."
8910 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8911 SHMEM_RD(bp,
8912 dev_info.port_hw_config[port].external_phy_config),
8913 SHMEM_RD(bp,
8914 dev_info.port_hw_config[port].external_phy_config2));
8915 return;
8916 }
8917
8918 if (CHIP_IS_E3(bp))
8919 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8920 else {
8921 switch (switch_cfg) {
8922 case SWITCH_CFG_1G:
8923 bp->port.phy_addr = REG_RD(
8924 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8925 break;
8926 case SWITCH_CFG_10G:
8927 bp->port.phy_addr = REG_RD(
8928 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8929 break;
8930 default:
8931 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8932 bp->port.link_config[0]);
8933 return;
8934 }
8935 }
8936 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8937 /* mask what we support according to speed_cap_mask per configuration */
8938 for (idx = 0; idx < cfg_size; idx++) {
8939 if (!(bp->link_params.speed_cap_mask[idx] &
8940 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8941 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8942
8943 if (!(bp->link_params.speed_cap_mask[idx] &
8944 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8945 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8946
8947 if (!(bp->link_params.speed_cap_mask[idx] &
8948 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8949 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8950
8951 if (!(bp->link_params.speed_cap_mask[idx] &
8952 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8953 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8954
8955 if (!(bp->link_params.speed_cap_mask[idx] &
8956 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8957 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8958 SUPPORTED_1000baseT_Full);
8959
8960 if (!(bp->link_params.speed_cap_mask[idx] &
8961 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8962 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8963
8964 if (!(bp->link_params.speed_cap_mask[idx] &
8965 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8966 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8967
8968 }
8969
8970 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8971 bp->port.supported[1]);
8972 }
8973
8974 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8975 {
8976 u32 link_config, idx, cfg_size = 0;
8977 bp->port.advertising[0] = 0;
8978 bp->port.advertising[1] = 0;
8979 switch (bp->link_params.num_phys) {
8980 case 1:
8981 case 2:
8982 cfg_size = 1;
8983 break;
8984 case 3:
8985 cfg_size = 2;
8986 break;
8987 }
8988 for (idx = 0; idx < cfg_size; idx++) {
8989 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8990 link_config = bp->port.link_config[idx];
8991 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8992 case PORT_FEATURE_LINK_SPEED_AUTO:
8993 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8994 bp->link_params.req_line_speed[idx] =
8995 SPEED_AUTO_NEG;
8996 bp->port.advertising[idx] |=
8997 bp->port.supported[idx];
8998 } else {
8999 /* force 10G, no AN */
9000 bp->link_params.req_line_speed[idx] =
9001 SPEED_10000;
9002 bp->port.advertising[idx] |=
9003 (ADVERTISED_10000baseT_Full |
9004 ADVERTISED_FIBRE);
9005 continue;
9006 }
9007 break;
9008
9009 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9010 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9011 bp->link_params.req_line_speed[idx] =
9012 SPEED_10;
9013 bp->port.advertising[idx] |=
9014 (ADVERTISED_10baseT_Full |
9015 ADVERTISED_TP);
9016 } else {
9017 BNX2X_ERR("NVRAM config error. "
9018 "Invalid link_config 0x%x"
9019 " speed_cap_mask 0x%x\n",
9020 link_config,
9021 bp->link_params.speed_cap_mask[idx]);
9022 return;
9023 }
9024 break;
9025
9026 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9027 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9028 bp->link_params.req_line_speed[idx] =
9029 SPEED_10;
9030 bp->link_params.req_duplex[idx] =
9031 DUPLEX_HALF;
9032 bp->port.advertising[idx] |=
9033 (ADVERTISED_10baseT_Half |
9034 ADVERTISED_TP);
9035 } else {
9036 BNX2X_ERR("NVRAM config error. "
9037 "Invalid link_config 0x%x"
9038 " speed_cap_mask 0x%x\n",
9039 link_config,
9040 bp->link_params.speed_cap_mask[idx]);
9041 return;
9042 }
9043 break;
9044
9045 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9046 if (bp->port.supported[idx] &
9047 SUPPORTED_100baseT_Full) {
9048 bp->link_params.req_line_speed[idx] =
9049 SPEED_100;
9050 bp->port.advertising[idx] |=
9051 (ADVERTISED_100baseT_Full |
9052 ADVERTISED_TP);
9053 } else {
9054 BNX2X_ERR("NVRAM config error. "
9055 "Invalid link_config 0x%x"
9056 " speed_cap_mask 0x%x\n",
9057 link_config,
9058 bp->link_params.speed_cap_mask[idx]);
9059 return;
9060 }
9061 break;
9062
9063 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9064 if (bp->port.supported[idx] &
9065 SUPPORTED_100baseT_Half) {
9066 bp->link_params.req_line_speed[idx] =
9067 SPEED_100;
9068 bp->link_params.req_duplex[idx] =
9069 DUPLEX_HALF;
9070 bp->port.advertising[idx] |=
9071 (ADVERTISED_100baseT_Half |
9072 ADVERTISED_TP);
9073 } else {
9074 BNX2X_ERR("NVRAM config error. "
9075 "Invalid link_config 0x%x"
9076 " speed_cap_mask 0x%x\n",
9077 link_config,
9078 bp->link_params.speed_cap_mask[idx]);
9079 return;
9080 }
9081 break;
9082
9083 case PORT_FEATURE_LINK_SPEED_1G:
9084 if (bp->port.supported[idx] &
9085 SUPPORTED_1000baseT_Full) {
9086 bp->link_params.req_line_speed[idx] =
9087 SPEED_1000;
9088 bp->port.advertising[idx] |=
9089 (ADVERTISED_1000baseT_Full |
9090 ADVERTISED_TP);
9091 } else {
9092 BNX2X_ERR("NVRAM config error. "
9093 "Invalid link_config 0x%x"
9094 " speed_cap_mask 0x%x\n",
9095 link_config,
9096 bp->link_params.speed_cap_mask[idx]);
9097 return;
9098 }
9099 break;
9100
9101 case PORT_FEATURE_LINK_SPEED_2_5G:
9102 if (bp->port.supported[idx] &
9103 SUPPORTED_2500baseX_Full) {
9104 bp->link_params.req_line_speed[idx] =
9105 SPEED_2500;
9106 bp->port.advertising[idx] |=
9107 (ADVERTISED_2500baseX_Full |
9108 ADVERTISED_TP);
9109 } else {
9110 BNX2X_ERR("NVRAM config error. "
9111 "Invalid link_config 0x%x"
9112 " speed_cap_mask 0x%x\n",
9113 link_config,
9114 bp->link_params.speed_cap_mask[idx]);
9115 return;
9116 }
9117 break;
9118
9119 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9120 if (bp->port.supported[idx] &
9121 SUPPORTED_10000baseT_Full) {
9122 bp->link_params.req_line_speed[idx] =
9123 SPEED_10000;
9124 bp->port.advertising[idx] |=
9125 (ADVERTISED_10000baseT_Full |
9126 ADVERTISED_FIBRE);
9127 } else {
9128 BNX2X_ERR("NVRAM config error. "
9129 "Invalid link_config 0x%x"
9130 " speed_cap_mask 0x%x\n",
9131 link_config,
9132 bp->link_params.speed_cap_mask[idx]);
9133 return;
9134 }
9135 break;
9136 case PORT_FEATURE_LINK_SPEED_20G:
9137 bp->link_params.req_line_speed[idx] = SPEED_20000;
9138
9139 break;
9140 default:
9141 BNX2X_ERR("NVRAM config error. "
9142 "BAD link speed link_config 0x%x\n",
9143 link_config);
9144 bp->link_params.req_line_speed[idx] =
9145 SPEED_AUTO_NEG;
9146 bp->port.advertising[idx] =
9147 bp->port.supported[idx];
9148 break;
9149 }
9150
9151 bp->link_params.req_flow_ctrl[idx] = (link_config &
9152 PORT_FEATURE_FLOW_CONTROL_MASK);
9153 if ((bp->link_params.req_flow_ctrl[idx] ==
9154 BNX2X_FLOW_CTRL_AUTO) &&
9155 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9156 bp->link_params.req_flow_ctrl[idx] =
9157 BNX2X_FLOW_CTRL_NONE;
9158 }
9159
9160 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9161 " 0x%x advertising 0x%x\n",
9162 bp->link_params.req_line_speed[idx],
9163 bp->link_params.req_duplex[idx],
9164 bp->link_params.req_flow_ctrl[idx],
9165 bp->port.advertising[idx]);
9166 }
9167 }
9168
9169 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9170 {
9171 mac_hi = cpu_to_be16(mac_hi);
9172 mac_lo = cpu_to_be32(mac_lo);
9173 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9174 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9175 }
9176
9177 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9178 {
9179 int port = BP_PORT(bp);
9180 u32 config;
9181 u32 ext_phy_type, ext_phy_config;
9182
9183 bp->link_params.bp = bp;
9184 bp->link_params.port = port;
9185
9186 bp->link_params.lane_config =
9187 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9188
9189 bp->link_params.speed_cap_mask[0] =
9190 SHMEM_RD(bp,
9191 dev_info.port_hw_config[port].speed_capability_mask);
9192 bp->link_params.speed_cap_mask[1] =
9193 SHMEM_RD(bp,
9194 dev_info.port_hw_config[port].speed_capability_mask2);
9195 bp->port.link_config[0] =
9196 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9197
9198 bp->port.link_config[1] =
9199 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9200
9201 bp->link_params.multi_phy_config =
9202 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9203 /* If the device is capable of WoL, set the default state according
9204 * to the HW
9205 */
9206 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9207 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9208 (config & PORT_FEATURE_WOL_ENABLED));
9209
9210 BNX2X_DEV_INFO("lane_config 0x%08x "
9211 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9212 bp->link_params.lane_config,
9213 bp->link_params.speed_cap_mask[0],
9214 bp->port.link_config[0]);
9215
9216 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9217 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9218 bnx2x_phy_probe(&bp->link_params);
9219 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9220
9221 bnx2x_link_settings_requested(bp);
9222
9223 /*
9224 * If connected directly, work with the internal PHY, otherwise, work
9225 * with the external PHY
9226 */
9227 ext_phy_config =
9228 SHMEM_RD(bp,
9229 dev_info.port_hw_config[port].external_phy_config);
9230 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9231 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9232 bp->mdio.prtad = bp->port.phy_addr;
9233
9234 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9235 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9236 bp->mdio.prtad =
9237 XGXS_EXT_PHY_ADDR(ext_phy_config);
9238
9239 /*
9240 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9241 * In MF mode, it is set to cover self test cases
9242 */
9243 if (IS_MF(bp))
9244 bp->port.need_hw_lock = 1;
9245 else
9246 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9247 bp->common.shmem_base,
9248 bp->common.shmem2_base);
9249 }
9250
9251 #ifdef BCM_CNIC
9252 void bnx2x_get_iscsi_info(struct bnx2x *bp)
9253 {
9254 int port = BP_PORT(bp);
9255
9256 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9257 drv_lic_key[port].max_iscsi_conn);
9258
9259 /* Get the number of maximum allowed iSCSI connections */
9260 bp->cnic_eth_dev.max_iscsi_conn =
9261 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9262 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9263
9264 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9265 bp->cnic_eth_dev.max_iscsi_conn);
9266
9267 /*
9268 * If maximum allowed number of connections is zero -
9269 * disable the feature.
9270 */
9271 if (!bp->cnic_eth_dev.max_iscsi_conn)
9272 bp->flags |= NO_ISCSI_FLAG;
9273 }
9274
9275 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9276 {
9277 int port = BP_PORT(bp);
9278 int func = BP_ABS_FUNC(bp);
9279
9280 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9281 drv_lic_key[port].max_fcoe_conn);
9282
9283 /* Get the number of maximum allowed FCoE connections */
9284 bp->cnic_eth_dev.max_fcoe_conn =
9285 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9286 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9287
9288 /* Read the WWN: */
9289 if (!IS_MF(bp)) {
9290 /* Port info */
9291 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9292 SHMEM_RD(bp,
9293 dev_info.port_hw_config[port].
9294 fcoe_wwn_port_name_upper);
9295 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9296 SHMEM_RD(bp,
9297 dev_info.port_hw_config[port].
9298 fcoe_wwn_port_name_lower);
9299
9300 /* Node info */
9301 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9302 SHMEM_RD(bp,
9303 dev_info.port_hw_config[port].
9304 fcoe_wwn_node_name_upper);
9305 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9306 SHMEM_RD(bp,
9307 dev_info.port_hw_config[port].
9308 fcoe_wwn_node_name_lower);
9309 } else if (!IS_MF_SD(bp)) {
9310 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9311
9312 /*
9313 * Read the WWN info only if the FCoE feature is enabled for
9314 * this function.
9315 */
9316 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9317 /* Port info */
9318 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9319 MF_CFG_RD(bp, func_ext_config[func].
9320 fcoe_wwn_port_name_upper);
9321 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9322 MF_CFG_RD(bp, func_ext_config[func].
9323 fcoe_wwn_port_name_lower);
9324
9325 /* Node info */
9326 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9327 MF_CFG_RD(bp, func_ext_config[func].
9328 fcoe_wwn_node_name_upper);
9329 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9330 MF_CFG_RD(bp, func_ext_config[func].
9331 fcoe_wwn_node_name_lower);
9332 }
9333 }
9334
9335 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
9336
9337 /*
9338 * If maximum allowed number of connections is zero -
9339 * disable the feature.
9340 */
9341 if (!bp->cnic_eth_dev.max_fcoe_conn)
9342 bp->flags |= NO_FCOE_FLAG;
9343 }
9344
9345 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9346 {
9347 /*
9348 * iSCSI may be dynamically disabled but reading
9349 * info here we will decrease memory usage by driver
9350 * if the feature is disabled for good
9351 */
9352 bnx2x_get_iscsi_info(bp);
9353 bnx2x_get_fcoe_info(bp);
9354 }
9355 #endif
9356
9357 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9358 {
9359 u32 val, val2;
9360 int func = BP_ABS_FUNC(bp);
9361 int port = BP_PORT(bp);
9362 #ifdef BCM_CNIC
9363 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9364 u8 *fip_mac = bp->fip_mac;
9365 #endif
9366
9367 /* Zero primary MAC configuration */
9368 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9369
9370 if (BP_NOMCP(bp)) {
9371 BNX2X_ERROR("warning: random MAC workaround active\n");
9372 random_ether_addr(bp->dev->dev_addr);
9373 } else if (IS_MF(bp)) {
9374 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9375 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9376 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9377 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9378 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9379
9380 #ifdef BCM_CNIC
9381 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9382 * FCoE MAC then the appropriate feature should be disabled.
9383 */
9384 if (IS_MF_SI(bp)) {
9385 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9386 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9387 val2 = MF_CFG_RD(bp, func_ext_config[func].
9388 iscsi_mac_addr_upper);
9389 val = MF_CFG_RD(bp, func_ext_config[func].
9390 iscsi_mac_addr_lower);
9391 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9392 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9393 iscsi_mac);
9394 } else
9395 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9396
9397 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9398 val2 = MF_CFG_RD(bp, func_ext_config[func].
9399 fcoe_mac_addr_upper);
9400 val = MF_CFG_RD(bp, func_ext_config[func].
9401 fcoe_mac_addr_lower);
9402 bnx2x_set_mac_buf(fip_mac, val, val2);
9403 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n",
9404 fip_mac);
9405
9406 } else
9407 bp->flags |= NO_FCOE_FLAG;
9408 }
9409 #endif
9410 } else {
9411 /* in SF read MACs from port configuration */
9412 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9413 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9414 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9415
9416 #ifdef BCM_CNIC
9417 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9418 iscsi_mac_upper);
9419 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9420 iscsi_mac_lower);
9421 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9422
9423 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9424 fcoe_fip_mac_upper);
9425 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9426 fcoe_fip_mac_lower);
9427 bnx2x_set_mac_buf(fip_mac, val, val2);
9428 #endif
9429 }
9430
9431 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9432 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9433
9434 #ifdef BCM_CNIC
9435 /* Set the FCoE MAC in MF_SD mode */
9436 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9437 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9438
9439 /* Disable iSCSI if MAC configuration is
9440 * invalid.
9441 */
9442 if (!is_valid_ether_addr(iscsi_mac)) {
9443 bp->flags |= NO_ISCSI_FLAG;
9444 memset(iscsi_mac, 0, ETH_ALEN);
9445 }
9446
9447 /* Disable FCoE if MAC configuration is
9448 * invalid.
9449 */
9450 if (!is_valid_ether_addr(fip_mac)) {
9451 bp->flags |= NO_FCOE_FLAG;
9452 memset(bp->fip_mac, 0, ETH_ALEN);
9453 }
9454 #endif
9455
9456 if (!is_valid_ether_addr(bp->dev->dev_addr))
9457 dev_err(&bp->pdev->dev,
9458 "bad Ethernet MAC address configuration: "
9459 "%pM, change it manually before bringing up "
9460 "the appropriate network interface\n",
9461 bp->dev->dev_addr);
9462 }
9463
9464 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9465 {
9466 int /*abs*/func = BP_ABS_FUNC(bp);
9467 int vn;
9468 u32 val = 0;
9469 int rc = 0;
9470
9471 bnx2x_get_common_hwinfo(bp);
9472
9473 /*
9474 * initialize IGU parameters
9475 */
9476 if (CHIP_IS_E1x(bp)) {
9477 bp->common.int_block = INT_BLOCK_HC;
9478
9479 bp->igu_dsb_id = DEF_SB_IGU_ID;
9480 bp->igu_base_sb = 0;
9481 } else {
9482 bp->common.int_block = INT_BLOCK_IGU;
9483
9484 /* do not allow device reset during IGU info preocessing */
9485 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9486
9487 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9488
9489 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9490 int tout = 5000;
9491
9492 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9493
9494 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9495 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9496 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9497
9498 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9499 tout--;
9500 usleep_range(1000, 1000);
9501 }
9502
9503 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9504 dev_err(&bp->pdev->dev,
9505 "FORCING Normal Mode failed!!!\n");
9506 return -EPERM;
9507 }
9508 }
9509
9510 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9511 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9512 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9513 } else
9514 BNX2X_DEV_INFO("IGU Normal Mode\n");
9515
9516 bnx2x_get_igu_cam_info(bp);
9517
9518 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9519 }
9520
9521 /*
9522 * set base FW non-default (fast path) status block id, this value is
9523 * used to initialize the fw_sb_id saved on the fp/queue structure to
9524 * determine the id used by the FW.
9525 */
9526 if (CHIP_IS_E1x(bp))
9527 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9528 else /*
9529 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9530 * the same queue are indicated on the same IGU SB). So we prefer
9531 * FW and IGU SBs to be the same value.
9532 */
9533 bp->base_fw_ndsb = bp->igu_base_sb;
9534
9535 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9536 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9537 bp->igu_sb_cnt, bp->base_fw_ndsb);
9538
9539 /*
9540 * Initialize MF configuration
9541 */
9542
9543 bp->mf_ov = 0;
9544 bp->mf_mode = 0;
9545 vn = BP_VN(bp);
9546
9547 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9548 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9549 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9550 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9551
9552 if (SHMEM2_HAS(bp, mf_cfg_addr))
9553 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9554 else
9555 bp->common.mf_cfg_base = bp->common.shmem_base +
9556 offsetof(struct shmem_region, func_mb) +
9557 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9558 /*
9559 * get mf configuration:
9560 * 1. existence of MF configuration
9561 * 2. MAC address must be legal (check only upper bytes)
9562 * for Switch-Independent mode;
9563 * OVLAN must be legal for Switch-Dependent mode
9564 * 3. SF_MODE configures specific MF mode
9565 */
9566 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9567 /* get mf configuration */
9568 val = SHMEM_RD(bp,
9569 dev_info.shared_feature_config.config);
9570 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9571
9572 switch (val) {
9573 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9574 val = MF_CFG_RD(bp, func_mf_config[func].
9575 mac_upper);
9576 /* check for legal mac (upper bytes)*/
9577 if (val != 0xffff) {
9578 bp->mf_mode = MULTI_FUNCTION_SI;
9579 bp->mf_config[vn] = MF_CFG_RD(bp,
9580 func_mf_config[func].config);
9581 } else
9582 BNX2X_DEV_INFO("illegal MAC address "
9583 "for SI\n");
9584 break;
9585 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9586 /* get OV configuration */
9587 val = MF_CFG_RD(bp,
9588 func_mf_config[FUNC_0].e1hov_tag);
9589 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9590
9591 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9592 bp->mf_mode = MULTI_FUNCTION_SD;
9593 bp->mf_config[vn] = MF_CFG_RD(bp,
9594 func_mf_config[func].config);
9595 } else
9596 BNX2X_DEV_INFO("illegal OV for SD\n");
9597 break;
9598 default:
9599 /* Unknown configuration: reset mf_config */
9600 bp->mf_config[vn] = 0;
9601 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9602 }
9603 }
9604
9605 BNX2X_DEV_INFO("%s function mode\n",
9606 IS_MF(bp) ? "multi" : "single");
9607
9608 switch (bp->mf_mode) {
9609 case MULTI_FUNCTION_SD:
9610 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9611 FUNC_MF_CFG_E1HOV_TAG_MASK;
9612 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9613 bp->mf_ov = val;
9614 bp->path_has_ovlan = true;
9615
9616 BNX2X_DEV_INFO("MF OV for func %d is %d "
9617 "(0x%04x)\n", func, bp->mf_ov,
9618 bp->mf_ov);
9619 } else {
9620 dev_err(&bp->pdev->dev,
9621 "No valid MF OV for func %d, "
9622 "aborting\n", func);
9623 return -EPERM;
9624 }
9625 break;
9626 case MULTI_FUNCTION_SI:
9627 BNX2X_DEV_INFO("func %d is in MF "
9628 "switch-independent mode\n", func);
9629 break;
9630 default:
9631 if (vn) {
9632 dev_err(&bp->pdev->dev,
9633 "VN %d is in a single function mode, "
9634 "aborting\n", vn);
9635 return -EPERM;
9636 }
9637 break;
9638 }
9639
9640 /* check if other port on the path needs ovlan:
9641 * Since MF configuration is shared between ports
9642 * Possible mixed modes are only
9643 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9644 */
9645 if (CHIP_MODE_IS_4_PORT(bp) &&
9646 !bp->path_has_ovlan &&
9647 !IS_MF(bp) &&
9648 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9649 u8 other_port = !BP_PORT(bp);
9650 u8 other_func = BP_PATH(bp) + 2*other_port;
9651 val = MF_CFG_RD(bp,
9652 func_mf_config[other_func].e1hov_tag);
9653 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9654 bp->path_has_ovlan = true;
9655 }
9656 }
9657
9658 /* adjust igu_sb_cnt to MF for E1x */
9659 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9660 bp->igu_sb_cnt /= E1HVN_MAX;
9661
9662 /* port info */
9663 bnx2x_get_port_hwinfo(bp);
9664
9665 /* Get MAC addresses */
9666 bnx2x_get_mac_hwinfo(bp);
9667
9668 #ifdef BCM_CNIC
9669 bnx2x_get_cnic_info(bp);
9670 #endif
9671
9672 /* Get current FW pulse sequence */
9673 if (!BP_NOMCP(bp)) {
9674 int mb_idx = BP_FW_MB_IDX(bp);
9675
9676 bp->fw_drv_pulse_wr_seq =
9677 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9678 DRV_PULSE_SEQ_MASK);
9679 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9680 }
9681
9682 return rc;
9683 }
9684
9685 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9686 {
9687 int cnt, i, block_end, rodi;
9688 char vpd_data[BNX2X_VPD_LEN+1];
9689 char str_id_reg[VENDOR_ID_LEN+1];
9690 char str_id_cap[VENDOR_ID_LEN+1];
9691 u8 len;
9692
9693 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9694 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9695
9696 if (cnt < BNX2X_VPD_LEN)
9697 goto out_not_found;
9698
9699 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9700 PCI_VPD_LRDT_RO_DATA);
9701 if (i < 0)
9702 goto out_not_found;
9703
9704
9705 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9706 pci_vpd_lrdt_size(&vpd_data[i]);
9707
9708 i += PCI_VPD_LRDT_TAG_SIZE;
9709
9710 if (block_end > BNX2X_VPD_LEN)
9711 goto out_not_found;
9712
9713 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9714 PCI_VPD_RO_KEYWORD_MFR_ID);
9715 if (rodi < 0)
9716 goto out_not_found;
9717
9718 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9719
9720 if (len != VENDOR_ID_LEN)
9721 goto out_not_found;
9722
9723 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9724
9725 /* vendor specific info */
9726 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9727 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9728 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9729 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9730
9731 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9732 PCI_VPD_RO_KEYWORD_VENDOR0);
9733 if (rodi >= 0) {
9734 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9735
9736 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9737
9738 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9739 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9740 bp->fw_ver[len] = ' ';
9741 }
9742 }
9743 return;
9744 }
9745 out_not_found:
9746 return;
9747 }
9748
9749 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9750 {
9751 u32 flags = 0;
9752
9753 if (CHIP_REV_IS_FPGA(bp))
9754 SET_FLAGS(flags, MODE_FPGA);
9755 else if (CHIP_REV_IS_EMUL(bp))
9756 SET_FLAGS(flags, MODE_EMUL);
9757 else
9758 SET_FLAGS(flags, MODE_ASIC);
9759
9760 if (CHIP_MODE_IS_4_PORT(bp))
9761 SET_FLAGS(flags, MODE_PORT4);
9762 else
9763 SET_FLAGS(flags, MODE_PORT2);
9764
9765 if (CHIP_IS_E2(bp))
9766 SET_FLAGS(flags, MODE_E2);
9767 else if (CHIP_IS_E3(bp)) {
9768 SET_FLAGS(flags, MODE_E3);
9769 if (CHIP_REV(bp) == CHIP_REV_Ax)
9770 SET_FLAGS(flags, MODE_E3_A0);
9771 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9772 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9773 }
9774
9775 if (IS_MF(bp)) {
9776 SET_FLAGS(flags, MODE_MF);
9777 switch (bp->mf_mode) {
9778 case MULTI_FUNCTION_SD:
9779 SET_FLAGS(flags, MODE_MF_SD);
9780 break;
9781 case MULTI_FUNCTION_SI:
9782 SET_FLAGS(flags, MODE_MF_SI);
9783 break;
9784 }
9785 } else
9786 SET_FLAGS(flags, MODE_SF);
9787
9788 #if defined(__LITTLE_ENDIAN)
9789 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9790 #else /*(__BIG_ENDIAN)*/
9791 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9792 #endif
9793 INIT_MODE_FLAGS(bp) = flags;
9794 }
9795
9796 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9797 {
9798 int func;
9799 int timer_interval;
9800 int rc;
9801
9802 mutex_init(&bp->port.phy_mutex);
9803 mutex_init(&bp->fw_mb_mutex);
9804 spin_lock_init(&bp->stats_lock);
9805 #ifdef BCM_CNIC
9806 mutex_init(&bp->cnic_mutex);
9807 #endif
9808
9809 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9810 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9811 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9812 rc = bnx2x_get_hwinfo(bp);
9813 if (rc)
9814 return rc;
9815
9816 bnx2x_set_modes_bitmap(bp);
9817
9818 rc = bnx2x_alloc_mem_bp(bp);
9819 if (rc)
9820 return rc;
9821
9822 bnx2x_read_fwinfo(bp);
9823
9824 func = BP_FUNC(bp);
9825
9826 /* need to reset chip if undi was active */
9827 if (!BP_NOMCP(bp))
9828 bnx2x_undi_unload(bp);
9829
9830 /* init fw_seq after undi_unload! */
9831 if (!BP_NOMCP(bp)) {
9832 bp->fw_seq =
9833 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9834 DRV_MSG_SEQ_NUMBER_MASK);
9835 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9836 }
9837
9838 if (CHIP_REV_IS_FPGA(bp))
9839 dev_err(&bp->pdev->dev, "FPGA detected\n");
9840
9841 if (BP_NOMCP(bp) && (func == 0))
9842 dev_err(&bp->pdev->dev, "MCP disabled, "
9843 "must load devices in order!\n");
9844
9845 bp->multi_mode = multi_mode;
9846
9847 /* Set TPA flags */
9848 if (disable_tpa) {
9849 bp->flags &= ~TPA_ENABLE_FLAG;
9850 bp->dev->features &= ~NETIF_F_LRO;
9851 } else {
9852 bp->flags |= TPA_ENABLE_FLAG;
9853 bp->dev->features |= NETIF_F_LRO;
9854 }
9855 bp->disable_tpa = disable_tpa;
9856
9857 if (CHIP_IS_E1(bp))
9858 bp->dropless_fc = 0;
9859 else
9860 bp->dropless_fc = dropless_fc;
9861
9862 bp->mrrs = mrrs;
9863
9864 bp->tx_ring_size = MAX_TX_AVAIL;
9865
9866 /* make sure that the numbers are in the right granularity */
9867 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9868 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9869
9870 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9871 bp->current_interval = (poll ? poll : timer_interval);
9872
9873 init_timer(&bp->timer);
9874 bp->timer.expires = jiffies + bp->current_interval;
9875 bp->timer.data = (unsigned long) bp;
9876 bp->timer.function = bnx2x_timer;
9877
9878 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9879 bnx2x_dcbx_init_params(bp);
9880
9881 #ifdef BCM_CNIC
9882 if (CHIP_IS_E1x(bp))
9883 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9884 else
9885 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9886 #endif
9887
9888 /* multiple tx priority */
9889 if (CHIP_IS_E1x(bp))
9890 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9891 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9892 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9893 if (CHIP_IS_E3B0(bp))
9894 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9895
9896 return rc;
9897 }
9898
9899
9900 /****************************************************************************
9901 * General service functions
9902 ****************************************************************************/
9903
9904 /*
9905 * net_device service functions
9906 */
9907
9908 /* called with rtnl_lock */
9909 static int bnx2x_open(struct net_device *dev)
9910 {
9911 struct bnx2x *bp = netdev_priv(dev);
9912 bool global = false;
9913 int other_engine = BP_PATH(bp) ? 0 : 1;
9914 u32 other_load_counter, load_counter;
9915
9916 netif_carrier_off(dev);
9917
9918 bnx2x_set_power_state(bp, PCI_D0);
9919
9920 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9921 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9922
9923 /*
9924 * If parity had happen during the unload, then attentions
9925 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9926 * want the first function loaded on the current engine to
9927 * complete the recovery.
9928 */
9929 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9930 bnx2x_chk_parity_attn(bp, &global, true))
9931 do {
9932 /*
9933 * If there are attentions and they are in a global
9934 * blocks, set the GLOBAL_RESET bit regardless whether
9935 * it will be this function that will complete the
9936 * recovery or not.
9937 */
9938 if (global)
9939 bnx2x_set_reset_global(bp);
9940
9941 /*
9942 * Only the first function on the current engine should
9943 * try to recover in open. In case of attentions in
9944 * global blocks only the first in the chip should try
9945 * to recover.
9946 */
9947 if ((!load_counter &&
9948 (!global || !other_load_counter)) &&
9949 bnx2x_trylock_leader_lock(bp) &&
9950 !bnx2x_leader_reset(bp)) {
9951 netdev_info(bp->dev, "Recovered in open\n");
9952 break;
9953 }
9954
9955 /* recovery has failed... */
9956 bnx2x_set_power_state(bp, PCI_D3hot);
9957 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9958
9959 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9960 " completed yet. Try again later. If u still see this"
9961 " message after a few retries then power cycle is"
9962 " required.\n");
9963
9964 return -EAGAIN;
9965 } while (0);
9966
9967 bp->recovery_state = BNX2X_RECOVERY_DONE;
9968 return bnx2x_nic_load(bp, LOAD_OPEN);
9969 }
9970
9971 /* called with rtnl_lock */
9972 static int bnx2x_close(struct net_device *dev)
9973 {
9974 struct bnx2x *bp = netdev_priv(dev);
9975
9976 /* Unload the driver, release IRQs */
9977 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9978
9979 /* Power off */
9980 bnx2x_set_power_state(bp, PCI_D3hot);
9981
9982 return 0;
9983 }
9984
9985 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9986 struct bnx2x_mcast_ramrod_params *p)
9987 {
9988 int mc_count = netdev_mc_count(bp->dev);
9989 struct bnx2x_mcast_list_elem *mc_mac =
9990 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9991 struct netdev_hw_addr *ha;
9992
9993 if (!mc_mac)
9994 return -ENOMEM;
9995
9996 INIT_LIST_HEAD(&p->mcast_list);
9997
9998 netdev_for_each_mc_addr(ha, bp->dev) {
9999 mc_mac->mac = bnx2x_mc_addr(ha);
10000 list_add_tail(&mc_mac->link, &p->mcast_list);
10001 mc_mac++;
10002 }
10003
10004 p->mcast_list_len = mc_count;
10005
10006 return 0;
10007 }
10008
10009 static inline void bnx2x_free_mcast_macs_list(
10010 struct bnx2x_mcast_ramrod_params *p)
10011 {
10012 struct bnx2x_mcast_list_elem *mc_mac =
10013 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10014 link);
10015
10016 WARN_ON(!mc_mac);
10017 kfree(mc_mac);
10018 }
10019
10020 /**
10021 * bnx2x_set_uc_list - configure a new unicast MACs list.
10022 *
10023 * @bp: driver handle
10024 *
10025 * We will use zero (0) as a MAC type for these MACs.
10026 */
10027 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10028 {
10029 int rc;
10030 struct net_device *dev = bp->dev;
10031 struct netdev_hw_addr *ha;
10032 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10033 unsigned long ramrod_flags = 0;
10034
10035 /* First schedule a cleanup up of old configuration */
10036 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10037 if (rc < 0) {
10038 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10039 return rc;
10040 }
10041
10042 netdev_for_each_uc_addr(ha, dev) {
10043 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10044 BNX2X_UC_LIST_MAC, &ramrod_flags);
10045 if (rc < 0) {
10046 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10047 rc);
10048 return rc;
10049 }
10050 }
10051
10052 /* Execute the pending commands */
10053 __set_bit(RAMROD_CONT, &ramrod_flags);
10054 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10055 BNX2X_UC_LIST_MAC, &ramrod_flags);
10056 }
10057
10058 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10059 {
10060 struct net_device *dev = bp->dev;
10061 struct bnx2x_mcast_ramrod_params rparam = {0};
10062 int rc = 0;
10063
10064 rparam.mcast_obj = &bp->mcast_obj;
10065
10066 /* first, clear all configured multicast MACs */
10067 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10068 if (rc < 0) {
10069 BNX2X_ERR("Failed to clear multicast "
10070 "configuration: %d\n", rc);
10071 return rc;
10072 }
10073
10074 /* then, configure a new MACs list */
10075 if (netdev_mc_count(dev)) {
10076 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10077 if (rc) {
10078 BNX2X_ERR("Failed to create multicast MACs "
10079 "list: %d\n", rc);
10080 return rc;
10081 }
10082
10083 /* Now add the new MACs */
10084 rc = bnx2x_config_mcast(bp, &rparam,
10085 BNX2X_MCAST_CMD_ADD);
10086 if (rc < 0)
10087 BNX2X_ERR("Failed to set a new multicast "
10088 "configuration: %d\n", rc);
10089
10090 bnx2x_free_mcast_macs_list(&rparam);
10091 }
10092
10093 return rc;
10094 }
10095
10096
10097 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10098 void bnx2x_set_rx_mode(struct net_device *dev)
10099 {
10100 struct bnx2x *bp = netdev_priv(dev);
10101 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10102
10103 if (bp->state != BNX2X_STATE_OPEN) {
10104 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10105 return;
10106 }
10107
10108 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10109
10110 if (dev->flags & IFF_PROMISC)
10111 rx_mode = BNX2X_RX_MODE_PROMISC;
10112 else if ((dev->flags & IFF_ALLMULTI) ||
10113 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10114 CHIP_IS_E1(bp)))
10115 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10116 else {
10117 /* some multicasts */
10118 if (bnx2x_set_mc_list(bp) < 0)
10119 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10120
10121 if (bnx2x_set_uc_list(bp) < 0)
10122 rx_mode = BNX2X_RX_MODE_PROMISC;
10123 }
10124
10125 bp->rx_mode = rx_mode;
10126
10127 /* Schedule the rx_mode command */
10128 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10129 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10130 return;
10131 }
10132
10133 bnx2x_set_storm_rx_mode(bp);
10134 }
10135
10136 /* called with rtnl_lock */
10137 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10138 int devad, u16 addr)
10139 {
10140 struct bnx2x *bp = netdev_priv(netdev);
10141 u16 value;
10142 int rc;
10143
10144 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10145 prtad, devad, addr);
10146
10147 /* The HW expects different devad if CL22 is used */
10148 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10149
10150 bnx2x_acquire_phy_lock(bp);
10151 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10152 bnx2x_release_phy_lock(bp);
10153 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10154
10155 if (!rc)
10156 rc = value;
10157 return rc;
10158 }
10159
10160 /* called with rtnl_lock */
10161 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10162 u16 addr, u16 value)
10163 {
10164 struct bnx2x *bp = netdev_priv(netdev);
10165 int rc;
10166
10167 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10168 " value 0x%x\n", prtad, devad, addr, value);
10169
10170 /* The HW expects different devad if CL22 is used */
10171 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10172
10173 bnx2x_acquire_phy_lock(bp);
10174 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10175 bnx2x_release_phy_lock(bp);
10176 return rc;
10177 }
10178
10179 /* called with rtnl_lock */
10180 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10181 {
10182 struct bnx2x *bp = netdev_priv(dev);
10183 struct mii_ioctl_data *mdio = if_mii(ifr);
10184
10185 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10186 mdio->phy_id, mdio->reg_num, mdio->val_in);
10187
10188 if (!netif_running(dev))
10189 return -EAGAIN;
10190
10191 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10192 }
10193
10194 #ifdef CONFIG_NET_POLL_CONTROLLER
10195 static void poll_bnx2x(struct net_device *dev)
10196 {
10197 struct bnx2x *bp = netdev_priv(dev);
10198
10199 disable_irq(bp->pdev->irq);
10200 bnx2x_interrupt(bp->pdev->irq, dev);
10201 enable_irq(bp->pdev->irq);
10202 }
10203 #endif
10204
10205 static const struct net_device_ops bnx2x_netdev_ops = {
10206 .ndo_open = bnx2x_open,
10207 .ndo_stop = bnx2x_close,
10208 .ndo_start_xmit = bnx2x_start_xmit,
10209 .ndo_select_queue = bnx2x_select_queue,
10210 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10211 .ndo_set_mac_address = bnx2x_change_mac_addr,
10212 .ndo_validate_addr = eth_validate_addr,
10213 .ndo_do_ioctl = bnx2x_ioctl,
10214 .ndo_change_mtu = bnx2x_change_mtu,
10215 .ndo_fix_features = bnx2x_fix_features,
10216 .ndo_set_features = bnx2x_set_features,
10217 .ndo_tx_timeout = bnx2x_tx_timeout,
10218 #ifdef CONFIG_NET_POLL_CONTROLLER
10219 .ndo_poll_controller = poll_bnx2x,
10220 #endif
10221 .ndo_setup_tc = bnx2x_setup_tc,
10222
10223 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10224 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10225 #endif
10226 };
10227
10228 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10229 {
10230 struct device *dev = &bp->pdev->dev;
10231
10232 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10233 bp->flags |= USING_DAC_FLAG;
10234 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10235 dev_err(dev, "dma_set_coherent_mask failed, "
10236 "aborting\n");
10237 return -EIO;
10238 }
10239 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10240 dev_err(dev, "System does not support DMA, aborting\n");
10241 return -EIO;
10242 }
10243
10244 return 0;
10245 }
10246
10247 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10248 struct net_device *dev,
10249 unsigned long board_type)
10250 {
10251 struct bnx2x *bp;
10252 int rc;
10253
10254 SET_NETDEV_DEV(dev, &pdev->dev);
10255 bp = netdev_priv(dev);
10256
10257 bp->dev = dev;
10258 bp->pdev = pdev;
10259 bp->flags = 0;
10260 bp->pf_num = PCI_FUNC(pdev->devfn);
10261
10262 rc = pci_enable_device(pdev);
10263 if (rc) {
10264 dev_err(&bp->pdev->dev,
10265 "Cannot enable PCI device, aborting\n");
10266 goto err_out;
10267 }
10268
10269 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10270 dev_err(&bp->pdev->dev,
10271 "Cannot find PCI device base address, aborting\n");
10272 rc = -ENODEV;
10273 goto err_out_disable;
10274 }
10275
10276 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10277 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10278 " base address, aborting\n");
10279 rc = -ENODEV;
10280 goto err_out_disable;
10281 }
10282
10283 if (atomic_read(&pdev->enable_cnt) == 1) {
10284 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10285 if (rc) {
10286 dev_err(&bp->pdev->dev,
10287 "Cannot obtain PCI resources, aborting\n");
10288 goto err_out_disable;
10289 }
10290
10291 pci_set_master(pdev);
10292 pci_save_state(pdev);
10293 }
10294
10295 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10296 if (bp->pm_cap == 0) {
10297 dev_err(&bp->pdev->dev,
10298 "Cannot find power management capability, aborting\n");
10299 rc = -EIO;
10300 goto err_out_release;
10301 }
10302
10303 if (!pci_is_pcie(pdev)) {
10304 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10305 rc = -EIO;
10306 goto err_out_release;
10307 }
10308
10309 rc = bnx2x_set_coherency_mask(bp);
10310 if (rc)
10311 goto err_out_release;
10312
10313 dev->mem_start = pci_resource_start(pdev, 0);
10314 dev->base_addr = dev->mem_start;
10315 dev->mem_end = pci_resource_end(pdev, 0);
10316
10317 dev->irq = pdev->irq;
10318
10319 bp->regview = pci_ioremap_bar(pdev, 0);
10320 if (!bp->regview) {
10321 dev_err(&bp->pdev->dev,
10322 "Cannot map register space, aborting\n");
10323 rc = -ENOMEM;
10324 goto err_out_release;
10325 }
10326
10327 bnx2x_set_power_state(bp, PCI_D0);
10328
10329 /* clean indirect addresses */
10330 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10331 PCICFG_VENDOR_ID_OFFSET);
10332 /*
10333 * Clean the following indirect addresses for all functions since it
10334 * is not used by the driver.
10335 */
10336 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10337 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10338 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10339 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10340
10341 if (CHIP_IS_E1x(bp)) {
10342 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10343 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10344 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10345 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10346 }
10347
10348 /*
10349 * Enable internal target-read (in case we are probed after PF FLR).
10350 * Must be done prior to any BAR read access. Only for 57712 and up
10351 */
10352 if (board_type != BCM57710 &&
10353 board_type != BCM57711 &&
10354 board_type != BCM57711E)
10355 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10356
10357 /* Reset the load counter */
10358 bnx2x_clear_load_cnt(bp);
10359
10360 dev->watchdog_timeo = TX_TIMEOUT;
10361
10362 dev->netdev_ops = &bnx2x_netdev_ops;
10363 bnx2x_set_ethtool_ops(dev);
10364
10365 dev->priv_flags |= IFF_UNICAST_FLT;
10366
10367 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10368 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10369 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
10370
10371 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10372 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10373
10374 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10375 if (bp->flags & USING_DAC_FLAG)
10376 dev->features |= NETIF_F_HIGHDMA;
10377
10378 /* Add Loopback capability to the device */
10379 dev->hw_features |= NETIF_F_LOOPBACK;
10380
10381 #ifdef BCM_DCBNL
10382 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10383 #endif
10384
10385 /* get_port_hwinfo() will set prtad and mmds properly */
10386 bp->mdio.prtad = MDIO_PRTAD_NONE;
10387 bp->mdio.mmds = 0;
10388 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10389 bp->mdio.dev = dev;
10390 bp->mdio.mdio_read = bnx2x_mdio_read;
10391 bp->mdio.mdio_write = bnx2x_mdio_write;
10392
10393 return 0;
10394
10395 err_out_release:
10396 if (atomic_read(&pdev->enable_cnt) == 1)
10397 pci_release_regions(pdev);
10398
10399 err_out_disable:
10400 pci_disable_device(pdev);
10401 pci_set_drvdata(pdev, NULL);
10402
10403 err_out:
10404 return rc;
10405 }
10406
10407 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10408 int *width, int *speed)
10409 {
10410 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10411
10412 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10413
10414 /* return value of 1=2.5GHz 2=5GHz */
10415 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10416 }
10417
10418 static int bnx2x_check_firmware(struct bnx2x *bp)
10419 {
10420 const struct firmware *firmware = bp->firmware;
10421 struct bnx2x_fw_file_hdr *fw_hdr;
10422 struct bnx2x_fw_file_section *sections;
10423 u32 offset, len, num_ops;
10424 u16 *ops_offsets;
10425 int i;
10426 const u8 *fw_ver;
10427
10428 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10429 return -EINVAL;
10430
10431 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10432 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10433
10434 /* Make sure none of the offsets and sizes make us read beyond
10435 * the end of the firmware data */
10436 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10437 offset = be32_to_cpu(sections[i].offset);
10438 len = be32_to_cpu(sections[i].len);
10439 if (offset + len > firmware->size) {
10440 dev_err(&bp->pdev->dev,
10441 "Section %d length is out of bounds\n", i);
10442 return -EINVAL;
10443 }
10444 }
10445
10446 /* Likewise for the init_ops offsets */
10447 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10448 ops_offsets = (u16 *)(firmware->data + offset);
10449 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10450
10451 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10452 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10453 dev_err(&bp->pdev->dev,
10454 "Section offset %d is out of bounds\n", i);
10455 return -EINVAL;
10456 }
10457 }
10458
10459 /* Check FW version */
10460 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10461 fw_ver = firmware->data + offset;
10462 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10463 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10464 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10465 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10466 dev_err(&bp->pdev->dev,
10467 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10468 fw_ver[0], fw_ver[1], fw_ver[2],
10469 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10470 BCM_5710_FW_MINOR_VERSION,
10471 BCM_5710_FW_REVISION_VERSION,
10472 BCM_5710_FW_ENGINEERING_VERSION);
10473 return -EINVAL;
10474 }
10475
10476 return 0;
10477 }
10478
10479 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10480 {
10481 const __be32 *source = (const __be32 *)_source;
10482 u32 *target = (u32 *)_target;
10483 u32 i;
10484
10485 for (i = 0; i < n/4; i++)
10486 target[i] = be32_to_cpu(source[i]);
10487 }
10488
10489 /*
10490 Ops array is stored in the following format:
10491 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10492 */
10493 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10494 {
10495 const __be32 *source = (const __be32 *)_source;
10496 struct raw_op *target = (struct raw_op *)_target;
10497 u32 i, j, tmp;
10498
10499 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10500 tmp = be32_to_cpu(source[j]);
10501 target[i].op = (tmp >> 24) & 0xff;
10502 target[i].offset = tmp & 0xffffff;
10503 target[i].raw_data = be32_to_cpu(source[j + 1]);
10504 }
10505 }
10506
10507 /**
10508 * IRO array is stored in the following format:
10509 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10510 */
10511 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10512 {
10513 const __be32 *source = (const __be32 *)_source;
10514 struct iro *target = (struct iro *)_target;
10515 u32 i, j, tmp;
10516
10517 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10518 target[i].base = be32_to_cpu(source[j]);
10519 j++;
10520 tmp = be32_to_cpu(source[j]);
10521 target[i].m1 = (tmp >> 16) & 0xffff;
10522 target[i].m2 = tmp & 0xffff;
10523 j++;
10524 tmp = be32_to_cpu(source[j]);
10525 target[i].m3 = (tmp >> 16) & 0xffff;
10526 target[i].size = tmp & 0xffff;
10527 j++;
10528 }
10529 }
10530
10531 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10532 {
10533 const __be16 *source = (const __be16 *)_source;
10534 u16 *target = (u16 *)_target;
10535 u32 i;
10536
10537 for (i = 0; i < n/2; i++)
10538 target[i] = be16_to_cpu(source[i]);
10539 }
10540
10541 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10542 do { \
10543 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10544 bp->arr = kmalloc(len, GFP_KERNEL); \
10545 if (!bp->arr) { \
10546 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10547 goto lbl; \
10548 } \
10549 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10550 (u8 *)bp->arr, len); \
10551 } while (0)
10552
10553 int bnx2x_init_firmware(struct bnx2x *bp)
10554 {
10555 const char *fw_file_name;
10556 struct bnx2x_fw_file_hdr *fw_hdr;
10557 int rc;
10558
10559 if (CHIP_IS_E1(bp))
10560 fw_file_name = FW_FILE_NAME_E1;
10561 else if (CHIP_IS_E1H(bp))
10562 fw_file_name = FW_FILE_NAME_E1H;
10563 else if (!CHIP_IS_E1x(bp))
10564 fw_file_name = FW_FILE_NAME_E2;
10565 else {
10566 BNX2X_ERR("Unsupported chip revision\n");
10567 return -EINVAL;
10568 }
10569
10570 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10571
10572 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10573 if (rc) {
10574 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10575 goto request_firmware_exit;
10576 }
10577
10578 rc = bnx2x_check_firmware(bp);
10579 if (rc) {
10580 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10581 goto request_firmware_exit;
10582 }
10583
10584 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10585
10586 /* Initialize the pointers to the init arrays */
10587 /* Blob */
10588 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10589
10590 /* Opcodes */
10591 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10592
10593 /* Offsets */
10594 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10595 be16_to_cpu_n);
10596
10597 /* STORMs firmware */
10598 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10599 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10600 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10601 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10602 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10603 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10604 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10605 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10606 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10607 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10608 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10609 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10610 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10611 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10612 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10613 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10614 /* IRO */
10615 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10616
10617 return 0;
10618
10619 iro_alloc_err:
10620 kfree(bp->init_ops_offsets);
10621 init_offsets_alloc_err:
10622 kfree(bp->init_ops);
10623 init_ops_alloc_err:
10624 kfree(bp->init_data);
10625 request_firmware_exit:
10626 release_firmware(bp->firmware);
10627
10628 return rc;
10629 }
10630
10631 static void bnx2x_release_firmware(struct bnx2x *bp)
10632 {
10633 kfree(bp->init_ops_offsets);
10634 kfree(bp->init_ops);
10635 kfree(bp->init_data);
10636 release_firmware(bp->firmware);
10637 }
10638
10639
10640 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10641 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10642 .init_hw_cmn = bnx2x_init_hw_common,
10643 .init_hw_port = bnx2x_init_hw_port,
10644 .init_hw_func = bnx2x_init_hw_func,
10645
10646 .reset_hw_cmn = bnx2x_reset_common,
10647 .reset_hw_port = bnx2x_reset_port,
10648 .reset_hw_func = bnx2x_reset_func,
10649
10650 .gunzip_init = bnx2x_gunzip_init,
10651 .gunzip_end = bnx2x_gunzip_end,
10652
10653 .init_fw = bnx2x_init_firmware,
10654 .release_fw = bnx2x_release_firmware,
10655 };
10656
10657 void bnx2x__init_func_obj(struct bnx2x *bp)
10658 {
10659 /* Prepare DMAE related driver resources */
10660 bnx2x_setup_dmae(bp);
10661
10662 bnx2x_init_func_obj(bp, &bp->func_obj,
10663 bnx2x_sp(bp, func_rdata),
10664 bnx2x_sp_mapping(bp, func_rdata),
10665 &bnx2x_func_sp_drv);
10666 }
10667
10668 /* must be called after sriov-enable */
10669 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10670 {
10671 int cid_count = BNX2X_L2_CID_COUNT(bp);
10672
10673 #ifdef BCM_CNIC
10674 cid_count += CNIC_CID_MAX;
10675 #endif
10676 return roundup(cid_count, QM_CID_ROUND);
10677 }
10678
10679 /**
10680 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10681 *
10682 * @dev: pci device
10683 *
10684 */
10685 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10686 {
10687 int pos;
10688 u16 control;
10689
10690 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10691
10692 /*
10693 * If MSI-X is not supported - return number of SBs needed to support
10694 * one fast path queue: one FP queue + SB for CNIC
10695 */
10696 if (!pos)
10697 return 1 + CNIC_PRESENT;
10698
10699 /*
10700 * The value in the PCI configuration space is the index of the last
10701 * entry, namely one less than the actual size of the table, which is
10702 * exactly what we want to return from this function: number of all SBs
10703 * without the default SB.
10704 */
10705 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10706 return control & PCI_MSIX_FLAGS_QSIZE;
10707 }
10708
10709 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10710 const struct pci_device_id *ent)
10711 {
10712 struct net_device *dev = NULL;
10713 struct bnx2x *bp;
10714 int pcie_width, pcie_speed;
10715 int rc, max_non_def_sbs;
10716 int rx_count, tx_count, rss_count;
10717 /*
10718 * An estimated maximum supported CoS number according to the chip
10719 * version.
10720 * We will try to roughly estimate the maximum number of CoSes this chip
10721 * may support in order to minimize the memory allocated for Tx
10722 * netdev_queue's. This number will be accurately calculated during the
10723 * initialization of bp->max_cos based on the chip versions AND chip
10724 * revision in the bnx2x_init_bp().
10725 */
10726 u8 max_cos_est = 0;
10727
10728 switch (ent->driver_data) {
10729 case BCM57710:
10730 case BCM57711:
10731 case BCM57711E:
10732 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10733 break;
10734
10735 case BCM57712:
10736 case BCM57712_MF:
10737 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10738 break;
10739
10740 case BCM57800:
10741 case BCM57800_MF:
10742 case BCM57810:
10743 case BCM57810_MF:
10744 case BCM57840:
10745 case BCM57840_MF:
10746 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10747 break;
10748
10749 default:
10750 pr_err("Unknown board_type (%ld), aborting\n",
10751 ent->driver_data);
10752 return -ENODEV;
10753 }
10754
10755 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10756
10757 /* !!! FIXME !!!
10758 * Do not allow the maximum SB count to grow above 16
10759 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10760 * We will use the FP_SB_MAX_E1x macro for this matter.
10761 */
10762 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10763
10764 WARN_ON(!max_non_def_sbs);
10765
10766 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10767 rss_count = max_non_def_sbs - CNIC_PRESENT;
10768
10769 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10770 rx_count = rss_count + FCOE_PRESENT;
10771
10772 /*
10773 * Maximum number of netdev Tx queues:
10774 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10775 */
10776 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10777
10778 /* dev zeroed in init_etherdev */
10779 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10780 if (!dev) {
10781 dev_err(&pdev->dev, "Cannot allocate net device\n");
10782 return -ENOMEM;
10783 }
10784
10785 bp = netdev_priv(dev);
10786
10787 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10788 tx_count, rx_count);
10789
10790 bp->igu_sb_cnt = max_non_def_sbs;
10791 bp->msg_enable = debug;
10792 pci_set_drvdata(pdev, dev);
10793
10794 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10795 if (rc < 0) {
10796 free_netdev(dev);
10797 return rc;
10798 }
10799
10800 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
10801
10802 rc = bnx2x_init_bp(bp);
10803 if (rc)
10804 goto init_one_exit;
10805
10806 /*
10807 * Map doorbels here as we need the real value of bp->max_cos which
10808 * is initialized in bnx2x_init_bp().
10809 */
10810 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10811 min_t(u64, BNX2X_DB_SIZE(bp),
10812 pci_resource_len(pdev, 2)));
10813 if (!bp->doorbells) {
10814 dev_err(&bp->pdev->dev,
10815 "Cannot map doorbell space, aborting\n");
10816 rc = -ENOMEM;
10817 goto init_one_exit;
10818 }
10819
10820 /* calc qm_cid_count */
10821 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10822
10823 #ifdef BCM_CNIC
10824 /* disable FCOE L2 queue for E1x */
10825 if (CHIP_IS_E1x(bp))
10826 bp->flags |= NO_FCOE_FLAG;
10827
10828 #endif
10829
10830 /* Configure interrupt mode: try to enable MSI-X/MSI if
10831 * needed, set bp->num_queues appropriately.
10832 */
10833 bnx2x_set_int_mode(bp);
10834
10835 /* Add all NAPI objects */
10836 bnx2x_add_all_napi(bp);
10837
10838 rc = register_netdev(dev);
10839 if (rc) {
10840 dev_err(&pdev->dev, "Cannot register net device\n");
10841 goto init_one_exit;
10842 }
10843
10844 #ifdef BCM_CNIC
10845 if (!NO_FCOE(bp)) {
10846 /* Add storage MAC address */
10847 rtnl_lock();
10848 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10849 rtnl_unlock();
10850 }
10851 #endif
10852
10853 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10854
10855 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10856 board_info[ent->driver_data].name,
10857 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10858 pcie_width,
10859 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10860 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10861 "5GHz (Gen2)" : "2.5GHz",
10862 dev->base_addr, bp->pdev->irq, dev->dev_addr);
10863
10864 return 0;
10865
10866 init_one_exit:
10867 if (bp->regview)
10868 iounmap(bp->regview);
10869
10870 if (bp->doorbells)
10871 iounmap(bp->doorbells);
10872
10873 free_netdev(dev);
10874
10875 if (atomic_read(&pdev->enable_cnt) == 1)
10876 pci_release_regions(pdev);
10877
10878 pci_disable_device(pdev);
10879 pci_set_drvdata(pdev, NULL);
10880
10881 return rc;
10882 }
10883
10884 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10885 {
10886 struct net_device *dev = pci_get_drvdata(pdev);
10887 struct bnx2x *bp;
10888
10889 if (!dev) {
10890 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10891 return;
10892 }
10893 bp = netdev_priv(dev);
10894
10895 #ifdef BCM_CNIC
10896 /* Delete storage MAC address */
10897 if (!NO_FCOE(bp)) {
10898 rtnl_lock();
10899 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10900 rtnl_unlock();
10901 }
10902 #endif
10903
10904 #ifdef BCM_DCBNL
10905 /* Delete app tlvs from dcbnl */
10906 bnx2x_dcbnl_update_applist(bp, true);
10907 #endif
10908
10909 unregister_netdev(dev);
10910
10911 /* Delete all NAPI objects */
10912 bnx2x_del_all_napi(bp);
10913
10914 /* Power on: we can't let PCI layer write to us while we are in D3 */
10915 bnx2x_set_power_state(bp, PCI_D0);
10916
10917 /* Disable MSI/MSI-X */
10918 bnx2x_disable_msi(bp);
10919
10920 /* Power off */
10921 bnx2x_set_power_state(bp, PCI_D3hot);
10922
10923 /* Make sure RESET task is not scheduled before continuing */
10924 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10925
10926 if (bp->regview)
10927 iounmap(bp->regview);
10928
10929 if (bp->doorbells)
10930 iounmap(bp->doorbells);
10931
10932 bnx2x_free_mem_bp(bp);
10933
10934 free_netdev(dev);
10935
10936 if (atomic_read(&pdev->enable_cnt) == 1)
10937 pci_release_regions(pdev);
10938
10939 pci_disable_device(pdev);
10940 pci_set_drvdata(pdev, NULL);
10941 }
10942
10943 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10944 {
10945 int i;
10946
10947 bp->state = BNX2X_STATE_ERROR;
10948
10949 bp->rx_mode = BNX2X_RX_MODE_NONE;
10950
10951 #ifdef BCM_CNIC
10952 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10953 #endif
10954 /* Stop Tx */
10955 bnx2x_tx_disable(bp);
10956
10957 bnx2x_netif_stop(bp, 0);
10958
10959 del_timer_sync(&bp->timer);
10960
10961 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10962
10963 /* Release IRQs */
10964 bnx2x_free_irq(bp);
10965
10966 /* Free SKBs, SGEs, TPA pool and driver internals */
10967 bnx2x_free_skbs(bp);
10968
10969 for_each_rx_queue(bp, i)
10970 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10971
10972 bnx2x_free_mem(bp);
10973
10974 bp->state = BNX2X_STATE_CLOSED;
10975
10976 netif_carrier_off(bp->dev);
10977
10978 return 0;
10979 }
10980
10981 static void bnx2x_eeh_recover(struct bnx2x *bp)
10982 {
10983 u32 val;
10984
10985 mutex_init(&bp->port.phy_mutex);
10986
10987 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10988 bp->link_params.shmem_base = bp->common.shmem_base;
10989 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10990
10991 if (!bp->common.shmem_base ||
10992 (bp->common.shmem_base < 0xA0000) ||
10993 (bp->common.shmem_base >= 0xC0000)) {
10994 BNX2X_DEV_INFO("MCP not active\n");
10995 bp->flags |= NO_MCP_FLAG;
10996 return;
10997 }
10998
10999 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11000 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11001 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11002 BNX2X_ERR("BAD MCP validity signature\n");
11003
11004 if (!BP_NOMCP(bp)) {
11005 bp->fw_seq =
11006 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11007 DRV_MSG_SEQ_NUMBER_MASK);
11008 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11009 }
11010 }
11011
11012 /**
11013 * bnx2x_io_error_detected - called when PCI error is detected
11014 * @pdev: Pointer to PCI device
11015 * @state: The current pci connection state
11016 *
11017 * This function is called after a PCI bus error affecting
11018 * this device has been detected.
11019 */
11020 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11021 pci_channel_state_t state)
11022 {
11023 struct net_device *dev = pci_get_drvdata(pdev);
11024 struct bnx2x *bp = netdev_priv(dev);
11025
11026 rtnl_lock();
11027
11028 netif_device_detach(dev);
11029
11030 if (state == pci_channel_io_perm_failure) {
11031 rtnl_unlock();
11032 return PCI_ERS_RESULT_DISCONNECT;
11033 }
11034
11035 if (netif_running(dev))
11036 bnx2x_eeh_nic_unload(bp);
11037
11038 pci_disable_device(pdev);
11039
11040 rtnl_unlock();
11041
11042 /* Request a slot reset */
11043 return PCI_ERS_RESULT_NEED_RESET;
11044 }
11045
11046 /**
11047 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11048 * @pdev: Pointer to PCI device
11049 *
11050 * Restart the card from scratch, as if from a cold-boot.
11051 */
11052 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11053 {
11054 struct net_device *dev = pci_get_drvdata(pdev);
11055 struct bnx2x *bp = netdev_priv(dev);
11056
11057 rtnl_lock();
11058
11059 if (pci_enable_device(pdev)) {
11060 dev_err(&pdev->dev,
11061 "Cannot re-enable PCI device after reset\n");
11062 rtnl_unlock();
11063 return PCI_ERS_RESULT_DISCONNECT;
11064 }
11065
11066 pci_set_master(pdev);
11067 pci_restore_state(pdev);
11068
11069 if (netif_running(dev))
11070 bnx2x_set_power_state(bp, PCI_D0);
11071
11072 rtnl_unlock();
11073
11074 return PCI_ERS_RESULT_RECOVERED;
11075 }
11076
11077 /**
11078 * bnx2x_io_resume - called when traffic can start flowing again
11079 * @pdev: Pointer to PCI device
11080 *
11081 * This callback is called when the error recovery driver tells us that
11082 * its OK to resume normal operation.
11083 */
11084 static void bnx2x_io_resume(struct pci_dev *pdev)
11085 {
11086 struct net_device *dev = pci_get_drvdata(pdev);
11087 struct bnx2x *bp = netdev_priv(dev);
11088
11089 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11090 netdev_err(bp->dev, "Handling parity error recovery. "
11091 "Try again later\n");
11092 return;
11093 }
11094
11095 rtnl_lock();
11096
11097 bnx2x_eeh_recover(bp);
11098
11099 if (netif_running(dev))
11100 bnx2x_nic_load(bp, LOAD_NORMAL);
11101
11102 netif_device_attach(dev);
11103
11104 rtnl_unlock();
11105 }
11106
11107 static struct pci_error_handlers bnx2x_err_handler = {
11108 .error_detected = bnx2x_io_error_detected,
11109 .slot_reset = bnx2x_io_slot_reset,
11110 .resume = bnx2x_io_resume,
11111 };
11112
11113 static struct pci_driver bnx2x_pci_driver = {
11114 .name = DRV_MODULE_NAME,
11115 .id_table = bnx2x_pci_tbl,
11116 .probe = bnx2x_init_one,
11117 .remove = __devexit_p(bnx2x_remove_one),
11118 .suspend = bnx2x_suspend,
11119 .resume = bnx2x_resume,
11120 .err_handler = &bnx2x_err_handler,
11121 };
11122
11123 static int __init bnx2x_init(void)
11124 {
11125 int ret;
11126
11127 pr_info("%s", version);
11128
11129 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11130 if (bnx2x_wq == NULL) {
11131 pr_err("Cannot create workqueue\n");
11132 return -ENOMEM;
11133 }
11134
11135 ret = pci_register_driver(&bnx2x_pci_driver);
11136 if (ret) {
11137 pr_err("Cannot register driver\n");
11138 destroy_workqueue(bnx2x_wq);
11139 }
11140 return ret;
11141 }
11142
11143 static void __exit bnx2x_cleanup(void)
11144 {
11145 pci_unregister_driver(&bnx2x_pci_driver);
11146
11147 destroy_workqueue(bnx2x_wq);
11148 }
11149
11150 void bnx2x_notify_link_changed(struct bnx2x *bp)
11151 {
11152 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11153 }
11154
11155 module_init(bnx2x_init);
11156 module_exit(bnx2x_cleanup);
11157
11158 #ifdef BCM_CNIC
11159 /**
11160 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11161 *
11162 * @bp: driver handle
11163 * @set: set or clear the CAM entry
11164 *
11165 * This function will wait until the ramdord completion returns.
11166 * Return 0 if success, -ENODEV if ramrod doesn't return.
11167 */
11168 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11169 {
11170 unsigned long ramrod_flags = 0;
11171
11172 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11173 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11174 &bp->iscsi_l2_mac_obj, true,
11175 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11176 }
11177
11178 /* count denotes the number of new completions we have seen */
11179 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11180 {
11181 struct eth_spe *spe;
11182
11183 #ifdef BNX2X_STOP_ON_ERROR
11184 if (unlikely(bp->panic))
11185 return;
11186 #endif
11187
11188 spin_lock_bh(&bp->spq_lock);
11189 BUG_ON(bp->cnic_spq_pending < count);
11190 bp->cnic_spq_pending -= count;
11191
11192
11193 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11194 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11195 & SPE_HDR_CONN_TYPE) >>
11196 SPE_HDR_CONN_TYPE_SHIFT;
11197 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11198 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11199
11200 /* Set validation for iSCSI L2 client before sending SETUP
11201 * ramrod
11202 */
11203 if (type == ETH_CONNECTION_TYPE) {
11204 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11205 bnx2x_set_ctx_validation(bp, &bp->context.
11206 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11207 BNX2X_ISCSI_ETH_CID);
11208 }
11209
11210 /*
11211 * There may be not more than 8 L2, not more than 8 L5 SPEs
11212 * and in the air. We also check that number of outstanding
11213 * COMMON ramrods is not more than the EQ and SPQ can
11214 * accommodate.
11215 */
11216 if (type == ETH_CONNECTION_TYPE) {
11217 if (!atomic_read(&bp->cq_spq_left))
11218 break;
11219 else
11220 atomic_dec(&bp->cq_spq_left);
11221 } else if (type == NONE_CONNECTION_TYPE) {
11222 if (!atomic_read(&bp->eq_spq_left))
11223 break;
11224 else
11225 atomic_dec(&bp->eq_spq_left);
11226 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11227 (type == FCOE_CONNECTION_TYPE)) {
11228 if (bp->cnic_spq_pending >=
11229 bp->cnic_eth_dev.max_kwqe_pending)
11230 break;
11231 else
11232 bp->cnic_spq_pending++;
11233 } else {
11234 BNX2X_ERR("Unknown SPE type: %d\n", type);
11235 bnx2x_panic();
11236 break;
11237 }
11238
11239 spe = bnx2x_sp_get_next(bp);
11240 *spe = *bp->cnic_kwq_cons;
11241
11242 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11243 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11244
11245 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11246 bp->cnic_kwq_cons = bp->cnic_kwq;
11247 else
11248 bp->cnic_kwq_cons++;
11249 }
11250 bnx2x_sp_prod_update(bp);
11251 spin_unlock_bh(&bp->spq_lock);
11252 }
11253
11254 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11255 struct kwqe_16 *kwqes[], u32 count)
11256 {
11257 struct bnx2x *bp = netdev_priv(dev);
11258 int i;
11259
11260 #ifdef BNX2X_STOP_ON_ERROR
11261 if (unlikely(bp->panic))
11262 return -EIO;
11263 #endif
11264
11265 spin_lock_bh(&bp->spq_lock);
11266
11267 for (i = 0; i < count; i++) {
11268 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11269
11270 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11271 break;
11272
11273 *bp->cnic_kwq_prod = *spe;
11274
11275 bp->cnic_kwq_pending++;
11276
11277 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11278 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11279 spe->data.update_data_addr.hi,
11280 spe->data.update_data_addr.lo,
11281 bp->cnic_kwq_pending);
11282
11283 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11284 bp->cnic_kwq_prod = bp->cnic_kwq;
11285 else
11286 bp->cnic_kwq_prod++;
11287 }
11288
11289 spin_unlock_bh(&bp->spq_lock);
11290
11291 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11292 bnx2x_cnic_sp_post(bp, 0);
11293
11294 return i;
11295 }
11296
11297 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11298 {
11299 struct cnic_ops *c_ops;
11300 int rc = 0;
11301
11302 mutex_lock(&bp->cnic_mutex);
11303 c_ops = rcu_dereference_protected(bp->cnic_ops,
11304 lockdep_is_held(&bp->cnic_mutex));
11305 if (c_ops)
11306 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11307 mutex_unlock(&bp->cnic_mutex);
11308
11309 return rc;
11310 }
11311
11312 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11313 {
11314 struct cnic_ops *c_ops;
11315 int rc = 0;
11316
11317 rcu_read_lock();
11318 c_ops = rcu_dereference(bp->cnic_ops);
11319 if (c_ops)
11320 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11321 rcu_read_unlock();
11322
11323 return rc;
11324 }
11325
11326 /*
11327 * for commands that have no data
11328 */
11329 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11330 {
11331 struct cnic_ctl_info ctl = {0};
11332
11333 ctl.cmd = cmd;
11334
11335 return bnx2x_cnic_ctl_send(bp, &ctl);
11336 }
11337
11338 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11339 {
11340 struct cnic_ctl_info ctl = {0};
11341
11342 /* first we tell CNIC and only then we count this as a completion */
11343 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11344 ctl.data.comp.cid = cid;
11345 ctl.data.comp.error = err;
11346
11347 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11348 bnx2x_cnic_sp_post(bp, 0);
11349 }
11350
11351
11352 /* Called with netif_addr_lock_bh() taken.
11353 * Sets an rx_mode config for an iSCSI ETH client.
11354 * Doesn't block.
11355 * Completion should be checked outside.
11356 */
11357 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11358 {
11359 unsigned long accept_flags = 0, ramrod_flags = 0;
11360 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11361 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11362
11363 if (start) {
11364 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11365 * because it's the only way for UIO Queue to accept
11366 * multicasts (in non-promiscuous mode only one Queue per
11367 * function will receive multicast packets (leading in our
11368 * case).
11369 */
11370 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11371 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11372 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11373 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11374
11375 /* Clear STOP_PENDING bit if START is requested */
11376 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11377
11378 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11379 } else
11380 /* Clear START_PENDING bit if STOP is requested */
11381 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11382
11383 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11384 set_bit(sched_state, &bp->sp_state);
11385 else {
11386 __set_bit(RAMROD_RX, &ramrod_flags);
11387 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11388 ramrod_flags);
11389 }
11390 }
11391
11392
11393 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11394 {
11395 struct bnx2x *bp = netdev_priv(dev);
11396 int rc = 0;
11397
11398 switch (ctl->cmd) {
11399 case DRV_CTL_CTXTBL_WR_CMD: {
11400 u32 index = ctl->data.io.offset;
11401 dma_addr_t addr = ctl->data.io.dma_addr;
11402
11403 bnx2x_ilt_wr(bp, index, addr);
11404 break;
11405 }
11406
11407 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11408 int count = ctl->data.credit.credit_count;
11409
11410 bnx2x_cnic_sp_post(bp, count);
11411 break;
11412 }
11413
11414 /* rtnl_lock is held. */
11415 case DRV_CTL_START_L2_CMD: {
11416 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11417 unsigned long sp_bits = 0;
11418
11419 /* Configure the iSCSI classification object */
11420 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11421 cp->iscsi_l2_client_id,
11422 cp->iscsi_l2_cid, BP_FUNC(bp),
11423 bnx2x_sp(bp, mac_rdata),
11424 bnx2x_sp_mapping(bp, mac_rdata),
11425 BNX2X_FILTER_MAC_PENDING,
11426 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11427 &bp->macs_pool);
11428
11429 /* Set iSCSI MAC address */
11430 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11431 if (rc)
11432 break;
11433
11434 mmiowb();
11435 barrier();
11436
11437 /* Start accepting on iSCSI L2 ring */
11438
11439 netif_addr_lock_bh(dev);
11440 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11441 netif_addr_unlock_bh(dev);
11442
11443 /* bits to wait on */
11444 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11445 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11446
11447 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11448 BNX2X_ERR("rx_mode completion timed out!\n");
11449
11450 break;
11451 }
11452
11453 /* rtnl_lock is held. */
11454 case DRV_CTL_STOP_L2_CMD: {
11455 unsigned long sp_bits = 0;
11456
11457 /* Stop accepting on iSCSI L2 ring */
11458 netif_addr_lock_bh(dev);
11459 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11460 netif_addr_unlock_bh(dev);
11461
11462 /* bits to wait on */
11463 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11464 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11465
11466 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11467 BNX2X_ERR("rx_mode completion timed out!\n");
11468
11469 mmiowb();
11470 barrier();
11471
11472 /* Unset iSCSI L2 MAC */
11473 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11474 BNX2X_ISCSI_ETH_MAC, true);
11475 break;
11476 }
11477 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11478 int count = ctl->data.credit.credit_count;
11479
11480 smp_mb__before_atomic_inc();
11481 atomic_add(count, &bp->cq_spq_left);
11482 smp_mb__after_atomic_inc();
11483 break;
11484 }
11485
11486 default:
11487 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11488 rc = -EINVAL;
11489 }
11490
11491 return rc;
11492 }
11493
11494 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11495 {
11496 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11497
11498 if (bp->flags & USING_MSIX_FLAG) {
11499 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11500 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11501 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11502 } else {
11503 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11504 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11505 }
11506 if (!CHIP_IS_E1x(bp))
11507 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11508 else
11509 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11510
11511 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11512 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11513 cp->irq_arr[1].status_blk = bp->def_status_blk;
11514 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11515 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11516
11517 cp->num_irq = 2;
11518 }
11519
11520 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11521 void *data)
11522 {
11523 struct bnx2x *bp = netdev_priv(dev);
11524 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11525
11526 if (ops == NULL)
11527 return -EINVAL;
11528
11529 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11530 if (!bp->cnic_kwq)
11531 return -ENOMEM;
11532
11533 bp->cnic_kwq_cons = bp->cnic_kwq;
11534 bp->cnic_kwq_prod = bp->cnic_kwq;
11535 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11536
11537 bp->cnic_spq_pending = 0;
11538 bp->cnic_kwq_pending = 0;
11539
11540 bp->cnic_data = data;
11541
11542 cp->num_irq = 0;
11543 cp->drv_state |= CNIC_DRV_STATE_REGD;
11544 cp->iro_arr = bp->iro_arr;
11545
11546 bnx2x_setup_cnic_irq_info(bp);
11547
11548 rcu_assign_pointer(bp->cnic_ops, ops);
11549
11550 return 0;
11551 }
11552
11553 static int bnx2x_unregister_cnic(struct net_device *dev)
11554 {
11555 struct bnx2x *bp = netdev_priv(dev);
11556 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11557
11558 mutex_lock(&bp->cnic_mutex);
11559 cp->drv_state = 0;
11560 rcu_assign_pointer(bp->cnic_ops, NULL);
11561 mutex_unlock(&bp->cnic_mutex);
11562 synchronize_rcu();
11563 kfree(bp->cnic_kwq);
11564 bp->cnic_kwq = NULL;
11565
11566 return 0;
11567 }
11568
11569 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11570 {
11571 struct bnx2x *bp = netdev_priv(dev);
11572 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11573
11574 /* If both iSCSI and FCoE are disabled - return NULL in
11575 * order to indicate CNIC that it should not try to work
11576 * with this device.
11577 */
11578 if (NO_ISCSI(bp) && NO_FCOE(bp))
11579 return NULL;
11580
11581 cp->drv_owner = THIS_MODULE;
11582 cp->chip_id = CHIP_ID(bp);
11583 cp->pdev = bp->pdev;
11584 cp->io_base = bp->regview;
11585 cp->io_base2 = bp->doorbells;
11586 cp->max_kwqe_pending = 8;
11587 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11588 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11589 bnx2x_cid_ilt_lines(bp);
11590 cp->ctx_tbl_len = CNIC_ILT_LINES;
11591 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11592 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11593 cp->drv_ctl = bnx2x_drv_ctl;
11594 cp->drv_register_cnic = bnx2x_register_cnic;
11595 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11596 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11597 cp->iscsi_l2_client_id =
11598 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11599 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11600
11601 if (NO_ISCSI_OOO(bp))
11602 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11603
11604 if (NO_ISCSI(bp))
11605 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11606
11607 if (NO_FCOE(bp))
11608 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11609
11610 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11611 "starting cid %d\n",
11612 cp->ctx_blk_size,
11613 cp->ctx_tbl_offset,
11614 cp->ctx_tbl_len,
11615 cp->starting_cid);
11616 return cp;
11617 }
11618 EXPORT_SYMBOL(bnx2x_cnic_probe);
11619
11620 #endif /* BCM_CNIC */
11621
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