2 * arch/ppc/platforms/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002 MontaVista Software Inc.
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/types.h>
27 #include <linux/major.h>
28 #include <linux/blkdev.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/initrd.h>
33 #include <linux/irq.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
40 #include <asm/system.h>
41 #include <asm/pgtable.h>
45 #include <asm/machdep.h>
47 #include <asm/pci-bridge.h>
50 #include <asm/bootinfo.h>
51 #include <asm/ppc4xx_pic.h>
54 * Ebony IRQ triggering/polarity settings
56 static u_char ebony_IRQ_initsenses
[] __initdata
= {
57 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 0: UART 0 */
58 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 1: UART 1 */
59 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 2: IIC 0 */
60 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 3: IIC 1 */
61 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 4: PCI Inb Mess */
62 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 5: PCI Cmd Wrt */
63 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 6: PCI PM */
64 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 7: PCI MSI 0 */
65 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 8: PCI MSI 1 */
66 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 9: PCI MSI 2 */
67 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 10: MAL TX EOB */
68 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 11: MAL RX EOB */
69 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 12: DMA Chan 0 */
70 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 13: DMA Chan 1 */
71 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 14: DMA Chan 2 */
72 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 15: DMA Chan 3 */
73 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 16: Reserved */
74 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 17: Reserved */
75 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 18: GPT Timer 0 */
76 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 19: GPT Timer 1 */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 20: GPT Timer 2 */
78 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 21: GPT Timer 3 */
79 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 22: GPT Timer 4 */
80 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 23: Ext Int 0 */
81 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 24: Ext Int 1 */
82 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 25: Ext Int 2 */
83 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 26: Ext Int 3 */
84 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 27: Ext Int 4 */
85 (IRQ_SENSE_EDGE
| IRQ_POLARITY_NEGATIVE
), /* 28: Ext Int 5 */
86 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 29: Ext Int 6 */
87 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 30: UIC1 NC Int */
88 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 31: UIC1 Crit Int */
89 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 32: MAL SERR */
90 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 33: MAL TXDE */
91 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 34: MAL RXDE */
92 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 35: ECC Unc Err */
93 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 36: ECC Corr Err */
94 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 37: Ext Bus Ctrl */
95 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 38: Ext Bus Mstr */
96 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 39: OPB->PLB */
97 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 40: PCI MSI 3 */
98 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 41: PCI MSI 4 */
99 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 42: PCI MSI 5 */
100 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 43: PCI MSI 6 */
101 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 44: PCI MSI 7 */
102 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 45: PCI MSI 8 */
103 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 46: PCI MSI 9 */
104 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 47: PCI MSI 10 */
105 (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE
), /* 48: PCI MSI 11 */
106 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 49: PLB Perf Mon */
107 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 50: Ext Int 7 */
108 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 51: Ext Int 8 */
109 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 52: Ext Int 9 */
110 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 53: Ext Int 10 */
111 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 54: Ext Int 11 */
112 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* 55: Ext Int 12 */
113 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 56: Ser ROM Err */
114 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 57: Reserved */
115 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 58: Reserved */
116 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 59: PCI Async Err */
117 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 60: EMAC 0 */
118 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 61: EMAC 0 WOL */
119 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 62: EMAC 1 */
120 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* 63: EMAC 1 WOL */
123 static struct ibm44x_clocks clocks __initdata
;
126 ebony_calibrate_decr(void)
131 * Determine system clock speed
133 * If we are on Rev. B silicon, then use
134 * default external system clock. If we are
135 * on Rev. C silicon then errata forces us to
136 * use the internal clock.
138 switch (PVR_REV(mfspr(PVR
))) {
139 case PVR_REV(PVR_440GP_RB
):
140 freq
= EBONY_440GP_RB_SYSCLK
;
142 case PVR_REV(PVR_440GP_RC1
):
144 freq
= EBONY_440GP_RC_SYSCLK
;
148 ibm44x_calibrate_decr(freq
);
152 ebony_show_cpuinfo(struct seq_file
*m
)
154 seq_printf(m
, "vendor\t\t: IBM\n");
155 seq_printf(m
, "machine\t\t: Ebony\n");
161 ebony_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
163 static char pci_irq_table
[][4] =
165 * PCI IDSEL/INTPIN->INTLINE
169 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
170 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
171 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
172 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
175 const long min_idsel
= 1, max_idsel
= 4, irqs_per_slot
= 4;
176 return PCI_IRQ_TABLE_LOOKUP
;
179 #define PCIX_WRITEL(value, offset) \
180 (writel(value, (u32)pcix_reg_base+offset))
183 * FIXME: This is only here to "make it work". This will move
184 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
185 * configuration library. -Matt
188 ebony_setup_pcix(void)
192 pcix_reg_base
= ioremap64(PCIX0_REG_BASE
, PCIX0_REG_SIZE
);
194 /* Disable all windows */
195 PCIX_WRITEL(0, PCIX0_POM0SA
);
196 PCIX_WRITEL(0, PCIX0_POM1SA
);
197 PCIX_WRITEL(0, PCIX0_POM2SA
);
198 PCIX_WRITEL(0, PCIX0_PIM0SA
);
199 PCIX_WRITEL(0, PCIX0_PIM1SA
);
200 PCIX_WRITEL(0, PCIX0_PIM2SA
);
202 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
203 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH
);
204 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL
);
205 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH
);
206 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL
);
207 PCIX_WRITEL(0x80000001, PCIX0_POM0SA
);
209 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
210 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH
);
211 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL
);
212 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA
);
218 ebony_setup_hose(void)
220 struct pci_controller
*hose
;
222 /* Configure windows on the PCI-X host bridge */
225 hose
= pcibios_alloc_controller();
230 hose
->first_busno
= 0;
231 hose
->last_busno
= 0xff;
233 hose
->pci_mem_offset
= EBONY_PCI_MEM_OFFSET
;
235 pci_init_resource(&hose
->io_resource
,
241 pci_init_resource(&hose
->mem_resources
[0],
247 hose
->io_space
.start
= EBONY_PCI_LOWER_IO
;
248 hose
->io_space
.end
= EBONY_PCI_UPPER_IO
;
249 hose
->mem_space
.start
= EBONY_PCI_LOWER_MEM
;
250 hose
->mem_space
.end
= EBONY_PCI_UPPER_MEM
;
252 (unsigned long)ioremap64(EBONY_PCI_IO_BASE
, EBONY_PCI_IO_SIZE
);
253 hose
->io_base_virt
= (void *)isa_io_base
;
255 setup_indirect_pci(hose
,
256 EBONY_PCI_CFGA_PLB32
,
257 EBONY_PCI_CFGD_PLB32
);
258 hose
->set_cfg_type
= 1;
260 hose
->last_busno
= pciauto_bus_scan(hose
, hose
->first_busno
);
262 ppc_md
.pci_swizzle
= common_swizzle
;
263 ppc_md
.pci_map_irq
= ebony_map_irq
;
269 ebony_early_serial_map(void)
271 struct uart_port port
;
273 /* Setup ioremapped serial port access */
274 memset(&port
, 0, sizeof(port
));
275 port
.membase
= ioremap64(PPC440GP_UART0_ADDR
, 8);
277 port
.uartclk
= clocks
.uart0
;
279 port
.iotype
= SERIAL_IO_MEM
;
280 port
.flags
= ASYNC_BOOT_AUTOCONF
| ASYNC_SKIP_TEST
;
283 if (early_serial_setup(&port
) != 0) {
284 printk("Early serial init of port 0 failed\n");
287 port
.membase
= ioremap64(PPC440GP_UART1_ADDR
, 8);
291 if (early_serial_setup(&port
) != 0) {
292 printk("Early serial init of port 1 failed\n");
297 ebony_setup_arch(void)
299 unsigned char * vpd_base
;
301 struct ocp_func_emac_data
*emacdata
;
303 #if !defined(CONFIG_BDI_SWITCH)
305 * The Abatron BDI JTAG debugger does not tolerate others
306 * mucking with the debug registers.
308 mtspr(SPRN_DBCR0
, (DBCR0_TDE
| DBCR0_IDM
));
311 /* Set mac_addr for each EMAC */
312 vpd_base
= ioremap64(EBONY_VPD_BASE
, EBONY_VPD_SIZE
);
313 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 0);
314 emacdata
= def
->additions
;
315 memcpy(emacdata
->mac_addr
, EBONY_NA0_ADDR(vpd_base
), 6);
316 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 1);
317 emacdata
= def
->additions
;
318 memcpy(emacdata
->mac_addr
, EBONY_NA1_ADDR(vpd_base
), 6);
322 * Determine various clocks.
323 * To be completely correct we should get SysClk
324 * from FPGA, because it can be changed by on-board switches
327 ibm440gp_get_clocks(&clocks
, 33333333, 6 * 1843200);
328 ocp_sys_info
.opb_bus_freq
= clocks
.opb
;
330 /* Setup TODC access */
331 TODC_INIT(TODC_TYPE_DS1743
,
334 ioremap64(EBONY_RTC_ADDR
, EBONY_RTC_SIZE
),
337 /* init to some ~sane value until calibrate_delay() runs */
338 loops_per_jiffy
= 50000000/HZ
;
340 /* Setup PCI host bridge */
343 #ifdef CONFIG_BLK_DEV_INITRD
345 ROOT_DEV
= Root_RAM0
;
348 #ifdef CONFIG_ROOT_NFS
351 ROOT_DEV
= Root_HDA1
;
354 ebony_early_serial_map();
356 ibm4xxPIC_InitSenses
= ebony_IRQ_initsenses
;
357 ibm4xxPIC_NumInitSenses
= sizeof(ebony_IRQ_initsenses
);
359 /* Identify the system */
360 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
363 void __init
platform_init(unsigned long r3
, unsigned long r4
,
364 unsigned long r5
, unsigned long r6
, unsigned long r7
)
366 parse_bootinfo((struct bi_record
*) (r3
+ KERNELBASE
));
368 ibm44x_platform_init();
370 ppc_md
.setup_arch
= ebony_setup_arch
;
371 ppc_md
.show_cpuinfo
= ebony_show_cpuinfo
;
372 ppc_md
.get_irq
= NULL
; /* Set in ppc4xx_pic_init() */
374 ppc_md
.calibrate_decr
= ebony_calibrate_decr
;
375 ppc_md
.time_init
= todc_time_init
;
376 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
377 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
379 ppc_md
.nvram_read_val
= todc_direct_read_val
;
380 ppc_md
.nvram_write_val
= todc_direct_write_val
;
383 ppc_md
.early_serial_map
= ebony_early_serial_map
;