2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
8 * Copyright (C) 1999 VA Linux Systems
9 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
11 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
12 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
13 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
14 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
15 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
16 * 01/07/99 S.Eranian added the support for command line argument
17 * 06/24/99 W.Drummond added boot_cpu_data.
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
23 #include <linux/acpi.h>
24 #include <linux/bootmem.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/kernel.h>
28 #include <linux/reboot.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
31 #include <linux/string.h>
32 #include <linux/threads.h>
33 #include <linux/tty.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/efi.h>
37 #include <linux/initrd.h>
40 #include <asm/machvec.h>
42 #include <asm/meminit.h>
44 #include <asm/patch.h>
45 #include <asm/pgtable.h>
46 #include <asm/processor.h>
48 #include <asm/sections.h>
49 #include <asm/serial.h>
50 #include <asm/setup.h>
52 #include <asm/system.h>
53 #include <asm/unistd.h>
55 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
56 # error "struct cpuinfo_ia64 too big!"
60 unsigned long __per_cpu_offset
[NR_CPUS
];
61 EXPORT_SYMBOL(__per_cpu_offset
);
64 DEFINE_PER_CPU(struct cpuinfo_ia64
, cpu_info
);
65 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset
);
66 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8
);
67 unsigned long ia64_cycles_per_usec
;
68 struct ia64_boot_param
*ia64_boot_param
;
69 struct screen_info screen_info
;
71 unsigned long ia64_max_cacheline_size
;
72 unsigned long ia64_iobase
; /* virtual address for I/O accesses */
73 EXPORT_SYMBOL(ia64_iobase
);
74 struct io_space io_space
[MAX_IO_SPACES
];
75 EXPORT_SYMBOL(io_space
);
76 unsigned int num_io_spaces
;
78 unsigned char aux_device_present
= 0xaa; /* XXX remove this when legacy I/O is gone */
81 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
82 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
83 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
84 * address of the second buffer must be aligned to (merge_mask+1) in order to be
85 * mergeable). By default, we assume there is no I/O MMU which can merge physically
86 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
89 unsigned long ia64_max_iommu_merge_mask
= ~0UL;
90 EXPORT_SYMBOL(ia64_max_iommu_merge_mask
);
93 * We use a special marker for the end of memory and it uses the extra (+1) slot
95 struct rsvd_region rsvd_region
[IA64_MAX_RSVD_REGIONS
+ 1];
100 * Filter incoming memory segments based on the primitive map created from the boot
101 * parameters. Segments contained in the map are removed from the memory ranges. A
102 * caller-specified function is called with the memory ranges that remain after filtering.
103 * This routine does not assume the incoming segments are sorted.
106 filter_rsvd_memory (unsigned long start
, unsigned long end
, void *arg
)
108 unsigned long range_start
, range_end
, prev_start
;
109 void (*func
)(unsigned long, unsigned long, int);
113 if (start
== PAGE_OFFSET
) {
114 printk(KERN_WARNING
"warning: skipping physical page 0\n");
116 if (start
>= end
) return 0;
120 * lowest possible address(walker uses virtual)
122 prev_start
= PAGE_OFFSET
;
125 for (i
= 0; i
< num_rsvd_regions
; ++i
) {
126 range_start
= max(start
, prev_start
);
127 range_end
= min(end
, rsvd_region
[i
].start
);
129 if (range_start
< range_end
)
130 call_pernode_memory(__pa(range_start
), range_end
- range_start
, func
);
132 /* nothing more available in this segment */
133 if (range_end
== end
) return 0;
135 prev_start
= rsvd_region
[i
].end
;
137 /* end of memory marker allows full processing inside loop body */
142 sort_regions (struct rsvd_region
*rsvd_region
, int max
)
146 /* simple bubble sorting */
148 for (j
= 0; j
< max
; ++j
) {
149 if (rsvd_region
[j
].start
> rsvd_region
[j
+1].start
) {
150 struct rsvd_region tmp
;
151 tmp
= rsvd_region
[j
];
152 rsvd_region
[j
] = rsvd_region
[j
+ 1];
153 rsvd_region
[j
+ 1] = tmp
;
160 * reserve_memory - setup reserved memory areas
162 * Setup the reserved memory areas set aside for the boot parameters,
163 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
164 * see include/asm-ia64/meminit.h if you need to define more.
167 reserve_memory (void)
172 * none of the entries in this table overlap
174 rsvd_region
[n
].start
= (unsigned long) ia64_boot_param
;
175 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ sizeof(*ia64_boot_param
);
178 rsvd_region
[n
].start
= (unsigned long) __va(ia64_boot_param
->efi_memmap
);
179 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ ia64_boot_param
->efi_memmap_size
;
182 rsvd_region
[n
].start
= (unsigned long) __va(ia64_boot_param
->command_line
);
183 rsvd_region
[n
].end
= (rsvd_region
[n
].start
184 + strlen(__va(ia64_boot_param
->command_line
)) + 1);
187 rsvd_region
[n
].start
= (unsigned long) ia64_imva((void *)KERNEL_START
);
188 rsvd_region
[n
].end
= (unsigned long) ia64_imva(_end
);
191 #ifdef CONFIG_BLK_DEV_INITRD
192 if (ia64_boot_param
->initrd_start
) {
193 rsvd_region
[n
].start
= (unsigned long)__va(ia64_boot_param
->initrd_start
);
194 rsvd_region
[n
].end
= rsvd_region
[n
].start
+ ia64_boot_param
->initrd_size
;
199 /* end of memory marker */
200 rsvd_region
[n
].start
= ~0UL;
201 rsvd_region
[n
].end
= ~0UL;
204 num_rsvd_regions
= n
;
206 sort_regions(rsvd_region
, num_rsvd_regions
);
210 * find_initrd - get initrd parameters from the boot parameter structure
212 * Grab the initrd start and end from the boot parameter struct given us by
218 #ifdef CONFIG_BLK_DEV_INITRD
219 if (ia64_boot_param
->initrd_start
) {
220 initrd_start
= (unsigned long)__va(ia64_boot_param
->initrd_start
);
221 initrd_end
= initrd_start
+ia64_boot_param
->initrd_size
;
223 printk(KERN_INFO
"Initial ramdisk at: 0x%lx (%lu bytes)\n",
224 initrd_start
, ia64_boot_param
->initrd_size
);
232 extern unsigned long ia64_iobase
;
233 unsigned long phys_iobase
;
236 * Set `iobase' to the appropriate address in region 6 (uncached access range).
238 * The EFI memory map is the "preferred" location to get the I/O port space base,
239 * rather the relying on AR.KR0. This should become more clear in future SAL
240 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
241 * found in the memory map.
243 phys_iobase
= efi_get_iobase();
245 /* set AR.KR0 since this is all we use it for anyway */
246 ia64_set_kr(IA64_KR_IO_BASE
, phys_iobase
);
248 phys_iobase
= ia64_get_kr(IA64_KR_IO_BASE
);
249 printk(KERN_INFO
"No I/O port range found in EFI memory map, falling back "
251 printk(KERN_INFO
"I/O port base = 0x%lx\n", phys_iobase
);
253 ia64_iobase
= (unsigned long) ioremap(phys_iobase
, 0);
255 /* setup legacy IO port space */
256 io_space
[0].mmio_base
= ia64_iobase
;
257 io_space
[0].sparse
= 1;
261 #ifdef CONFIG_SERIAL_8250_CONSOLE
263 setup_serial_legacy (void)
265 struct uart_port port
;
266 unsigned int i
, iobase
[] = {0x3f8, 0x2f8};
268 printk(KERN_INFO
"Registering legacy COM ports for serial console\n");
269 memset(&port
, 0, sizeof(port
));
270 port
.iotype
= SERIAL_IO_PORT
;
271 port
.uartclk
= BASE_BAUD
* 16;
272 for (i
= 0; i
< ARRAY_SIZE(iobase
); i
++) {
274 port
.iobase
= iobase
[i
];
275 early_serial_setup(&port
);
281 * early_console_setup - setup debugging console
283 * Consoles started here require little enough setup that we can start using
284 * them very early in the boot process, either right after the machine
285 * vector initialization, or even before if the drivers can detect their hw.
287 * Returns non-zero if a console couldn't be setup.
289 static inline int __init
290 early_console_setup (void)
292 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
294 extern int sn_serial_console_early_setup(void);
295 if(!sn_serial_console_early_setup())
304 setup_arch (char **cmdline_p
)
308 ia64_patch_vtop((u64
) __start___vtop_patchlist
, (u64
) __end___vtop_patchlist
);
310 *cmdline_p
= __va(ia64_boot_param
->command_line
);
311 strlcpy(saved_command_line
, *cmdline_p
, COMMAND_LINE_SIZE
);
316 #ifdef CONFIG_IA64_GENERIC
317 machvec_init(acpi_get_sysname());
321 /* If we register an early console, allow CPU 0 to printk */
322 if (!early_console_setup())
323 cpu_set(smp_processor_id(), cpu_online_map
);
326 #ifdef CONFIG_ACPI_BOOT
327 /* Initialize the ACPI boot-time table parser */
329 # ifdef CONFIG_ACPI_NUMA
334 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
336 #endif /* CONFIG_APCI_BOOT */
340 /* process SAL system table: */
341 ia64_sal_init(efi
.sal_systab
);
344 cpu_physical_id(0) = hard_smp_processor_id();
347 cpu_init(); /* initialize the bootstrap CPU */
349 #ifdef CONFIG_ACPI_BOOT
352 #ifdef CONFIG_EFI_PCDP
353 efi_setup_pcdp_console(*cmdline_p
);
355 #ifdef CONFIG_SERIAL_8250_CONSOLE
357 setup_serial_legacy();
362 # if defined(CONFIG_DUMMY_CONSOLE)
363 conswitchp
= &dummy_con
;
365 # if defined(CONFIG_VGA_CONSOLE)
367 * Non-legacy systems may route legacy VGA MMIO range to system
368 * memory. vga_con probes the MMIO hole, so memory looks like
369 * a VGA device to it. The EFI memory map can tell us if it's
370 * memory so we can avoid this problem.
372 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY
)
373 conswitchp
= &vga_con
;
378 /* enable IA-64 Machine Check Abort Handling unless disabled */
379 if (!strstr(saved_command_line
, "nomca"))
382 platform_setup(cmdline_p
);
387 * Display cpu info for all cpu's.
390 show_cpuinfo (struct seq_file
*m
, void *v
)
393 # define lpj c->loops_per_jiffy
394 # define cpunum c->cpu
396 # define lpj loops_per_jiffy
401 const char *feature_name
;
403 { 1UL << 0, "branchlong" },
404 { 1UL << 1, "spontaneous deferral"},
405 { 1UL << 2, "16-byte atomic ops" }
407 char family
[32], features
[128], *cp
, sep
;
408 struct cpuinfo_ia64
*c
= v
;
415 case 0x07: memcpy(family
, "Itanium", 8); break;
416 case 0x1f: memcpy(family
, "Itanium 2", 10); break;
417 default: sprintf(family
, "%u", c
->family
); break;
420 /* build the feature string: */
421 memcpy(features
, " standard", 10);
424 for (i
= 0; i
< (int) ARRAY_SIZE(feature_bits
); ++i
) {
425 if (mask
& feature_bits
[i
].mask
) {
430 strcpy(cp
, feature_bits
[i
].feature_name
);
431 cp
+= strlen(feature_bits
[i
].feature_name
);
432 mask
&= ~feature_bits
[i
].mask
;
436 /* print unknown features as a hex value: */
439 sprintf(cp
, " 0x%lx", mask
);
450 "features :%s\n" /* don't change this---it _is_ right! */
453 "cpu MHz : %lu.%06lu\n"
454 "itc MHz : %lu.%06lu\n"
455 "BogoMIPS : %lu.%02lu\n\n",
456 cpunum
, c
->vendor
, family
, c
->model
, c
->revision
, c
->archrev
,
457 features
, c
->ppn
, c
->number
,
458 c
->proc_freq
/ 1000000, c
->proc_freq
% 1000000,
459 c
->itc_freq
/ 1000000, c
->itc_freq
% 1000000,
460 lpj
*HZ
/500000, (lpj
*HZ
/5000) % 100);
465 c_start (struct seq_file
*m
, loff_t
*pos
)
468 while (*pos
< NR_CPUS
&& !cpu_isset(*pos
, cpu_online_map
))
471 return *pos
< NR_CPUS
? cpu_data(*pos
) : NULL
;
475 c_next (struct seq_file
*m
, void *v
, loff_t
*pos
)
478 return c_start(m
, pos
);
482 c_stop (struct seq_file
*m
, void *v
)
486 struct seq_operations cpuinfo_op
= {
494 identify_cpu (struct cpuinfo_ia64
*c
)
497 unsigned long bits
[5];
503 u64 ppn
; /* processor serial number */
507 unsigned revision
: 8;
510 unsigned archrev
: 8;
511 unsigned reserved
: 24;
517 pal_vm_info_1_u_t vm1
;
518 pal_vm_info_2_u_t vm2
;
520 unsigned long impl_va_msb
= 50, phys_addr_size
= 44; /* Itanium defaults */
523 for (i
= 0; i
< 5; ++i
)
524 cpuid
.bits
[i
] = ia64_get_cpuid(i
);
526 memcpy(c
->vendor
, cpuid
.field
.vendor
, 16);
528 c
->cpu
= smp_processor_id();
530 c
->ppn
= cpuid
.field
.ppn
;
531 c
->number
= cpuid
.field
.number
;
532 c
->revision
= cpuid
.field
.revision
;
533 c
->model
= cpuid
.field
.model
;
534 c
->family
= cpuid
.field
.family
;
535 c
->archrev
= cpuid
.field
.archrev
;
536 c
->features
= cpuid
.field
.features
;
538 status
= ia64_pal_vm_summary(&vm1
, &vm2
);
539 if (status
== PAL_STATUS_SUCCESS
) {
540 impl_va_msb
= vm2
.pal_vm_info_2_s
.impl_va_msb
;
541 phys_addr_size
= vm1
.pal_vm_info_1_s
.phys_add_size
;
543 c
->unimpl_va_mask
= ~((7L<<61) | ((1L << (impl_va_msb
+ 1)) - 1));
544 c
->unimpl_pa_mask
= ~((1L<<63) | ((1L << phys_addr_size
) - 1));
548 setup_per_cpu_areas (void)
550 /* start_kernel() requires this... */
554 get_max_cacheline_size (void)
556 unsigned long line_size
, max
= 1;
557 u64 l
, levels
, unique_caches
;
558 pal_cache_config_info_t cci
;
561 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
563 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed (status=%ld)\n",
564 __FUNCTION__
, status
);
565 max
= SMP_CACHE_BYTES
;
569 for (l
= 0; l
< levels
; ++l
) {
570 status
= ia64_pal_cache_config_info(l
, /* cache_type (data_or_unified)= */ 2,
574 "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
575 __FUNCTION__
, l
, status
);
576 max
= SMP_CACHE_BYTES
;
578 line_size
= 1 << cci
.pcci_line_size
;
583 if (max
> ia64_max_cacheline_size
)
584 ia64_max_cacheline_size
= max
;
588 * cpu_init() initializes state that is per-CPU. This function acts
589 * as a 'CPU state barrier', nothing should get across.
594 extern void __devinit
ia64_mmu_init (void *);
595 unsigned long num_phys_stacked
;
596 pal_vm_info_2_u_t vmi
;
597 unsigned int max_ctx
;
598 struct cpuinfo_ia64
*cpu_info
;
601 cpu_data
= per_cpu_init();
603 get_max_cacheline_size();
606 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
607 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
608 * depends on the data returned by identify_cpu(). We break the dependency by
609 * accessing cpu_data() through the canonical per-CPU address.
611 cpu_info
= cpu_data
+ ((char *) &__ia64_per_cpu_var(cpu_info
) - __per_cpu_start
);
612 identify_cpu(cpu_info
);
614 #ifdef CONFIG_MCKINLEY
616 # define FEATURE_SET 16
617 struct ia64_pal_retval iprv
;
619 if (cpu_info
->family
== 0x1f) {
620 PAL_CALL_PHYS(iprv
, PAL_PROC_GET_FEATURES
, 0, FEATURE_SET
, 0);
621 if ((iprv
.status
== 0) && (iprv
.v0
& 0x80) && (iprv
.v2
& 0x80))
622 PAL_CALL_PHYS(iprv
, PAL_PROC_SET_FEATURES
,
623 (iprv
.v1
| 0x80), FEATURE_SET
, 0);
628 /* Clear the stack memory reserved for pt_regs: */
629 memset(ia64_task_regs(current
), 0, sizeof(struct pt_regs
));
631 ia64_set_kr(IA64_KR_FPU_OWNER
, 0);
634 * Initialize default control register to defer all speculative faults. The
635 * kernel MUST NOT depend on a particular setting of these bits (in other words,
636 * the kernel must have recovery code for all speculative accesses). Turn on
637 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
638 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
641 ia64_setreg(_IA64_REG_CR_DCR
, ( IA64_DCR_DP
| IA64_DCR_DK
| IA64_DCR_DX
| IA64_DCR_DR
642 | IA64_DCR_DA
| IA64_DCR_DD
| IA64_DCR_LC
));
643 atomic_inc(&init_mm
.mm_count
);
644 current
->active_mm
= &init_mm
;
648 ia64_mmu_init(ia64_imva(cpu_data
));
650 #ifdef CONFIG_IA32_SUPPORT
654 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
657 /* disable all local interrupt sources: */
658 ia64_set_itv(1 << 16);
659 ia64_set_lrr0(1 << 16);
660 ia64_set_lrr1(1 << 16);
661 ia64_setreg(_IA64_REG_CR_PMV
, 1 << 16);
662 ia64_setreg(_IA64_REG_CR_CMCV
, 1 << 16);
664 /* clear TPR & XTP to enable all interrupt classes: */
665 ia64_setreg(_IA64_REG_CR_TPR
, 0);
670 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
671 if (ia64_pal_vm_summary(NULL
, &vmi
) == 0)
672 max_ctx
= (1U << (vmi
.pal_vm_info_2_s
.rid_size
- 3)) - 1;
674 printk(KERN_WARNING
"cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
675 max_ctx
= (1U << 15) - 1; /* use architected minimum */
677 while (max_ctx
< ia64_ctx
.max_ctx
) {
678 unsigned int old
= ia64_ctx
.max_ctx
;
679 if (cmpxchg(&ia64_ctx
.max_ctx
, old
, max_ctx
) == old
)
683 if (ia64_pal_rse_info(&num_phys_stacked
, NULL
) != 0) {
684 printk(KERN_WARNING
"cpu_init: PAL RSE info failed; assuming 96 physical "
686 num_phys_stacked
= 96;
688 /* size of physical stacked register partition plus 8 bytes: */
689 __get_cpu_var(ia64_phys_stacked_size_p8
) = num_phys_stacked
*8 + 8;
696 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles
,
697 (unsigned long) __end___mckinley_e9_bundles
);