2 * linux/arch/arm/lib/copypage.S
4 * Copyright (C) 1995-1999 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * ASM optimised string functions
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/constants.h>
19 * ARMv4 optimised copy_user_page
21 * We flush the destination cache lines just before we write the data into the
22 * corresponding address. Since the Dcache is read-allocate, this removes the
23 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
24 * and merged as appropriate.
26 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
27 * instruction. If your processor does not supply this, you have to write your
28 * own copy_user_page that does the right thing.
30 ENTRY(v4wb_copy_user_page)
31 #if 0 /* mask by Victor Yu. 06-09-2005 */
32 stmfd sp!, {r4, lr} @ 2
33 mov r2, #PAGE_SZ/64 @ 1
34 ldmia r1!, {r3, r4, ip, lr} @ 4
35 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
36 stmia r0!, {r3, r4, ip, lr} @ 4
37 ldmia r1!, {r3, r4, ip, lr} @ 4+1
38 stmia r0!, {r3, r4, ip, lr} @ 4
39 ldmia r1!, {r3, r4, ip, lr} @ 4
40 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
41 stmia r0!, {r3, r4, ip, lr} @ 4
42 ldmia r1!, {r3, r4, ip, lr} @ 4
44 stmia r0!, {r3, r4, ip, lr} @ 4
45 ldmneia r1!, {r3, r4, ip, lr} @ 4
47 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
48 ldmfd sp!, {r4, pc} @ 3
49 #else /* add by Victor Yu. 06-09-2005 */
50 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
52 stmfd sp!, {r4, lr} @ 2
53 mov r2, #PAGE_SZ/32 @ 1
55 ldmia r1!, {r3, r4, ip, lr} @ 4
56 1: stmia r0!, {r3, r4, ip, lr} @ 4
57 ldmia r1!, {r3, r4, ip, lr} @ 4+1
59 stmia r0!, {r3, r4, ip, lr} @ 4
60 ldmneia r1!, {r3, r4, ip, lr} @ 4
63 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache
64 ldmfd sp!, {r4, pc} @ 3
67 stmfd sp!, {r4, lr} @ 2
68 mov r2, #PAGE_SZ/32 @ 1
70 1: ldmia r1!, {r3, r4, ip, lr} @ 4
71 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
72 stmia r0!, {r3, r4, ip, lr} @ 4
73 ldmia r1!, {r3, r4, ip, lr} @ 4
74 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
75 stmia r0!, {r3, r4, ip, lr} @ 4
78 mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB
79 ldmfd sp!, {r4, pc} @ 3
80 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
85 * ARMv4 optimised clear_user_page
87 * Same story as above.
89 ENTRY(v4wb_clear_user_page)
90 #if 0 /* mask by Victor Yu. 06-09-2005 */
92 mov r1, #PAGE_SZ/64 @ 1
97 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
98 stmia r0!, {r2, r3, ip, lr} @ 4
99 stmia r0!, {r2, r3, ip, lr} @ 4
100 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
101 stmia r0!, {r2, r3, ip, lr} @ 4
102 stmia r0!, {r2, r3, ip, lr} @ 4
105 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
107 #else /* add by Victor Yu. 06-09-2005 */
109 mov r1, #PAGE_SZ/32 @ 1
114 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
116 1: stmia r0!, {r2, r3, ip, lr} @ 4
117 stmia r0!, {r2, r3, ip, lr} @ 4
121 mcr p15, 0, r1, c7, c7, 0 @ flush ID cache
125 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
126 stmia r0!, {r2, r3, ip, lr} @ 4
127 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
128 stmia r0!, {r2, r3, ip, lr} @ 4
131 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
133 #endif /* CONFIG_CPU_DCACHE_WRITETHROUGH */
138 .type v4wb_user_fns, #object
140 .long v4wb_clear_user_page
141 .long v4wb_copy_user_page
142 .size v4wb_user_fns, . - v4wb_user_fns