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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / sound / pci / atiixp.c
blob61319fb5963ca471cbb12ae561befcd3bf66ef49
1 /*
2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <sound/driver.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/moduleparam.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/info.h>
34 #include <sound/ac97_codec.h>
35 #include <sound/initval.h>
36
37 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
38 MODULE_DESCRIPTION("ATI IXP AC97 controller");
39 MODULE_LICENSE("GPL");
40 MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400}}");
41
42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
44 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
45 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 48000};
46 static int spdif_aclink[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
47 static int boot_devs;
48
49 module_param_array(index, int, boot_devs, 0444);
50 MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
51 module_param_array(id, charp, boot_devs, 0444);
52 MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
53 module_param_array(enable, bool, boot_devs, 0444);
54 MODULE_PARM_DESC(enable, "Enable audio part of ATI IXP controller.");
55 module_param_array(ac97_clock, int, boot_devs, 0444);
56 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
57 module_param_array(spdif_aclink, bool, boot_devs, 0444);
58 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
59
60
61 /*
62 */
63
64 #define ATI_REG_ISR 0x00 /* interrupt source */
65 #define ATI_REG_ISR_IN_XRUN (1U<<0)
66 #define ATI_REG_ISR_IN_STATUS (1U<<1)
67 #define ATI_REG_ISR_OUT_XRUN (1U<<2)
68 #define ATI_REG_ISR_OUT_STATUS (1U<<3)
69 #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
70 #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
71 #define ATI_REG_ISR_PHYS_INTR (1U<<8)
72 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
73 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
74 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
75 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
76 #define ATI_REG_ISR_NEW_FRAME (1U<<13)
77
78 #define ATI_REG_IER 0x04 /* interrupt enable */
79 #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
80 #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
81 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
82 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
83 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
84 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
85 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
86 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
87 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
88 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
89 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
90 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
91 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
92
93 #define ATI_REG_CMD 0x08 /* command */
94 #define ATI_REG_CMD_POWERDOWN (1U<<0)
95 #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
96 #define ATI_REG_CMD_SEND_EN (1U<<2)
97 #define ATI_REG_CMD_STATUS_MEM (1U<<3)
98 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
99 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
100 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
101 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
102 #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
103 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
104 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
105 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
106 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
107 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
108 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
109 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
110 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
111 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
112 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
113 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
114 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
115 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
116 #define ATI_REG_CMD_PACKED_DIS (1U<<24)
117 #define ATI_REG_CMD_BURST_EN (1U<<25)
118 #define ATI_REG_CMD_PANIC_EN (1U<<26)
119 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
120 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
121 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
122 #define ATI_REG_CMD_AC_SYNC (1U<<30)
123 #define ATI_REG_CMD_AC_RESET (1U<<31)
124
125 #define ATI_REG_PHYS_OUT_ADDR 0x0c
126 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
127 #define ATI_REG_PHYS_OUT_RW (1U<<2)
128 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
129 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
130 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
131
132 #define ATI_REG_PHYS_IN_ADDR 0x10
133 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
134 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
135 #define ATI_REG_PHYS_IN_DATA_SHIFT 16
136
137 #define ATI_REG_SLOTREQ 0x14
138
139 #define ATI_REG_COUNTER 0x18
140 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
141 #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
142
143 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
144
145 #define ATI_REG_IN_DMA_LINKPTR 0x20
146 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
147 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
148 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
149 #define ATI_REG_IN_DMA_DT_SIZE 0x30
150
151 #define ATI_REG_OUT_DMA_SLOT 0x34
152 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
153 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
154 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
155 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
156
157 #define ATI_REG_OUT_DMA_LINKPTR 0x38
158 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
159 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
160 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
161 #define ATI_REG_OUT_DMA_DT_SIZE 0x48
162
163 #define ATI_REG_SPDF_CMD 0x4c
164 #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
165 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
166 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
167
168 #define ATI_REG_SPDF_DMA_LINKPTR 0x50
169 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
170 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
171 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
172 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
173
174 #define ATI_REG_MODEM_MIRROR 0x7c
175 #define ATI_REG_AUDIO_MIRROR 0x80
176
177 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
178 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
179
180 #define ATI_REG_FIFO_FLUSH 0x88
181 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
182 #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
183
184 /* LINKPTR */
185 #define ATI_REG_LINKPTR_EN (1U<<0)
186
187 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
188 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
189 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
190 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
191 #define ATI_REG_DMA_STATE (7U<<26)
192
193
194 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
195
196
197 /*
198 */
199
200 typedef struct snd_atiixp atiixp_t;
201 typedef struct snd_atiixp_dma atiixp_dma_t;
202 typedef struct snd_atiixp_dma_ops atiixp_dma_ops_t;
203
204
205 /*
206 * DMA packate descriptor
207 */
208
209 typedef struct atiixp_dma_desc {
210 u32 addr; /* DMA buffer address */
211 u16 status; /* status bits */
212 u16 size; /* size of the packet in dwords */
213 u32 next; /* address of the next packet descriptor */
214 } atiixp_dma_desc_t;
215
216 /*
217 * stream enum
218 */
219 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
220 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
221 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
222
223 #define NUM_ATI_CODECS 3
224
225
226 /*
227 * constants and callbacks for each DMA type
228 */
229 struct snd_atiixp_dma_ops {
230 int type; /* ATI_DMA_XXX */
231 unsigned int llp_offset; /* LINKPTR offset */
232 unsigned int dt_cur; /* DT_CUR offset */
233 void (*enable_dma)(atiixp_t *chip, int on); /* called from open callback */
234 void (*enable_transfer)(atiixp_t *chip, int on); /* called from trigger (START/STOP) */
235 void (*flush_dma)(atiixp_t *chip); /* called from trigger (STOP only) */
236 };
237
238 /*
239 * DMA stream
240 */
241 struct snd_atiixp_dma {
242 const atiixp_dma_ops_t *ops;
243 struct snd_dma_buffer desc_buf;
244 snd_pcm_substream_t *substream; /* assigned PCM substream */
245 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
246 unsigned int period_bytes, periods;
247 int opened;
248 int running;
249 int pcm_open_flag;
250 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
251 };
252
253 /*
254 * ATI IXP chip
255 */
256 struct snd_atiixp {
257 snd_card_t *card;
258 struct pci_dev *pci;
259
260 unsigned long addr;
261 void __iomem *remap_addr;
262 int irq;
263
264 ac97_bus_t *ac97_bus;
265 ac97_t *ac97[NUM_ATI_CODECS];
266
267 spinlock_t reg_lock;
268 spinlock_t ac97_lock;
269
270 atiixp_dma_t dmas[NUM_ATI_DMAS];
271 struct ac97_pcm *pcms[NUM_ATI_PCMS];
272 snd_pcm_t *pcmdevs[NUM_ATI_PCMDEVS];
273
274 int max_channels; /* max. channels for PCM out */
275
276 unsigned int codec_not_ready_bits; /* for codec detection */
277
278 int spdif_over_aclink; /* passed from the module option */
279 struct semaphore open_mutex; /* playback open mutex */
280 };
281
282
283 /*
284 */
285 static struct pci_device_id snd_atiixp_ids[] = {
286 { 0x1002, 0x4341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
287 { 0x1002, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB300 */
288 { 0x1002, 0x4370, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */
289 { 0, }
290 };
291
292 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
293
294
295 /*
296 * lowlevel functions
297 */
298
299 /*
300 * update the bits of the given register.
301 * return 1 if the bits changed.
302 */
303 static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg,
304 unsigned int mask, unsigned int value)
305 {
306 void __iomem *addr = chip->remap_addr + reg;
307 unsigned int data, old_data;
308 old_data = data = readl(addr);
309 data &= ~mask;
310 data |= value;
311 if (old_data == data)
312 return 0;
313 writel(data, addr);
314 return 1;
315 }
316
317 /*
318 * macros for easy use
319 */
320 #define atiixp_write(chip,reg,value) \
321 writel(value, chip->remap_addr + ATI_REG_##reg)
322 #define atiixp_read(chip,reg) \
323 readl(chip->remap_addr + ATI_REG_##reg)
324 #define atiixp_update(chip,reg,mask,val) \
325 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
326
327 /* delay for one tick */
328 #define do_delay() do { \
329 set_current_state(TASK_UNINTERRUPTIBLE); \
330 schedule_timeout(1); \
331 } while (0)
332
333
334 /*
335 * handling DMA packets
336 *
337 * we allocate a linear buffer for the DMA, and split it to each packet.
338 * in a future version, a scatter-gather buffer should be implemented.
339 */
340
341 #define ATI_DESC_LIST_SIZE \
342 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(atiixp_dma_desc_t))
343
344 /*
345 * build packets ring for the given buffer size.
346 *
347 * IXP handles the buffer descriptors, which are connected as a linked
348 * list. although we can change the list dynamically, in this version,
349 * a static RING of buffer descriptors is used.
350 *
351 * the ring is built in this function, and is set up to the hardware.
352 */
353 static int atiixp_build_dma_packets(atiixp_t *chip, atiixp_dma_t *dma,
354 snd_pcm_substream_t *substream,
355 unsigned int periods,
356 unsigned int period_bytes)
357 {
358 unsigned int i;
359 u32 addr, desc_addr;
360 unsigned long flags;
361
362 if (periods > ATI_MAX_DESCRIPTORS)
363 return -ENOMEM;
364
365 if (dma->desc_buf.area == NULL) {
366 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
367 ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0)
368 return -ENOMEM;
369 dma->period_bytes = dma->periods = 0; /* clear */
370 }
371
372 if (dma->periods == periods && dma->period_bytes == period_bytes)
373 return 0;
374
375 /* reset DMA before changing the descriptor table */
376 spin_lock_irqsave(&chip->reg_lock, flags);
377 writel(0, chip->remap_addr + dma->ops->llp_offset);
378 dma->ops->enable_dma(chip, 0);
379 dma->ops->enable_dma(chip, 1);
380 spin_unlock_irqrestore(&chip->reg_lock, flags);
381
382 /* fill the entries */
383 addr = (u32)substream->runtime->dma_addr;
384 desc_addr = (u32)dma->desc_buf.addr;
385 for (i = 0; i < periods; i++) {
386 atiixp_dma_desc_t *desc = &((atiixp_dma_desc_t *)dma->desc_buf.area)[i];
387 desc->addr = cpu_to_le32(addr);
388 desc->status = 0;
389 desc->size = period_bytes >> 2; /* in dwords */
390 desc_addr += sizeof(atiixp_dma_desc_t);
391 if (i == periods - 1)
392 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
393 else
394 desc->next = cpu_to_le32(desc_addr);
395 addr += period_bytes;
396 }
397
398 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
399 chip->remap_addr + dma->ops->llp_offset);
400
401 dma->period_bytes = period_bytes;
402 dma->periods = periods;
403
404 return 0;
405 }
406
407 /*
408 * remove the ring buffer and release it if assigned
409 */
410 static void atiixp_clear_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, snd_pcm_substream_t *substream)
411 {
412 if (dma->desc_buf.area) {
413 writel(0, chip->remap_addr + dma->ops->llp_offset);
414 snd_dma_free_pages(&dma->desc_buf);
415 dma->desc_buf.area = NULL;
416 }
417 }
418
419 /*
420 * AC97 interface
421 */
422 static int snd_atiixp_acquire_codec(atiixp_t *chip)
423 {
424 int timeout = 1000;
425
426 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
427 if (! timeout--) {
428 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
429 return -EBUSY;
430 }
431 udelay(1);
432 }
433 return 0;
434 }
435
436 static unsigned short snd_atiixp_codec_read(atiixp_t *chip, unsigned short codec, unsigned short reg)
437 {
438 unsigned int data;
439 int timeout;
440
441 if (snd_atiixp_acquire_codec(chip) < 0)
442 return 0xffff;
443 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
444 ATI_REG_PHYS_OUT_ADDR_EN |
445 ATI_REG_PHYS_OUT_RW |
446 codec;
447 atiixp_write(chip, PHYS_OUT_ADDR, data);
448 if (snd_atiixp_acquire_codec(chip) < 0)
449 return 0xffff;
450 timeout = 1000;
451 do {
452 data = atiixp_read(chip, PHYS_IN_ADDR);
453 if (data & ATI_REG_PHYS_IN_READ_FLAG)
454 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
455 udelay(1);
456 } while (--timeout);
457 /* time out may happen during reset */
458 if (reg < 0x7c)
459 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
460 return 0xffff;
461 }
462
463
464 static void snd_atiixp_codec_write(atiixp_t *chip, unsigned short codec, unsigned short reg, unsigned short val)
465 {
466 unsigned int data;
467
468 if (snd_atiixp_acquire_codec(chip) < 0)
469 return;
470 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
471 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
472 ATI_REG_PHYS_OUT_ADDR_EN | codec;
473 atiixp_write(chip, PHYS_OUT_ADDR, data);
474 }
475
476
477 static unsigned short snd_atiixp_ac97_read(ac97_t *ac97, unsigned short reg)
478 {
479 atiixp_t *chip = ac97->private_data;
480 unsigned short data;
481 spin_lock(&chip->ac97_lock);
482 data = snd_atiixp_codec_read(chip, ac97->num, reg);
483 spin_unlock(&chip->ac97_lock);
484 return data;
485
486 }
487
488 static void snd_atiixp_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
489 {
490 atiixp_t *chip = ac97->private_data;
491 spin_lock(&chip->ac97_lock);
492 snd_atiixp_codec_write(chip, ac97->num, reg, val);
493 spin_unlock(&chip->ac97_lock);
494 }
495
496 /*
497 * reset AC link
498 */
499 static int snd_atiixp_aclink_reset(atiixp_t *chip)
500 {
501 int timeout;
502
503 /* reset powerdoewn */
504 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
505 udelay(10);
506
507 /* perform a software reset */
508 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
509 atiixp_read(chip, CMD);
510 udelay(10);
511 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
512
513 timeout = 10;
514 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
515 /* do a hard reset */
516 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
517 ATI_REG_CMD_AC_SYNC);
518 atiixp_read(chip, CMD);
519 do_delay();
520 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
521 if (--timeout) {
522 snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
523 break;
524 }
525 }
526
527 /* deassert RESET and assert SYNC to make sure */
528 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
529 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
530
531 return 0;
532 }
533
534 #ifdef CONFIG_PM
535 static int snd_atiixp_aclink_down(atiixp_t *chip)
536 {
537 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
538 // return -EBUSY;
539 atiixp_update(chip, CMD,
540 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
541 ATI_REG_CMD_POWERDOWN);
542 return 0;
543 }
544 #endif
545
546 /*
547 * auto-detection of codecs
548 *
549 * the IXP chip can generate interrupts for the non-existing codecs.
550 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
551 * even if all three codecs are connected.
552 */
553
554 #define ALL_CODEC_NOT_READY \
555 (ATI_REG_ISR_CODEC0_NOT_READY |\
556 ATI_REG_ISR_CODEC1_NOT_READY |\
557 ATI_REG_ISR_CODEC2_NOT_READY)
558 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
559
560 static int snd_atiixp_codec_detect(atiixp_t *chip)
561 {
562 int timeout;
563
564 chip->codec_not_ready_bits = 0;
565 atiixp_write(chip, IER, CODEC_CHECK_BITS);
566 /* wait for the interrupts */
567 timeout = HZ / 10;
568 while (timeout-- > 0) {
569 do_delay();
570 if (chip->codec_not_ready_bits)
571 break;
572 }
573 atiixp_write(chip, IER, 0); /* disable irqs */
574
575 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
576 snd_printk(KERN_ERR "atiixp: no codec detected!\n");
577 return -ENXIO;
578 }
579 return 0;
580 }
581
582
583 /*
584 * enable DMA and irqs
585 */
586 static int snd_atiixp_chip_start(atiixp_t *chip)
587 {
588 unsigned int reg;
589
590 /* set up spdif, enable burst mode */
591 reg = atiixp_read(chip, CMD);
592 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
593 reg |= ATI_REG_CMD_BURST_EN;
594 atiixp_write(chip, CMD, reg);
595
596 reg = atiixp_read(chip, SPDF_CMD);
597 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
598 atiixp_write(chip, SPDF_CMD, reg);
599
600 /* clear all interrupt source */
601 atiixp_write(chip, ISR, 0xffffffff);
602 /* enable irqs */
603 atiixp_write(chip, IER,
604 ATI_REG_IER_IO_STATUS_EN |
605 ATI_REG_IER_IN_XRUN_EN |
606 ATI_REG_IER_OUT_XRUN_EN |
607 ATI_REG_IER_SPDF_XRUN_EN |
608 ATI_REG_IER_SPDF_STATUS_EN);
609 return 0;
610 }
611
612
613 /*
614 * disable DMA and IRQs
615 */
616 static int snd_atiixp_chip_stop(atiixp_t *chip)
617 {
618 /* clear interrupt source */
619 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
620 /* disable irqs */
621 atiixp_write(chip, IER, 0);
622 return 0;
623 }
624
625
626 /*
627 * PCM section
628 */
629
630 /*
631 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
632 * position. when SG-buffer is implemented, the offset must be calculated
633 * correctly...
634 */
635 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(snd_pcm_substream_t *substream)
636 {
637 atiixp_t *chip = snd_pcm_substream_chip(substream);
638 snd_pcm_runtime_t *runtime = substream->runtime;
639 atiixp_dma_t *dma = (atiixp_dma_t *)runtime->private_data;
640 unsigned int curptr;
641
642 spin_lock(&chip->reg_lock);
643 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
644 if (curptr < dma->buf_addr) {
645 snd_printdd("curptr = %x, base = %x\n", curptr, dma->buf_addr);
646 curptr = 0;
647 } else {
648 curptr -= dma->buf_addr;
649 if (curptr >= dma->buf_bytes) {
650 snd_printdd("curptr = %x, size = %x\n", curptr, dma->buf_bytes);
651 curptr = 0;
652 }
653 }
654 spin_unlock(&chip->reg_lock);
655 return bytes_to_frames(runtime, curptr);
656 }
657
658 /*
659 * XRUN detected, and stop the PCM substream
660 */
661 static void snd_atiixp_xrun_dma(atiixp_t *chip, atiixp_dma_t *dma)
662 {
663 if (! dma->substream || ! dma->running)
664 return;
665 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
666 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
667 }
668
669 /*
670 * the period ack. update the substream.
671 */
672 static void snd_atiixp_update_dma(atiixp_t *chip, atiixp_dma_t *dma)
673 {
674 if (! dma->substream || ! dma->running)
675 return;
676 snd_pcm_period_elapsed(dma->substream);
677 }
678
679 /* set BUS_BUSY interrupt bit if any DMA is running */
680 /* call with spinlock held */
681 static void snd_atiixp_check_bus_busy(atiixp_t *chip)
682 {
683 unsigned int bus_busy;
684 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
685 ATI_REG_CMD_RECEIVE_EN |
686 ATI_REG_CMD_SPDF_OUT_EN))
687 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
688 else
689 bus_busy = 0;
690 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
691 }
692
693 /* common trigger callback
694 * calling the lowlevel callbacks in it
695 */
696 static int snd_atiixp_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
697 {
698 atiixp_t *chip = snd_pcm_substream_chip(substream);
699 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
700 int err = 0;
701
702 snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL);
703
704 spin_lock(&chip->reg_lock);
705 switch (cmd) {
706 case SNDRV_PCM_TRIGGER_START:
707 dma->ops->enable_transfer(chip, 1);
708 dma->running = 1;
709 break;
710 case SNDRV_PCM_TRIGGER_STOP:
711 dma->ops->enable_transfer(chip, 0);
712 dma->running = 0;
713 break;
714 default:
715 err = -EINVAL;
716 break;
717 }
718 if (! err) {
719 snd_atiixp_check_bus_busy(chip);
720 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
721 dma->ops->flush_dma(chip);
722 snd_atiixp_check_bus_busy(chip);
723 }
724 }
725 spin_unlock(&chip->reg_lock);
726 return err;
727 }
728
729
730 /*
731 * lowlevel callbacks for each DMA type
732 *
733 * every callback is supposed to be called in chip->reg_lock spinlock
734 */
735
736 /* flush FIFO of analog OUT DMA */
737 static void atiixp_out_flush_dma(atiixp_t *chip)
738 {
739 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
740 }
741
742 /* enable/disable analog OUT DMA */
743 static void atiixp_out_enable_dma(atiixp_t *chip, int on)
744 {
745 unsigned int data;
746 data = atiixp_read(chip, CMD);
747 if (on) {
748 if (data & ATI_REG_CMD_OUT_DMA_EN)
749 return;
750 atiixp_out_flush_dma(chip);
751 data |= ATI_REG_CMD_OUT_DMA_EN;
752 } else
753 data &= ~ATI_REG_CMD_OUT_DMA_EN;
754 atiixp_write(chip, CMD, data);
755 }
756
757 /* start/stop transfer over OUT DMA */
758 static void atiixp_out_enable_transfer(atiixp_t *chip, int on)
759 {
760 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
761 on ? ATI_REG_CMD_SEND_EN : 0);
762 }
763
764 /* enable/disable analog IN DMA */
765 static void atiixp_in_enable_dma(atiixp_t *chip, int on)
766 {
767 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
768 on ? ATI_REG_CMD_IN_DMA_EN : 0);
769 }
770
771 /* start/stop analog IN DMA */
772 static void atiixp_in_enable_transfer(atiixp_t *chip, int on)
773 {
774 if (on) {
775 unsigned int data = atiixp_read(chip, CMD);
776 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
777 data |= ATI_REG_CMD_RECEIVE_EN;
778 #if 0 /* FIXME: this causes the endless loop */
779 /* wait until slot 3/4 are finished */
780 while ((atiixp_read(chip, COUNTER) &
781 ATI_REG_COUNTER_SLOT) != 5)
782 ;
783 #endif
784 atiixp_write(chip, CMD, data);
785 }
786 } else
787 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
788 }
789
790 /* flush FIFO of analog IN DMA */
791 static void atiixp_in_flush_dma(atiixp_t *chip)
792 {
793 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
794 }
795
796 /* enable/disable SPDIF OUT DMA */
797 static void atiixp_spdif_enable_dma(atiixp_t *chip, int on)
798 {
799 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
800 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
801 }
802
803 /* start/stop SPDIF OUT DMA */
804 static void atiixp_spdif_enable_transfer(atiixp_t *chip, int on)
805 {
806 unsigned int data;
807 data = atiixp_read(chip, CMD);
808 if (on)
809 data |= ATI_REG_CMD_SPDF_OUT_EN;
810 else
811 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
812 atiixp_write(chip, CMD, data);
813 }
814
815 /* flush FIFO of SPDIF OUT DMA */
816 static void atiixp_spdif_flush_dma(atiixp_t *chip)
817 {
818 int timeout;
819
820 /* DMA off, transfer on */
821 atiixp_spdif_enable_dma(chip, 0);
822 atiixp_spdif_enable_transfer(chip, 1);
823
824 timeout = 100;
825 do {
826 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
827 break;
828 udelay(1);
829 } while (timeout-- > 0);
830
831 atiixp_spdif_enable_transfer(chip, 0);
832 }
833
834 /* set up slots and formats for SPDIF OUT */
835 static int snd_atiixp_spdif_prepare(snd_pcm_substream_t *substream)
836 {
837 atiixp_t *chip = snd_pcm_substream_chip(substream);
838
839 spin_lock_irq(&chip->reg_lock);
840 if (chip->spdif_over_aclink) {
841 unsigned int data;
842 /* enable slots 10/11 */
843 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
844 ATI_REG_CMD_SPDF_CONFIG_01);
845 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
846 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
847 ATI_REG_OUT_DMA_SLOT_BIT(11);
848 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
849 atiixp_write(chip, OUT_DMA_SLOT, data);
850 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
851 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
852 ATI_REG_CMD_INTERLEAVE_OUT : 0);
853 } else {
854 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
855 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
856 }
857 spin_unlock_irq(&chip->reg_lock);
858 return 0;
859 }
860
861 /* set up slots and formats for analog OUT */
862 static int snd_atiixp_playback_prepare(snd_pcm_substream_t *substream)
863 {
864 atiixp_t *chip = snd_pcm_substream_chip(substream);
865 unsigned int data;
866
867 spin_lock_irq(&chip->reg_lock);
868 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
869 switch (substream->runtime->channels) {
870 case 8:
871 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
872 ATI_REG_OUT_DMA_SLOT_BIT(11);
873 /* fallthru */
874 case 6:
875 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
876 ATI_REG_OUT_DMA_SLOT_BIT(8);
877 /* fallthru */
878 case 4:
879 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
880 ATI_REG_OUT_DMA_SLOT_BIT(9);
881 /* fallthru */
882 default:
883 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
884 ATI_REG_OUT_DMA_SLOT_BIT(4);
885 break;
886 }
887
888 /* set output threshold */
889 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
890 atiixp_write(chip, OUT_DMA_SLOT, data);
891
892 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
893 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
894 ATI_REG_CMD_INTERLEAVE_OUT : 0);
895
896 /*
897 * enable 6 channel re-ordering bit if needed
898 */
899 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
900 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
901
902 spin_unlock_irq(&chip->reg_lock);
903 return 0;
904 }
905
906 /* set up slots and formats for analog IN */
907 static int snd_atiixp_capture_prepare(snd_pcm_substream_t *substream)
908 {
909 atiixp_t *chip = snd_pcm_substream_chip(substream);
910
911 spin_lock_irq(&chip->reg_lock);
912 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
913 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
914 ATI_REG_CMD_INTERLEAVE_IN : 0);
915 spin_unlock_irq(&chip->reg_lock);
916 return 0;
917 }
918
919 /*
920 * hw_params - allocate the buffer and set up buffer descriptors
921 */
922 static int snd_atiixp_pcm_hw_params(snd_pcm_substream_t *substream,
923 snd_pcm_hw_params_t *hw_params)
924 {
925 atiixp_t *chip = snd_pcm_substream_chip(substream);
926 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
927 int err;
928
929 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
930 if (err < 0)
931 return err;
932 dma->buf_addr = substream->runtime->dma_addr;
933 dma->buf_bytes = params_buffer_bytes(hw_params);
934
935 err = atiixp_build_dma_packets(chip, dma, substream,
936 params_periods(hw_params),
937 params_period_bytes(hw_params));
938 if (err < 0)
939 return err;
940
941 if (dma->ac97_pcm_type >= 0) {
942 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
943 /* PCM is bound to AC97 codec(s)
944 * set up the AC97 codecs
945 */
946 if (dma->pcm_open_flag) {
947 snd_ac97_pcm_close(pcm);
948 dma->pcm_open_flag = 0;
949 }
950 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
951 params_channels(hw_params),
952 pcm->r[0].slots);
953 if (err >= 0)
954 dma->pcm_open_flag = 1;
955 }
956
957 return err;
958 }
959
960 static int snd_atiixp_pcm_hw_free(snd_pcm_substream_t * substream)
961 {
962 atiixp_t *chip = snd_pcm_substream_chip(substream);
963 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
964
965 if (dma->pcm_open_flag) {
966 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
967 snd_ac97_pcm_close(pcm);
968 dma->pcm_open_flag = 0;
969 }
970 atiixp_clear_dma_packets(chip, dma, substream);
971 snd_pcm_lib_free_pages(substream);
972 return 0;
973 }
974
975
976 /*
977 * pcm hardware definition, identical for all DMA types
978 */
979 static snd_pcm_hardware_t snd_atiixp_pcm_hw =
980 {
981 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
982 SNDRV_PCM_INFO_BLOCK_TRANSFER |
983 SNDRV_PCM_INFO_RESUME |
984 SNDRV_PCM_INFO_MMAP_VALID),
985 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
986 .rates = SNDRV_PCM_RATE_48000,
987 .rate_min = 48000,
988 .rate_max = 48000,
989 .channels_min = 2,
990 .channels_max = 2,
991 .buffer_bytes_max = 256 * 1024,
992 .period_bytes_min = 32,
993 .period_bytes_max = 128 * 1024,
994 .periods_min = 2,
995 .periods_max = ATI_MAX_DESCRIPTORS,
996 };
997
998 static int snd_atiixp_pcm_open(snd_pcm_substream_t *substream, atiixp_dma_t *dma, int pcm_type)
999 {
1000 atiixp_t *chip = snd_pcm_substream_chip(substream);
1001 snd_pcm_runtime_t *runtime = substream->runtime;
1002 int err;
1003
1004 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
1005
1006 if (dma->opened)
1007 return -EBUSY;
1008 dma->substream = substream;
1009 runtime->hw = snd_atiixp_pcm_hw;
1010 dma->ac97_pcm_type = pcm_type;
1011 if (pcm_type >= 0) {
1012 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1013 snd_pcm_limit_hw_rates(runtime);
1014 } else {
1015 /* direct SPDIF */
1016 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1017 }
1018 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1019 return err;
1020 runtime->private_data = dma;
1021
1022 /* enable DMA bits */
1023 spin_lock_irq(&chip->reg_lock);
1024 dma->ops->enable_dma(chip, 1);
1025 spin_unlock_irq(&chip->reg_lock);
1026 dma->opened = 1;
1027
1028 return 0;
1029 }
1030
1031 static int snd_atiixp_pcm_close(snd_pcm_substream_t *substream, atiixp_dma_t *dma)
1032 {
1033 atiixp_t *chip = snd_pcm_substream_chip(substream);
1034 /* disable DMA bits */
1035 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
1036 spin_lock_irq(&chip->reg_lock);
1037 dma->ops->enable_dma(chip, 0);
1038 spin_unlock_irq(&chip->reg_lock);
1039 dma->substream = NULL;
1040 dma->opened = 0;
1041 return 0;
1042 }
1043
1044 /*
1045 */
1046 static int snd_atiixp_playback_open(snd_pcm_substream_t *substream)
1047 {
1048 atiixp_t *chip = snd_pcm_substream_chip(substream);
1049 int err;
1050
1051 down(&chip->open_mutex);
1052 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1053 up(&chip->open_mutex);
1054 if (err < 0)
1055 return err;
1056 substream->runtime->hw.channels_max = chip->max_channels;
1057 if (chip->max_channels > 2)
1058 /* channels must be even */
1059 snd_pcm_hw_constraint_step(substream->runtime, 0,
1060 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1061 return 0;
1062 }
1063
1064 static int snd_atiixp_playback_close(snd_pcm_substream_t *substream)
1065 {
1066 atiixp_t *chip = snd_pcm_substream_chip(substream);
1067 int err;
1068 down(&chip->open_mutex);
1069 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1070 up(&chip->open_mutex);
1071 return err;
1072 }
1073
1074 static int snd_atiixp_capture_open(snd_pcm_substream_t *substream)
1075 {
1076 atiixp_t *chip = snd_pcm_substream_chip(substream);
1077 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1078 }
1079
1080 static int snd_atiixp_capture_close(snd_pcm_substream_t *substream)
1081 {
1082 atiixp_t *chip = snd_pcm_substream_chip(substream);
1083 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1084 }
1085
1086 static int snd_atiixp_spdif_open(snd_pcm_substream_t *substream)
1087 {
1088 atiixp_t *chip = snd_pcm_substream_chip(substream);
1089 int err;
1090 down(&chip->open_mutex);
1091 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1092 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1093 else
1094 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1095 up(&chip->open_mutex);
1096 return err;
1097 }
1098
1099 static int snd_atiixp_spdif_close(snd_pcm_substream_t *substream)
1100 {
1101 atiixp_t *chip = snd_pcm_substream_chip(substream);
1102 int err;
1103 down(&chip->open_mutex);
1104 if (chip->spdif_over_aclink)
1105 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1106 else
1107 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1108 up(&chip->open_mutex);
1109 return err;
1110 }
1111
1112 /* AC97 playback */
1113 static snd_pcm_ops_t snd_atiixp_playback_ops = {
1114 .open = snd_atiixp_playback_open,
1115 .close = snd_atiixp_playback_close,
1116 .ioctl = snd_pcm_lib_ioctl,
1117 .hw_params = snd_atiixp_pcm_hw_params,
1118 .hw_free = snd_atiixp_pcm_hw_free,
1119 .prepare = snd_atiixp_playback_prepare,
1120 .trigger = snd_atiixp_pcm_trigger,
1121 .pointer = snd_atiixp_pcm_pointer,
1122 };
1123
1124 /* AC97 capture */
1125 static snd_pcm_ops_t snd_atiixp_capture_ops = {
1126 .open = snd_atiixp_capture_open,
1127 .close = snd_atiixp_capture_close,
1128 .ioctl = snd_pcm_lib_ioctl,
1129 .hw_params = snd_atiixp_pcm_hw_params,
1130 .hw_free = snd_atiixp_pcm_hw_free,
1131 .prepare = snd_atiixp_capture_prepare,
1132 .trigger = snd_atiixp_pcm_trigger,
1133 .pointer = snd_atiixp_pcm_pointer,
1134 };
1135
1136 /* SPDIF playback */
1137 static snd_pcm_ops_t snd_atiixp_spdif_ops = {
1138 .open = snd_atiixp_spdif_open,
1139 .close = snd_atiixp_spdif_close,
1140 .ioctl = snd_pcm_lib_ioctl,
1141 .hw_params = snd_atiixp_pcm_hw_params,
1142 .hw_free = snd_atiixp_pcm_hw_free,
1143 .prepare = snd_atiixp_spdif_prepare,
1144 .trigger = snd_atiixp_pcm_trigger,
1145 .pointer = snd_atiixp_pcm_pointer,
1146 };
1147
1148 static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = {
1149 /* front PCM */
1150 {
1151 .exclusive = 1,
1152 .r = { {
1153 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1154 (1 << AC97_SLOT_PCM_RIGHT) |
1155 (1 << AC97_SLOT_PCM_CENTER) |
1156 (1 << AC97_SLOT_PCM_SLEFT) |
1157 (1 << AC97_SLOT_PCM_SRIGHT) |
1158 (1 << AC97_SLOT_LFE)
1159 }
1160 }
1161 },
1162 /* PCM IN #1 */
1163 {
1164 .stream = 1,
1165 .exclusive = 1,
1166 .r = { {
1167 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1168 (1 << AC97_SLOT_PCM_RIGHT)
1169 }
1170 }
1171 },
1172 /* S/PDIF OUT (optional) */
1173 {
1174 .exclusive = 1,
1175 .spdif = 1,
1176 .r = { {
1177 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1178 (1 << AC97_SLOT_SPDIF_RIGHT2)
1179 }
1180 }
1181 },
1182 };
1183
1184 static atiixp_dma_ops_t snd_atiixp_playback_dma_ops = {
1185 .type = ATI_DMA_PLAYBACK,
1186 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1187 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1188 .enable_dma = atiixp_out_enable_dma,
1189 .enable_transfer = atiixp_out_enable_transfer,
1190 .flush_dma = atiixp_out_flush_dma,
1191 };
1192
1193 static atiixp_dma_ops_t snd_atiixp_capture_dma_ops = {
1194 .type = ATI_DMA_CAPTURE,
1195 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1196 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1197 .enable_dma = atiixp_in_enable_dma,
1198 .enable_transfer = atiixp_in_enable_transfer,
1199 .flush_dma = atiixp_in_flush_dma,
1200 };
1201
1202 static atiixp_dma_ops_t snd_atiixp_spdif_dma_ops = {
1203 .type = ATI_DMA_SPDIF,
1204 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1205 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1206 .enable_dma = atiixp_spdif_enable_dma,
1207 .enable_transfer = atiixp_spdif_enable_transfer,
1208 .flush_dma = atiixp_spdif_flush_dma,
1209 };
1210
1211
1212 static int __devinit snd_atiixp_pcm_new(atiixp_t *chip)
1213 {
1214 snd_pcm_t *pcm;
1215 ac97_bus_t *pbus = chip->ac97_bus;
1216 int err, i, num_pcms;
1217
1218 /* initialize constants */
1219 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1220 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1221 if (! chip->spdif_over_aclink)
1222 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1223
1224 /* assign AC97 pcm */
1225 if (chip->spdif_over_aclink)
1226 num_pcms = 3;
1227 else
1228 num_pcms = 2;
1229 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1230 if (err < 0)
1231 return err;
1232 for (i = 0; i < num_pcms; i++)
1233 chip->pcms[i] = &pbus->pcms[i];
1234
1235 chip->max_channels = 2;
1236 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1237 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1238 chip->max_channels = 6;
1239 else
1240 chip->max_channels = 4;
1241 }
1242
1243 /* PCM #0: analog I/O */
1244 err = snd_pcm_new(chip->card, "ATI IXP AC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1245 if (err < 0)
1246 return err;
1247 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1248 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1249 pcm->private_data = chip;
1250 strcpy(pcm->name, "ATI IXP AC97");
1251 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1252
1253 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1254 snd_dma_pci_data(chip->pci), 64*1024, 128*1024);
1255
1256 /* no SPDIF support on codec? */
1257 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1258 return 0;
1259
1260 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1261 if (chip->pcms[ATI_PCM_SPDIF])
1262 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1263
1264 /* PCM #1: spdif playback */
1265 err = snd_pcm_new(chip->card, "ATI IXP IEC958", ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1266 if (err < 0)
1267 return err;
1268 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1269 pcm->private_data = chip;
1270 if (chip->spdif_over_aclink)
1271 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1272 else
1273 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1274 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1275
1276 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1277 snd_dma_pci_data(chip->pci), 64*1024, 128*1024);
1278
1279 /* pre-select AC97 SPDIF slots 10/11 */
1280 for (i = 0; i < NUM_ATI_CODECS; i++) {
1281 if (chip->ac97[i])
1282 snd_ac97_update_bits(chip->ac97[i], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
1283 }
1284
1285 return 0;
1286 }
1287
1288
1289
1290 /*
1291 * interrupt handler
1292 */
1293 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1294 {
1295 atiixp_t *chip = dev_id;
1296 unsigned int status;
1297
1298 status = atiixp_read(chip, ISR);
1299
1300 if (! status)
1301 return IRQ_NONE;
1302
1303 /* process audio DMA */
1304 if (status & ATI_REG_ISR_OUT_XRUN)
1305 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1306 else if (status & ATI_REG_ISR_OUT_STATUS)
1307 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1308 if (status & ATI_REG_ISR_IN_XRUN)
1309 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1310 else if (status & ATI_REG_ISR_IN_STATUS)
1311 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1312 if (! chip->spdif_over_aclink) {
1313 if (status & ATI_REG_ISR_SPDF_XRUN)
1314 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1315 else if (status & ATI_REG_ISR_SPDF_STATUS)
1316 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1317 }
1318
1319 /* for codec detection */
1320 if (status & CODEC_CHECK_BITS) {
1321 unsigned int detected;
1322 detected = status & CODEC_CHECK_BITS;
1323 spin_lock(&chip->reg_lock);
1324 chip->codec_not_ready_bits |= detected;
1325 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1326 spin_unlock(&chip->reg_lock);
1327 }
1328
1329 /* ack */
1330 atiixp_write(chip, ISR, status);
1331
1332 return IRQ_HANDLED;
1333 }
1334
1335
1336 /*
1337 * ac97 mixer section
1338 */
1339
1340 static int __devinit snd_atiixp_mixer_new(atiixp_t *chip, int clock)
1341 {
1342 ac97_bus_t *pbus;
1343 ac97_template_t ac97;
1344 int i, err;
1345 int codec_count;
1346 static ac97_bus_ops_t ops = {
1347 .write = snd_atiixp_ac97_write,
1348 .read = snd_atiixp_ac97_read,
1349 };
1350 static unsigned int codec_skip[NUM_ATI_CODECS] = {
1351 ATI_REG_ISR_CODEC0_NOT_READY,
1352 ATI_REG_ISR_CODEC1_NOT_READY,
1353 ATI_REG_ISR_CODEC2_NOT_READY,
1354 };
1355
1356 if (snd_atiixp_codec_detect(chip) < 0)
1357 return -ENXIO;
1358
1359 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1360 return err;
1361 pbus->clock = clock;
1362 pbus->shared_type = AC97_SHARED_TYPE_ATIIXP; /* shared with modem driver */
1363 chip->ac97_bus = pbus;
1364
1365 codec_count = 0;
1366 for (i = 0; i < NUM_ATI_CODECS; i++) {
1367 if (chip->codec_not_ready_bits & codec_skip[i])
1368 continue;
1369 memset(&ac97, 0, sizeof(ac97));
1370 ac97.private_data = chip;
1371 ac97.pci = chip->pci;
1372 ac97.num = i;
1373 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1374 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1375 chip->ac97[i] = NULL; /* to be sure */
1376 snd_printdd("atiixp: codec %d not available for audio\n", i);
1377 continue;
1378 }
1379 codec_count++;
1380 }
1381
1382 if (! codec_count) {
1383 snd_printk(KERN_ERR "atiixp: no codec available\n");
1384 return -ENODEV;
1385 }
1386
1387 /* snd_ac97_tune_hardware(chip->ac97, ac97_quirks); */
1388
1389 return 0;
1390 }
1391
1392
1393 #ifdef CONFIG_PM
1394 /*
1395 * power management
1396 */
1397 static int snd_atiixp_suspend(snd_card_t *card, unsigned int state)
1398 {
1399 atiixp_t *chip = card->pm_private_data;
1400 int i;
1401
1402 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1403 if (chip->pcmdevs[i])
1404 snd_pcm_suspend_all(chip->pcmdevs[i]);
1405 for (i = 0; i < NUM_ATI_CODECS; i++)
1406 if (chip->ac97[i])
1407 snd_ac97_suspend(chip->ac97[i]);
1408 snd_atiixp_aclink_down(chip);
1409 snd_atiixp_chip_stop(chip);
1410
1411 pci_set_power_state(chip->pci, 3);
1412 pci_disable_device(chip->pci);
1413 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1414 return 0;
1415 }
1416
1417 static int snd_atiixp_resume(snd_card_t *card, unsigned int state)
1418 {
1419 atiixp_t *chip = card->pm_private_data;
1420 int i;
1421
1422 pci_enable_device(chip->pci);
1423 pci_set_power_state(chip->pci, 0);
1424
1425 snd_atiixp_aclink_reset(chip);
1426 snd_atiixp_chip_start(chip);
1427
1428 for (i = 0; i < NUM_ATI_CODECS; i++)
1429 if (chip->ac97[i])
1430 snd_ac97_resume(chip->ac97[i]);
1431
1432 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1433 return 0;
1434 }
1435 #endif /* CONFIG_PM */
1436
1437
1438 /*
1439 * proc interface for register dump
1440 */
1441
1442 static void snd_atiixp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1443 {
1444 atiixp_t *chip = entry->private_data;
1445 int i;
1446
1447 for (i = 0; i < 256; i += 4)
1448 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1449 }
1450
1451 static void __devinit snd_atiixp_proc_init(atiixp_t *chip)
1452 {
1453 snd_info_entry_t *entry;
1454
1455 if (! snd_card_proc_new(chip->card, "atiixp", &entry))
1456 snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read);
1457 }
1458
1459
1460
1461 /*
1462 * destructor
1463 */
1464
1465 static int snd_atiixp_free(atiixp_t *chip)
1466 {
1467 if (chip->irq < 0)
1468 goto __hw_end;
1469 snd_atiixp_chip_stop(chip);
1470 synchronize_irq(chip->irq);
1471 __hw_end:
1472 if (chip->irq >= 0)
1473 free_irq(chip->irq, (void *)chip);
1474 if (chip->remap_addr)
1475 iounmap(chip->remap_addr);
1476 pci_release_regions(chip->pci);
1477 kfree(chip);
1478 return 0;
1479 }
1480
1481 static int snd_atiixp_dev_free(snd_device_t *device)
1482 {
1483 atiixp_t *chip = device->device_data;
1484 return snd_atiixp_free(chip);
1485 }
1486
1487 /*
1488 * constructor for chip instance
1489 */
1490 static int __devinit snd_atiixp_create(snd_card_t *card,
1491 struct pci_dev *pci,
1492 atiixp_t **r_chip)
1493 {
1494 static snd_device_ops_t ops = {
1495 .dev_free = snd_atiixp_dev_free,
1496 };
1497 atiixp_t *chip;
1498 int err;
1499
1500 if ((err = pci_enable_device(pci)) < 0)
1501 return err;
1502
1503 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1504 if (chip == NULL)
1505 return -ENOMEM;
1506
1507 spin_lock_init(&chip->reg_lock);
1508 spin_lock_init(&chip->ac97_lock);
1509 init_MUTEX(&chip->open_mutex);
1510 chip->card = card;
1511 chip->pci = pci;
1512 chip->irq = -1;
1513 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
1514 kfree(chip);
1515 return err;
1516 }
1517 chip->addr = pci_resource_start(pci, 0);
1518 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0));
1519 if (chip->remap_addr == 0) {
1520 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1521 snd_atiixp_free(chip);
1522 return -EIO;
1523 }
1524
1525 if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1526 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1527 snd_atiixp_free(chip);
1528 return -EBUSY;
1529 }
1530 chip->irq = pci->irq;
1531 pci_set_master(pci);
1532 synchronize_irq(chip->irq);
1533
1534 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1535 snd_atiixp_free(chip);
1536 return err;
1537 }
1538
1539 snd_card_set_dev(card, &pci->dev);
1540
1541 *r_chip = chip;
1542 return 0;
1543 }
1544
1545
1546 static int __devinit snd_atiixp_probe(struct pci_dev *pci,
1547 const struct pci_device_id *pci_id)
1548 {
1549 static int dev;
1550 snd_card_t *card;
1551 atiixp_t *chip;
1552 unsigned char revision;
1553 int err;
1554
1555 if (dev >= SNDRV_CARDS)
1556 return -ENODEV;
1557 if (!enable[dev]) {
1558 dev++;
1559 return -ENOENT;
1560 }
1561
1562 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1563 if (card == NULL)
1564 return -ENOMEM;
1565
1566 pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
1567
1568 strcpy(card->driver, spdif_aclink[dev] ? "ATIIXP" : "ATIIXP-SPDMA");
1569 strcpy(card->shortname, "ATI IXP");
1570 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1571 goto __error;
1572
1573 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1574 goto __error;
1575
1576 chip->spdif_over_aclink = spdif_aclink[dev];
1577
1578 if ((err = snd_atiixp_mixer_new(chip, ac97_clock[dev])) < 0)
1579 goto __error;
1580
1581 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1582 goto __error;
1583
1584 snd_atiixp_proc_init(chip);
1585
1586 snd_atiixp_chip_start(chip);
1587
1588 sprintf(card->longname, "%s rev %x at 0x%lx, irq %i",
1589 card->shortname, revision, chip->addr, chip->irq);
1590
1591 snd_card_set_pm_callback(card, snd_atiixp_suspend, snd_atiixp_resume, chip);
1592
1593 if ((err = snd_card_register(card)) < 0)
1594 goto __error;
1595
1596 pci_set_drvdata(pci, card);
1597 dev++;
1598 return 0;
1599
1600 __error:
1601 snd_card_free(card);
1602 return err;
1603 }
1604
1605 static void __devexit snd_atiixp_remove(struct pci_dev *pci)
1606 {
1607 snd_card_free(pci_get_drvdata(pci));
1608 pci_set_drvdata(pci, NULL);
1609 }
1610
1611 static struct pci_driver driver = {
1612 .name = "ATI IXP AC97 controller",
1613 .id_table = snd_atiixp_ids,
1614 .probe = snd_atiixp_probe,
1615 .remove = __devexit_p(snd_atiixp_remove),
1616 SND_PCI_PM_CALLBACKS
1617 };
1618
1619
1620 static int __init alsa_card_atiixp_init(void)
1621 {
1622 return pci_module_init(&driver);
1623 }
1624
1625 static void __exit alsa_card_atiixp_exit(void)
1626 {
1627 pci_unregister_driver(&driver);
1628 }
1629
1630 module_init(alsa_card_atiixp_init)
1631 module_exit(alsa_card_atiixp_exit)
MOXA 2.6.9 from sdlinux-moxaart.tgz