include/asm-x86_64/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <linux/config.h>
   8
   9 extern int printk(const char * fmt, ...)
  10         __attribute__ ((format (printf, 1, 2)));
  11
  12 /*
  13  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  14  */
  15
  16 typedef struct {
  17         volatile unsigned int lock;
  18 #ifdef CONFIG_DEBUG_SPINLOCK
  19         unsigned magic;
  20 #endif
  21 } spinlock_t;
  22
  23 #define SPINLOCK_MAGIC  0xdead4ead
  24
  25 #ifdef CONFIG_DEBUG_SPINLOCK
  26 #define SPINLOCK_MAGIC_INIT     , SPINLOCK_MAGIC
  27 #else
  28 #define SPINLOCK_MAGIC_INIT     /* */
  29 #endif
  30
  31 #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 SPINLOCK_MAGIC_INIT }
  32
  33 #define spin_lock_init(x)       do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
  34
  35 /*
  36  * Simple spin lock operations.  There are two variants, one clears IRQ's
  37  * on the local processor, one does not.
  38  *
  39  * We make no fairness assumptions. They have a cost.
  40  */
  41
  42 #define spin_is_locked(x)       (*(volatile signed char *)(&(x)->lock) <= 0)
  43 #define spin_unlock_wait(x)     do { barrier(); } while(spin_is_locked(x))
  44 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
  45
  46 #define spin_lock_string \
  47         "\n1:\t" \
  48         "lock ; decb %0\n\t" \
  49         "js 2f\n" \
  50         LOCK_SECTION_START("") \
  51         "2:\t" \
  52         "rep;nop\n\t" \
  53         "cmpb $0,%0\n\t" \
  54         "jle 2b\n\t" \
  55         "jmp 1b\n" \
  56         LOCK_SECTION_END
  57
  58 /*
  59  * This works. Despite all the confusion.
  60  * (except on PPro SMP or if we are using OOSTORE)
  61  * (PPro errata 66, 92)
  62  */
  63
  64 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
  65
  66 #define spin_unlock_string \
  67         "movb $1,%0" \
  68                 :"=m" (lock->lock) : : "memory"
  69
  70
  71 static inline void _raw_spin_unlock(spinlock_t *lock)
  72 {
  73 #ifdef CONFIG_DEBUG_SPINLOCK
  74         BUG_ON(lock->magic != SPINLOCK_MAGIC);
  75         BUG_ON(!spin_is_locked(lock));
  76 #endif
  77         __asm__ __volatile__(
  78                 spin_unlock_string
  79         );
  80 }
  81
  82 #else
  83
  84 #define spin_unlock_string \
  85         "xchgb %b0, %1" \
  86                 :"=q" (oldval), "=m" (lock->lock) \
  87                 :"0" (oldval) : "memory"
  88
  89 static inline void _raw_spin_unlock(spinlock_t *lock)
  90 {
  91         char oldval = 1;
  92 #ifdef CONFIG_DEBUG_SPINLOCK
  93         BUG_ON(lock->magic != SPINLOCK_MAGIC);
  94         BUG_ON(!spin_is_locked(lock));
  95 #endif
  96         __asm__ __volatile__(
  97                 spin_unlock_string
  98         );
  99 }
 100
 101 #endif
 102
 103 static inline int _raw_spin_trylock(spinlock_t *lock)
 104 {
 105         char oldval;
 106         __asm__ __volatile__(
 107                 "xchgb %b0,%1"
 108                 :"=q" (oldval), "=m" (lock->lock)
 109                 :"0" (0) : "memory");
 110         return oldval > 0;
 111 }
 112
 113 static inline void _raw_spin_lock(spinlock_t *lock)
 114 {
 115 #ifdef CONFIG_DEBUG_SPINLOCK
 116         if (lock->magic != SPINLOCK_MAGIC) {
 117                 printk("eip: %p\n", __builtin_return_address(0));
 118                 BUG();
 119         }
 120 #endif
 121         __asm__ __volatile__(
 122                 spin_lock_string
 123                 :"=m" (lock->lock) : : "memory");
 124 }
 125
 126
 127 /*
 128  * Read-write spinlocks, allowing multiple readers
 129  * but only one writer.
 130  *
 131  * NOTE! it is quite common to have readers in interrupts
 132  * but no interrupt writers. For those circumstances we
 133  * can "mix" irq-safe locks - any writer needs to get a
 134  * irq-safe write-lock, but readers can get non-irqsafe
 135  * read-locks.
 136  */
 137 typedef struct {
 138         volatile unsigned int lock;
 139 #ifdef CONFIG_DEBUG_SPINLOCK
 140         unsigned magic;
 141 #endif
 142 } rwlock_t;
 143
 144 #define RWLOCK_MAGIC    0xdeaf1eed
 145
 146 #ifdef CONFIG_DEBUG_SPINLOCK
 147 #define RWLOCK_MAGIC_INIT       , RWLOCK_MAGIC
 148 #else
 149 #define RWLOCK_MAGIC_INIT       /* */
 150 #endif
 151
 152 #define RW_LOCK_UNLOCKED (rwlock_t) { RW_LOCK_BIAS RWLOCK_MAGIC_INIT }
 153
 154 #define rwlock_init(x)  do { *(x) = RW_LOCK_UNLOCKED; } while(0)
 155
 156 #define rwlock_is_locked(x) ((x)->lock != RW_LOCK_BIAS)
 157
 158 /*
 159  * On x86, we implement read-write locks as a 32-bit counter
 160  * with the high bit (sign) being the "contended" bit.
 161  *
 162  * The inline assembly is non-obvious. Think about it.
 163  *
 164  * Changed to use the same technique as rw semaphores.  See
 165  * semaphore.h for details.  -ben
 166  */
 167 /* the spinlock helpers are in arch/i386/kernel/semaphore.c */
 168
 169 static inline void _raw_read_lock(rwlock_t *rw)
 170 {
 171 #ifdef CONFIG_DEBUG_SPINLOCK
 172         BUG_ON(rw->magic != RWLOCK_MAGIC);
 173 #endif
 174         __build_read_lock(rw, "__read_lock_failed");
 175 }
 176
 177 static inline void _raw_write_lock(rwlock_t *rw)
 178 {
 179 #ifdef CONFIG_DEBUG_SPINLOCK
 180         BUG_ON(rw->magic != RWLOCK_MAGIC);
 181 #endif
 182         __build_write_lock(rw, "__write_lock_failed");
 183 }
 184
 185 #define _raw_read_unlock(rw)            asm volatile("lock ; incl %0" :"=m" ((rw)->lock) : : "memory")
 186 #define _raw_write_unlock(rw)   asm volatile("lock ; addl $" RW_LOCK_BIAS_STR ",%0":"=m" ((rw)->lock) : : "memory")
 187
 188 static inline int _raw_write_trylock(rwlock_t *lock)
 189 {
 190         atomic_t *count = (atomic_t *)lock;
 191         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 192                 return 1;
 193         atomic_add(RW_LOCK_BIAS, count);
 194         return 0;
 195 }
 196
 197 #endif /* __ASM_SPINLOCK_H */