include/asm-arm/arch-s3c2410/map.h

   1 /* linux/include/asm-arm/arch-s3c2410/map.h
   2  *
   3  * (c) 2003 Simtec Electronics
   4  *  Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Changelog:
  13  *  12-May-2003 BJD  Created file
  14  *  06-Jan-2003 BJD  Linux 2.6.0 version, moved bast specifics out
  15 */
  16
  17 #ifndef __ASM_ARCH_MAP_H
  18 #define __ASM_ARCH_MAP_H
  19
  20 /* we have a bit of a tight squeeze to fit all our registers from
  21  * 0xF00000000 upwards, since we use all of the nGCS space in some
  22  * capacity, and also need to fit the S3C2410 registers in as well...
  23  *
  24  * we try to ensure stuff like the IRQ registers are available for
  25  * an single MOVS instruction (ie, only 8 bits of set data)
  26  *
  27  * Note, we are trying to remove some of these from the implementation
  28  * as they are only useful to certain drivers...
  29  */
  30
  31 #define S3C2410_ADDR(x)   (0xF0000000 + (x))
  32
  33 /* interrupt controller is the first thing we put in, to make
  34  * the assembly code for the irq detection easier
  35  */
  36 #define S3C2410_VA_IRQ     S3C2410_ADDR(0x00000000)
  37 #define S3C2410_PA_IRQ     (0x4A000000)
  38 #define S3C2410_SZ_IRQ     SZ_1M
  39
  40 /* memory controller registers */
  41 #define S3C2410_VA_MEMCTRL S3C2410_ADDR(0x00100000)
  42 #define S3C2410_PA_MEMCTRL (0x48000000)
  43 #define S3C2410_SZ_MEMCTRL SZ_1M
  44
  45 /* USB host controller */
  46 #define S3C2410_VA_USBHOST S3C2410_ADDR(0x00200000)
  47 #define S3C2410_PA_USBHOST (0x49000000)
  48 #define S3C2410_SZ_USBHOST SZ_1M
  49
  50 /* DMA controller */
  51 #define S3C2410_VA_DMA     S3C2410_ADDR(0x00300000)
  52 #define S3C2410_PA_DMA     (0x4B000000)
  53 #define S3C2410_SZ_DMA     SZ_1M
  54
  55 /* Clock and Power management */
  56 #define S3C2410_VA_CLKPWR  S3C2410_ADDR(0x00400000)
  57 #define S3C2410_PA_CLKPWR  (0x4C000000)
  58 #define S3C2410_SZ_CLKPWR  SZ_1M
  59
  60 /* LCD controller */
  61 #define S3C2410_VA_LCD     S3C2410_ADDR(0x00600000)
  62 #define S3C2410_PA_LCD     (0x4D000000)
  63 #define S3C2410_SZ_LCD     SZ_1M
  64
  65 /* NAND flash controller */
  66 #define S3C2410_VA_NAND    S3C2410_ADDR(0x00700000)
  67 #define S3C2410_PA_NAND    (0x4E000000)
  68 #define S3C2410_SZ_NAND    SZ_1M
  69
  70 /* UARTs */
  71 #define S3C2410_VA_UART    S3C2410_ADDR(0x00800000)
  72 #define S3C2410_PA_UART    (0x50000000)
  73 #define S3C2410_SZ_UART    SZ_1M
  74
  75 /* Timers */
  76 #define S3C2410_VA_TIMER   S3C2410_ADDR(0x00900000)
  77 #define S3C2410_PA_TIMER   (0x51000000)
  78 #define S3C2410_SZ_TIMER   SZ_1M
  79
  80 /* USB Device port */
  81 #define S3C2410_VA_USBDEV  S3C2410_ADDR(0x00A00000)
  82 #define S3C2410_PA_USBDEV  (0x52000000)
  83 #define S3C2410_SZ_USBDEV  SZ_1M
  84
  85 /* Watchdog */
  86 #define S3C2410_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
  87 #define S3C2410_PA_WATCHDOG (0x53000000)
  88 #define S3C2410_SZ_WATCHDOG SZ_1M
  89
  90 /* IIC hardware controller */
  91 #define S3C2410_VA_IIC     S3C2410_ADDR(0x00C00000)
  92 #define S3C2410_PA_IIC     (0x54000000)
  93 #define S3C2410_SZ_IIC     SZ_1M
  94
  95 #define VA_IIC_BASE        (S3C2410_VA_IIC)
  96
  97 /* IIS controller */
  98 #define S3C2410_VA_IIS     S3C2410_ADDR(0x00D00000)
  99 #define S3C2410_PA_IIS     (0x55000000)
 100 #define S3C2410_SZ_IIS     SZ_1M
 101
 102 /* GPIO ports */
 103 #define S3C2410_VA_GPIO    S3C2410_ADDR(0x00E00000)
 104 #define S3C2410_PA_GPIO    (0x56000000)
 105 #define S3C2410_SZ_GPIO    SZ_1M
 106
 107 /* RTC */
 108 #define S3C2410_VA_RTC     S3C2410_ADDR(0x00F00000)
 109 #define S3C2410_PA_RTC     (0x57000000)
 110 #define S3C2410_SZ_RTC     SZ_1M
 111
 112 /* ADC */
 113 #define S3C2410_VA_ADC     S3C2410_ADDR(0x01000000)
 114 #define S3C2410_PA_ADC     (0x58000000)
 115 #define S3C2410_SZ_ADC     SZ_1M
 116
 117 /* SPI */
 118 #define S3C2410_VA_SPI     S3C2410_ADDR(0x01100000)
 119 #define S3C2410_PA_SPI     (0x59000000)
 120 #define S3C2410_SZ_SPI     SZ_1M
 121
 122 /* SDI */
 123 #define S3C2410_VA_SDI     S3C2410_ADDR(0x01200000)
 124 #define S3C2410_PA_SDI     (0x5A000000)
 125 #define S3C2410_SZ_SDI     SZ_1M
 126
 127 /* ISA style IO, for each machine to sort out mappings for, if it
 128  * implements it. We reserve two 16M regions for ISA.
 129  */
 130
 131 #define S3C2410_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
 132 #define S3C2410_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
 133
 134 /* physical addresses of all the chip-select areas */
 135
 136 #define S3C2410_CS0 (0x00000000)
 137 #define S3C2410_CS1 (0x08000000)
 138 #define S3C2410_CS2 (0x10000000)
 139 #define S3C2410_CS3 (0x18000000)
 140 #define S3C2410_CS4 (0x20000000)
 141 #define S3C2410_CS5 (0x28000000)
 142 #define S3C2410_CS6 (0x30000000)
 143 #define S3C2410_CS7 (0x38000000)
 144
 145 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
 146
 147
 148 #endif /* __ASM_ARCH_MAP_H */