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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / scsi / sata_sil.c
blob9a349a9be37e736f05debdf171449b82e343763a
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 * The contents of this file are subject to the Open
12 * Software License version 1.1 that can be found at
13 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
14 * by reference.
15 *
16 * Alternatively, the contents of this file may be used under the terms
17 * of the GNU General Public License version 2 (the "GPL") as distributed
18 * in the kernel source COPYING file, in which case the provisions of
19 * the GPL are applicable instead of the above. If you wish to allow
20 * the use of your version of this file only under the terms of the
21 * GPL and not to allow others to use your version of this file under
22 * the OSL, indicate your decision by deleting the provisions above and
23 * replace them with the notice and other provisions required by the GPL.
24 * If you do not delete the provisions above, a recipient may use your
25 * version of this file under either the OSL or the GPL.
26 *
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include "scsi.h"
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
39
40 #define DRV_NAME "sata_sil"
41 #define DRV_VERSION "0.54"
42
43 enum {
44 sil_3112 = 0,
45 sil_3114 = 1,
46
47 SIL_SYSCFG = 0x48,
48 SIL_MASK_IDE0_INT = (1 << 22),
49 SIL_MASK_IDE1_INT = (1 << 23),
50 SIL_MASK_IDE2_INT = (1 << 24),
51 SIL_MASK_IDE3_INT = (1 << 25),
52 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
53 SIL_MASK_4PORT = SIL_MASK_2PORT |
54 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
55
56 SIL_IDE2_BMDMA = 0x200,
57
58 SIL_INTR_STEERING = (1 << 1),
59 SIL_QUIRK_MOD15WRITE = (1 << 0),
60 SIL_QUIRK_UDMA5MAX = (1 << 1),
61 };
62
63 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
64 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
65 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
66 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
67 static void sil_post_set_mode (struct ata_port *ap);
68
69 static struct pci_device_id sil_pci_tbl[] = {
70 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
71 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
72 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
73 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
74 { } /* terminate list */
75 };
76
77
78 /* TODO firmware versions should be added - eric */
79 struct sil_drivelist {
80 const char * product;
81 unsigned int quirk;
82 } sil_blacklist [] = {
83 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
84 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
85 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
86 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
87 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
88 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
89 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
90 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
91 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
92 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
93 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
94 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
95 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
96 { }
97 };
98
99 static struct pci_driver sil_pci_driver = {
100 .name = DRV_NAME,
101 .id_table = sil_pci_tbl,
102 .probe = sil_init_one,
103 .remove = ata_pci_remove_one,
104 };
105
106 static Scsi_Host_Template sil_sht = {
107 .module = THIS_MODULE,
108 .name = DRV_NAME,
109 .ioctl = ata_scsi_ioctl,
110 .queuecommand = ata_scsi_queuecmd,
111 .eh_strategy_handler = ata_scsi_error,
112 .can_queue = ATA_DEF_QUEUE,
113 .this_id = ATA_SHT_THIS_ID,
114 .sg_tablesize = LIBATA_MAX_PRD,
115 .max_sectors = ATA_MAX_SECTORS,
116 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
117 .emulated = ATA_SHT_EMULATED,
118 .use_clustering = ATA_SHT_USE_CLUSTERING,
119 .proc_name = DRV_NAME,
120 .dma_boundary = ATA_DMA_BOUNDARY,
121 .slave_configure = ata_scsi_slave_config,
122 .bios_param = ata_std_bios_param,
123 };
124
125 static struct ata_port_operations sil_ops = {
126 .port_disable = ata_port_disable,
127 .dev_config = sil_dev_config,
128 .tf_load = ata_tf_load,
129 .tf_read = ata_tf_read,
130 .check_status = ata_check_status,
131 .exec_command = ata_exec_command,
132 .dev_select = ata_std_dev_select,
133 .phy_reset = sata_phy_reset,
134 .post_set_mode = sil_post_set_mode,
135 .bmdma_setup = ata_bmdma_setup,
136 .bmdma_start = ata_bmdma_start,
137 .qc_prep = ata_qc_prep,
138 .qc_issue = ata_qc_issue_prot,
139 .eng_timeout = ata_eng_timeout,
140 .irq_handler = ata_interrupt,
141 .irq_clear = ata_bmdma_irq_clear,
142 .scr_read = sil_scr_read,
143 .scr_write = sil_scr_write,
144 .port_start = ata_port_start,
145 .port_stop = ata_port_stop,
146 };
147
148 static struct ata_port_info sil_port_info[] = {
149 /* sil_3112 */
150 {
151 .sht = &sil_sht,
152 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
153 ATA_FLAG_SRST | ATA_FLAG_MMIO,
154 .pio_mask = 0x1f, /* pio0-4 */
155 .mwdma_mask = 0x07, /* mwdma0-2 */
156 .udma_mask = 0x3f, /* udma0-5 */
157 .port_ops = &sil_ops,
158 }, /* sil_3114 */
159 {
160 .sht = &sil_sht,
161 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
162 ATA_FLAG_SRST | ATA_FLAG_MMIO,
163 .pio_mask = 0x1f, /* pio0-4 */
164 .mwdma_mask = 0x07, /* mwdma0-2 */
165 .udma_mask = 0x3f, /* udma0-5 */
166 .port_ops = &sil_ops,
167 },
168 };
169
170 /* per-port register offsets */
171 /* TODO: we can probably calculate rather than use a table */
172 static const struct {
173 unsigned long tf; /* ATA taskfile register block */
174 unsigned long ctl; /* ATA control/altstatus register block */
175 unsigned long bmdma; /* DMA register block */
176 unsigned long scr; /* SATA control register block */
177 unsigned long sien; /* SATA Interrupt Enable register */
178 unsigned long xfer_mode;/* data transfer mode register */
179 } sil_port[] = {
180 /* port 0 ... */
181 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
182 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
183 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
184 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
185 /* ... port 3 */
186 };
187
188 MODULE_AUTHOR("Jeff Garzik");
189 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
190 MODULE_LICENSE("GPL");
191 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
192
193 static void sil_post_set_mode (struct ata_port *ap)
194 {
195 struct ata_host_set *host_set = ap->host_set;
196 struct ata_device *dev;
197 void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
198 u32 tmp, dev_mode[2];
199 unsigned int i;
200
201 for (i = 0; i < 2; i++) {
202 dev = &ap->device[i];
203 if (!ata_dev_present(dev))
204 dev_mode[i] = 0; /* PIO0/1/2 */
205 else if (dev->flags & ATA_DFLAG_PIO)
206 dev_mode[i] = 1; /* PIO3/4 */
207 else
208 dev_mode[i] = 3; /* UDMA */
209 /* value 2 indicates MDMA */
210 }
211
212 tmp = readl(addr);
213 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
214 tmp |= dev_mode[0];
215 tmp |= (dev_mode[1] << 4);
216 writel(tmp, addr);
217 readl(addr); /* flush */
218 }
219
220 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
221 {
222 unsigned long offset = ap->ioaddr.scr_addr;
223
224 switch (sc_reg) {
225 case SCR_STATUS:
226 return offset + 4;
227 case SCR_ERROR:
228 return offset + 8;
229 case SCR_CONTROL:
230 return offset;
231 default:
232 /* do nothing */
233 break;
234 }
235
236 return 0;
237 }
238
239 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
240 {
241 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
242 if (mmio)
243 return readl(mmio);
244 return 0xffffffffU;
245 }
246
247 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
248 {
249 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
250 if (mmio)
251 writel(val, mmio);
252 }
253
254 /**
255 * sil_dev_config - Apply device/host-specific errata fixups
256 * @ap: Port containing device to be examined
257 * @dev: Device to be examined
258 *
259 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
260 * device is known to be present, this function is called.
261 * We apply two errata fixups which are specific to Silicon Image,
262 * a Seagate and a Maxtor fixup.
263 *
264 * For certain Seagate devices, we must limit the maximum sectors
265 * to under 8K.
266 *
267 * For certain Maxtor devices, we must not program the drive
268 * beyond udma5.
269 *
270 * Both fixups are unfairly pessimistic. As soon as I get more
271 * information on these errata, I will create a more exhaustive
272 * list, and apply the fixups to only the specific
273 * devices/hosts/firmwares that need it.
274 *
275 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
276 * The Maxtor quirk is in the blacklist, but I'm keeping the original
277 * pessimistic fix for the following reasons...
278 * - There seems to be less info on it, only one device gleaned off the
279 * Windows driver, maybe only one is affected. More info would be greatly
280 * appreciated.
281 * - But then again UDMA5 is hardly anything to complain about
282 */
283 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
284 {
285 unsigned int n, quirks = 0;
286 unsigned char model_num[40];
287 const char *s;
288 unsigned int len;
289
290 ata_dev_id_string(dev, model_num, ATA_ID_PROD_OFS,
291 sizeof(model_num));
292 s = &model_num[0];
293 len = strnlen(s, sizeof(model_num));
294
295 /* ATAPI specifies that empty space is blank-filled; remove blanks */
296 while ((len > 0) && (s[len - 1] == ' '))
297 len--;
298
299 for (n = 0; sil_blacklist[n].product; n++)
300 if (!memcmp(sil_blacklist[n].product, s,
301 strlen(sil_blacklist[n].product))) {
302 quirks = sil_blacklist[n].quirk;
303 break;
304 }
305
306 /* limit requests to 15 sectors */
307 if (quirks & SIL_QUIRK_MOD15WRITE) {
308 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
309 ap->id, dev->devno);
310 ap->host->max_sectors = 15;
311 ap->host->hostt->max_sectors = 15;
312 dev->flags |= ATA_DFLAG_LOCK_SECTORS;
313 return;
314 }
315
316 /* limit to udma5 */
317 if (quirks & SIL_QUIRK_UDMA5MAX) {
318 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
319 ap->id, dev->devno, s);
320 ap->udma_mask &= ATA_UDMA5;
321 return;
322 }
323 }
324
325 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
326 {
327 static int printed_version;
328 struct ata_probe_ent *probe_ent = NULL;
329 unsigned long base;
330 void *mmio_base;
331 int rc;
332 unsigned int i;
333 u32 tmp, irq_mask;
334
335 if (!printed_version++)
336 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
337
338 /*
339 * If this driver happens to only be useful on Apple's K2, then
340 * we should check that here as it has a normal Serverworks ID
341 */
342 rc = pci_enable_device(pdev);
343 if (rc)
344 return rc;
345
346 rc = pci_request_regions(pdev, DRV_NAME);
347 if (rc)
348 goto err_out;
349
350 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
351 if (rc)
352 goto err_out_regions;
353 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
354 if (rc)
355 goto err_out_regions;
356
357 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
358 if (probe_ent == NULL) {
359 rc = -ENOMEM;
360 goto err_out_regions;
361 }
362
363 memset(probe_ent, 0, sizeof(*probe_ent));
364 INIT_LIST_HEAD(&probe_ent->node);
365 probe_ent->pdev = pdev;
366 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
367 probe_ent->sht = sil_port_info[ent->driver_data].sht;
368 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
369 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
370 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
371 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
372 probe_ent->irq = pdev->irq;
373 probe_ent->irq_flags = SA_SHIRQ;
374 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
375
376 mmio_base = ioremap(pci_resource_start(pdev, 5),
377 pci_resource_len(pdev, 5));
378 if (mmio_base == NULL) {
379 rc = -ENOMEM;
380 goto err_out_free_ent;
381 }
382
383 probe_ent->mmio_base = mmio_base;
384
385 base = (unsigned long) mmio_base;
386
387 for (i = 0; i < probe_ent->n_ports; i++) {
388 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
389 probe_ent->port[i].altstatus_addr =
390 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
391 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
392 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
393 ata_std_ports(&probe_ent->port[i]);
394 }
395
396 if (ent->driver_data == sil_3114) {
397 irq_mask = SIL_MASK_4PORT;
398
399 /* flip the magic "make 4 ports work" bit */
400 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
401 if ((tmp & SIL_INTR_STEERING) == 0)
402 writel(tmp | SIL_INTR_STEERING,
403 mmio_base + SIL_IDE2_BMDMA);
404
405 } else {
406 irq_mask = SIL_MASK_2PORT;
407 }
408
409 /* make sure IDE0/1/2/3 interrupts are not masked */
410 tmp = readl(mmio_base + SIL_SYSCFG);
411 if (tmp & irq_mask) {
412 tmp &= ~irq_mask;
413 writel(tmp, mmio_base + SIL_SYSCFG);
414 readl(mmio_base + SIL_SYSCFG); /* flush */
415 }
416
417 /* mask all SATA phy-related interrupts */
418 /* TODO: unmask bit 6 (SError N bit) for hotplug */
419 for (i = 0; i < probe_ent->n_ports; i++)
420 writel(0, mmio_base + sil_port[i].sien);
421
422 pci_set_master(pdev);
423
424 /* FIXME: check ata_device_add return value */
425 ata_device_add(probe_ent);
426 kfree(probe_ent);
427
428 return 0;
429
430 err_out_free_ent:
431 kfree(probe_ent);
432 err_out_regions:
433 pci_release_regions(pdev);
434 err_out:
435 pci_disable_device(pdev);
436 return rc;
437 }
438
439 static int __init sil_init(void)
440 {
441 return pci_module_init(&sil_pci_driver);
442 }
443
444 static void __exit sil_exit(void)
445 {
446 pci_unregister_driver(&sil_pci_driver);
447 }
448
449
450 module_init(sil_init);
451 module_exit(sil_exit);
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