initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / parisc / dino.c
blob5840219f6efd72ccf31b9fd407edd43d60c60f43
1 /*
2 ** DINO manager
3 **
4 ** (c) Copyright 1999 Red Hat Software
5 ** (c) Copyright 1999 SuSE GmbH
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** (c) Copyright 2000 Grant Grundler
8 **
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
14 ** This module provides access to Dino PCI bus (config/IOport spaces)
15 ** and helps manage Dino IRQ lines.
17 ** Dino interrupt handling is a bit complicated.
18 ** Dino always writes to the broadcast EIR via irr0 for now.
19 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
20 ** Only one processor interrupt is used for the 11 IRQ line
21 ** inputs to dino.
23 ** The different between Built-in Dino and Card-Mode
24 ** dino is in chip initialization and pci device initialization.
26 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
27 ** BARs are configured and used by the driver. Programming MMIO address
28 ** requires substantial knowledge of available Host I/O address ranges
29 ** is currently not supported. Port/Config accessor functions are the
30 ** same. "BIOS" differences are handled within the existing routines.
33 /* Changes :
34 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
35 ** - added support for the integrated RS232.
39 ** TODO: create a virtual address for each Dino HPA.
40 ** GSC code might be able to do this since IODC data tells us
41 ** how many pages are used. PCI subsystem could (must?) do this
42 ** for PCI drivers devices which implement/use MMIO registers.
45 #include <linux/config.h>
46 #include <linux/delay.h>
47 #include <linux/types.h>
48 #include <linux/kernel.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/ioport.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h> /* for struct irqaction */
54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
56 #include <asm/pdc.h>
57 #include <asm/page.h>
58 #include <asm/system.h>
59 #include <asm/io.h>
60 #include <asm/irq.h>
61 #include <asm/hardware.h>
63 #include "gsc.h"
65 #undef DINO_DEBUG
67 #ifdef DINO_DEBUG
68 #define DBG(x...) printk(x)
69 #else
70 #define DBG(x...)
71 #endif
74 ** Config accessor functions only pass in the 8-bit bus number
75 ** and not the 8-bit "PCI Segment" number. Each Dino will be
76 ** assigned a PCI bus number based on "when" it's discovered.
78 ** The "secondary" bus number is set to this before calling
79 ** pci_scan_bus(). If any PPB's are present, the scan will
80 ** discover them and update the "secondary" and "subordinate"
81 ** fields in Dino's pci_bus structure.
83 ** Changes in the configuration *will* result in a different
84 ** bus number for each dino.
87 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
89 #define DINO_IAR0 0x004
90 #define DINO_IODC_ADDR 0x008
91 #define DINO_IODC_DATA_0 0x008
92 #define DINO_IODC_DATA_1 0x008
93 #define DINO_IRR0 0x00C
94 #define DINO_IAR1 0x010
95 #define DINO_IRR1 0x014
96 #define DINO_IMR 0x018
97 #define DINO_IPR 0x01C
98 #define DINO_TOC_ADDR 0x020
99 #define DINO_ICR 0x024
100 #define DINO_ILR 0x028
101 #define DINO_IO_COMMAND 0x030
102 #define DINO_IO_STATUS 0x034
103 #define DINO_IO_CONTROL 0x038
104 #define DINO_IO_GSC_ERR_RESP 0x040
105 #define DINO_IO_ERR_INFO 0x044
106 #define DINO_IO_PCI_ERR_RESP 0x048
107 #define DINO_IO_FBB_EN 0x05c
108 #define DINO_IO_ADDR_EN 0x060
109 #define DINO_PCI_ADDR 0x064
110 #define DINO_CONFIG_DATA 0x068
111 #define DINO_IO_DATA 0x06c
112 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
113 #define DINO_GSC2X_CONFIG 0x7b4
114 #define DINO_GMASK 0x800
115 #define DINO_PAMR 0x804
116 #define DINO_PAPR 0x808
117 #define DINO_DAMODE 0x80c
118 #define DINO_PCICMD 0x810
119 #define DINO_PCISTS 0x814
120 #define DINO_MLTIM 0x81c
121 #define DINO_BRDG_FEAT 0x820
122 #define DINO_PCIROR 0x824
123 #define DINO_PCIWOR 0x828
124 #define DINO_TLTIM 0x830
126 #define DINO_IRQS 11 /* bits 0-10 are architected */
127 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
129 #define DINO_MASK_IRQ(x) (1<<(x))
131 #define PCIINTA 0x001
132 #define PCIINTB 0x002
133 #define PCIINTC 0x004
134 #define PCIINTD 0x008
135 #define PCIINTE 0x010
136 #define PCIINTF 0x020
137 #define GSCEXTINT 0x040
138 /* #define xxx 0x080 - bit 7 is "default" */
139 /* #define xxx 0x100 - bit 8 not used */
140 /* #define xxx 0x200 - bit 9 not used */
141 #define RS232INT 0x400
143 struct dino_device
145 struct pci_hba_data hba; /* 'C' inheritance - must be first */
146 spinlock_t dinosaur_pen;
147 unsigned long txn_addr; /* EIR addr to generate interrupt */
148 u32 txn_data; /* EIR data assign to each dino */
149 int irq; /* Virtual IRQ dino uses */
150 struct irq_region *dino_region; /* region for this Dino */
152 u32 imr; /* IRQ's which are enabled */
153 #ifdef DINO_DEBUG
154 unsigned int dino_irr0; /* save most recent IRQ line stat */
155 #endif
158 /* Looks nice and keeps the compiler happy */
159 #define DINO_DEV(d) ((struct dino_device *) d)
163 * Dino Configuration Space Accessor Functions
166 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
169 * keep the current highest bus count to assist in allocating busses. This
170 * tries to keep a global bus count total so that when we discover an
171 * entirely new bus, it can be given a unique bus number.
173 static int dino_current_bus = 0;
175 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
176 int size, u32 *val)
178 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
179 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
180 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
181 unsigned long base_addr = d->hba.base_addr;
182 unsigned long flags;
184 spin_lock_irqsave(&d->dinosaur_pen, flags);
186 /* tell HW which CFG address */
187 gsc_writel(v, base_addr + DINO_PCI_ADDR);
189 /* generate cfg read cycle */
190 if (size == 1) {
191 *val = gsc_readb(base_addr + DINO_CONFIG_DATA + (where & 3));
192 } else if (size == 2) {
193 *val = le16_to_cpu(gsc_readw(base_addr +
194 DINO_CONFIG_DATA + (where & 2)));
195 } else if (size == 4) {
196 *val = le32_to_cpu(gsc_readl(base_addr + DINO_CONFIG_DATA));
199 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
200 return 0;
204 * Dino address stepping "feature":
205 * When address stepping, Dino attempts to drive the bus one cycle too soon
206 * even though the type of cycle (config vs. MMIO) might be different.
207 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
209 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
210 int size, u32 val)
212 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
213 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
214 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
215 unsigned long base_addr = d->hba.base_addr;
216 unsigned long flags;
218 spin_lock_irqsave(&d->dinosaur_pen, flags);
220 /* avoid address stepping feature */
221 gsc_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
222 gsc_readl(base_addr + DINO_CONFIG_DATA);
224 /* tell HW which CFG address */
225 gsc_writel(v, base_addr + DINO_PCI_ADDR);
226 /* generate cfg read cycle */
227 if (size == 1) {
228 gsc_writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
229 } else if (size == 2) {
230 gsc_writew(cpu_to_le16(val),
231 base_addr + DINO_CONFIG_DATA + (where & 2));
232 } else if (size == 4) {
233 gsc_writel(cpu_to_le32(val), base_addr + DINO_CONFIG_DATA);
236 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
237 return 0;
240 static struct pci_ops dino_cfg_ops = {
241 .read = dino_cfg_read,
242 .write = dino_cfg_write,
247 * Dino "I/O Port" Space Accessor Functions
249 * Many PCI devices don't require use of I/O port space (eg Tulip,
250 * NCR720) since they export the same registers to both MMIO and
251 * I/O port space. Performance is going to stink if drivers use
252 * I/O port instead of MMIO.
255 #define cpu_to_le8(x) (x)
256 #define le8_to_cpu(x) (x)
258 #define DINO_PORT_IN(type, size, mask) \
259 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
261 u##size v; \
262 unsigned long flags; \
263 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
264 /* tell HW which IO Port address */ \
265 gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
266 /* generate I/O PORT read cycle */ \
267 v = gsc_read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
268 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
269 return le##size##_to_cpu(v); \
272 DINO_PORT_IN(b, 8, 3)
273 DINO_PORT_IN(w, 16, 2)
274 DINO_PORT_IN(l, 32, 0)
276 #define DINO_PORT_OUT(type, size, mask) \
277 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
279 unsigned long flags; \
280 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
281 /* tell HW which IO port address */ \
282 gsc_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
283 /* generate cfg write cycle */ \
284 gsc_write##type(cpu_to_le##size(val), d->base_addr+DINO_IO_DATA+(addr&mask)); \
285 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
288 DINO_PORT_OUT(b, 8, 3)
289 DINO_PORT_OUT(w, 16, 2)
290 DINO_PORT_OUT(l, 32, 0)
292 struct pci_port_ops dino_port_ops = {
293 .inb = dino_in8,
294 .inw = dino_in16,
295 .inl = dino_in32,
296 .outb = dino_out8,
297 .outw = dino_out16,
298 .outl = dino_out32
301 static void
302 dino_mask_irq(void *irq_dev, int irq)
304 struct dino_device *dino_dev = DINO_DEV(irq_dev);
306 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
308 if (NULL == irq_dev || irq > DINO_IRQS || irq < 0) {
309 printk(KERN_WARNING "%s(0x%lx, %d) - not a dino irq?\n",
310 __FUNCTION__, (long) irq_dev, irq);
311 BUG();
312 } else {
314 ** Clear the matching bit in the IMR register
316 dino_dev->imr &= ~(DINO_MASK_IRQ(irq));
317 gsc_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
322 static void
323 dino_unmask_irq(void *irq_dev, int irq)
325 struct dino_device *dino_dev = DINO_DEV(irq_dev);
326 u32 tmp;
328 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq);
330 if (NULL == irq_dev || irq > DINO_IRQS) {
331 printk(KERN_WARNING "%s(): %d not a dino irq?\n",
332 __FUNCTION__, irq);
333 BUG();
334 return;
337 /* set the matching bit in the IMR register */
338 dino_dev->imr |= DINO_MASK_IRQ(irq); /* used in dino_isr() */
339 gsc_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
341 /* Emulate "Level Triggered" Interrupt
342 ** Basically, a driver is blowing it if the IRQ line is asserted
343 ** while the IRQ is disabled. But tulip.c seems to do that....
344 ** Give 'em a kluge award and a nice round of applause!
346 ** The gsc_write will generate an interrupt which invokes dino_isr().
347 ** dino_isr() will read IPR and find nothing. But then catch this
348 ** when it also checks ILR.
350 tmp = gsc_readl(dino_dev->hba.base_addr+DINO_ILR);
351 if (tmp & DINO_MASK_IRQ(irq)) {
352 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
353 __FUNCTION__, tmp);
354 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
360 static void
361 dino_enable_irq(void *irq_dev, int irq)
363 struct dino_device *dino_dev = DINO_DEV(irq_dev);
366 ** clear pending IRQ bits
368 ** This does NOT change ILR state!
369 ** See comments in dino_unmask_irq() for ILR usage.
371 gsc_readl(dino_dev->hba.base_addr+DINO_IPR);
373 dino_unmask_irq(irq_dev, irq);
377 static struct irq_region_ops dino_irq_ops = {
378 .disable_irq = dino_mask_irq, /* ??? */
379 .enable_irq = dino_enable_irq,
380 .mask_irq = dino_mask_irq,
381 .unmask_irq = dino_unmask_irq
386 * Handle a Processor interrupt generated by Dino.
388 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
389 * wedging the CPU. Could be removed or made optional at some point.
391 static irqreturn_t
392 dino_isr(int irq, void *intr_dev, struct pt_regs *regs)
394 struct dino_device *dino_dev = DINO_DEV(intr_dev);
395 u32 mask;
396 int ilr_loop = 100;
397 extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
400 /* read and acknowledge pending interrupts */
401 #ifdef DINO_DEBUG
402 dino_dev->dino_irr0 =
403 #endif
404 mask = gsc_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
406 ilr_again:
407 while (mask)
409 int irq;
411 irq = __ffs(mask);
413 mask &= ~(1<<irq);
415 DBG(KERN_WARNING "%s(%x, %p) mask %0x\n",
416 __FUNCTION__, irq, intr_dev, mask);
417 do_irq(&dino_dev->dino_region->action[irq],
418 dino_dev->dino_region->data.irqbase + irq,
419 regs);
423 /* Support for level triggered IRQ lines.
425 ** Dropping this support would make this routine *much* faster.
426 ** But since PCI requires level triggered IRQ line to share lines...
427 ** device drivers may assume lines are level triggered (and not
428 ** edge triggered like EISA/ISA can be).
430 mask = gsc_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
431 if (mask) {
432 if (--ilr_loop > 0)
433 goto ilr_again;
434 printk(KERN_ERR "Dino %lx: stuck interrupt %d\n", dino_dev->hba.base_addr, mask);
435 return IRQ_NONE;
437 return IRQ_HANDLED;
440 static int dino_choose_irq(struct parisc_device *dev)
442 int irq = -1;
444 switch (dev->id.sversion) {
445 case 0x00084: irq = 8; break; /* PS/2 */
446 case 0x0008c: irq = 10; break; /* RS232 */
447 case 0x00096: irq = 8; break; /* PS/2 */
450 return irq;
453 static void __init
454 dino_bios_init(void)
456 DBG("dino_bios_init\n");
460 * dino_card_setup - Set up the memory space for a Dino in card mode.
461 * @bus: the bus under this dino
463 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
464 * to set up the addresses of the devices on this bus.
466 #define _8MB 0x00800000UL
467 static void __init
468 dino_card_setup(struct pci_bus *bus, unsigned long base_addr)
470 int i;
471 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
472 struct resource *res;
473 char name[128];
474 int size;
476 res = &dino_dev->hba.lmmio_space;
477 res->flags = IORESOURCE_MEM;
478 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", bus->bridge->bus_id);
479 res->name = kmalloc(size+1, GFP_KERNEL);
480 if(res->name)
481 strcpy((char *)res->name, name);
482 else
483 res->name = dino_dev->hba.lmmio_space.name;
486 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
487 F_EXTEND(0xf0000000UL) | _8MB,
488 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
489 struct list_head *ln, *tmp_ln;
491 printk(KERN_ERR "Dino: cannot attach bus %s\n",
492 bus->bridge->bus_id);
493 /* kill the bus, we can't do anything with it */
494 list_for_each_safe(ln, tmp_ln, &bus->devices) {
495 struct pci_dev *dev = pci_dev_b(ln);
497 list_del(&dev->global_list);
498 list_del(&dev->bus_list);
501 return;
503 bus->resource[1] = res;
504 bus->resource[0] = &(dino_dev->hba.io_space);
506 /* Now tell dino what range it has */
507 for (i = 1; i < 31; i++) {
508 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
509 break;
511 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %lx\n",
512 i, res->start, base_addr + DINO_IO_ADDR_EN);
513 gsc_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
516 static void __init
517 dino_card_fixup(struct pci_dev *dev)
519 u32 irq_pin;
522 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
523 ** Not sure they were ever productized.
524 ** Die here since we'll die later in dino_inb() anyway.
526 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
527 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
531 ** Set Latency Timer to 0xff (not a shared bus)
532 ** Set CACHELINE_SIZE.
534 dino_cfg_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
537 ** Program INT_LINE for card-mode devices.
538 ** The cards are hardwired according to this algorithm.
539 ** And it doesn't matter if PPB's are present or not since
540 ** the IRQ lines bypass the PPB.
542 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
543 ** The additional "-1" adjusts for skewing the IRQ<->slot.
545 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
546 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
548 /* Shouldn't really need to do this but it's in case someone tries
549 ** to bypass PCI services and look at the card themselves.
551 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
554 /* The alignment contraints for PCI bridges under dino */
555 #define DINO_BRIDGE_ALIGN 0x100000
558 static void __init
559 dino_fixup_bus(struct pci_bus *bus)
561 struct list_head *ln;
562 struct pci_dev *dev;
563 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
564 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
566 DBG(KERN_WARNING "%s(0x%p) bus %d sysdata 0x%p\n",
567 __FUNCTION__, bus, bus->secondary, bus->bridge->platform_data);
569 /* Firmware doesn't set up card-mode dino, so we have to */
570 if (is_card_dino(&dino_dev->hba.dev->id)) {
571 dino_card_setup(bus, dino_dev->hba.base_addr);
572 } else if(bus->parent == NULL) {
573 /* must have a dino above it, reparent the resources
574 * into the dino window */
575 int i;
576 struct resource *res = &dino_dev->hba.lmmio_space;
578 bus->resource[0] = &(dino_dev->hba.io_space);
579 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
580 if(res[i].flags == 0)
581 break;
582 bus->resource[i+1] = &res[i];
585 } else if(bus->self) {
586 int i;
588 pci_read_bridge_bases(bus);
591 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
592 if((bus->self->resource[i].flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
593 continue;
595 if(bus->self->resource[i].flags & IORESOURCE_MEM) {
596 /* There's a quirk to alignment of
597 * bridge memory resources: the start
598 * is the alignment and start-end is
599 * the size. However, firmware will
600 * have assigned start and end, so we
601 * need to take this into account */
602 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
603 bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
607 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
608 bus->self->dev.bus_id, i,
609 bus->self->resource[i].start,
610 bus->self->resource[i].end);
611 pci_assign_resource(bus->self, i);
612 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
613 bus->self->dev.bus_id, i,
614 bus->self->resource[i].start,
615 bus->self->resource[i].end);
620 list_for_each(ln, &bus->devices) {
621 int i;
623 dev = pci_dev_b(ln);
624 if (is_card_dino(&dino_dev->hba.dev->id))
625 dino_card_fixup(dev);
628 ** P2PB's only have 2 BARs, no IRQs.
629 ** I'd like to just ignore them for now.
631 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
632 continue;
634 /* Adjust the I/O Port space addresses */
635 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
636 struct resource *res = &dev->resource[i];
637 if (res->flags & IORESOURCE_IO) {
638 res->start |= port_base;
639 res->end |= port_base;
641 #ifdef __LP64__
642 /* Sign Extend MMIO addresses */
643 else if (res->flags & IORESOURCE_MEM) {
644 res->start |= F_EXTEND(0UL);
645 res->end |= F_EXTEND(0UL);
647 #endif
649 /* null out the ROM resource if there is one (we don't
650 * care about an expansion rom on parisc, since it
651 * usually contains (x86) bios code) */
652 dev->resource[PCI_ROM_RESOURCE].flags = 0;
654 if(dev->irq == 255) {
656 #define DINO_FIX_UNASSIGNED_INTERRUPTS
657 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
659 /* This code tries to assign an unassigned
660 * interrupt. Leave it disabled unless you
661 * *really* know what you're doing since the
662 * pin<->interrupt line mapping varies by bus
663 * and machine */
665 u32 irq_pin;
667 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
668 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
669 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
670 dev->irq += dino_dev->dino_region->data.irqbase;
671 printk(KERN_WARNING "Device %s has undefined IRQ, setting to %d\n", dev->slot_name, irq_pin);
672 #else
673 dev->irq = 65535;
674 printk(KERN_WARNING "Device %s has unassigned IRQ\n", dev->slot_name);
675 #endif
676 } else {
678 /* Adjust INT_LINE for that busses region */
679 dev->irq += dino_dev->dino_region->data.irqbase;
685 struct pci_bios_ops dino_bios_ops = {
686 .init = dino_bios_init,
687 .fixup_bus = dino_fixup_bus
692 * Initialise a DINO controller chip
694 static void __init
695 dino_card_init(struct dino_device *dino_dev)
697 u32 brdg_feat = 0x00784e05;
699 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
700 gsc_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
701 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
703 #if 1
704 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
706 ** PCX-L processors don't support XQL like Dino wants it.
707 ** PCX-L2 ignore XQL signal and it doesn't matter.
709 brdg_feat &= ~0x4; /* UXQL */
710 #endif
711 gsc_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
714 ** Don't enable address decoding until we know which I/O range
715 ** currently is available from the host. Only affects MMIO
716 ** and not I/O port space.
718 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
720 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
721 gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
722 gsc_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
724 gsc_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
725 gsc_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
726 gsc_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
728 /* Disable PAMR before writing PAPR */
729 gsc_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
730 gsc_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
731 gsc_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
734 ** Dino ERS encourages enabling FBB (0x6f).
735 ** We can't until we know *all* devices below us can support it.
736 ** (Something in device configuration header tells us).
738 gsc_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
740 /* Somewhere, the PCI spec says give devices 1 second
741 ** to recover from the #RESET being de-asserted.
742 ** Experience shows most devices only need 10ms.
743 ** This short-cut speeds up booting significantly.
745 mdelay(pci_post_reset_delay);
748 static int __init
749 dino_bridge_init(struct dino_device *dino_dev, const char *name)
751 unsigned long io_addr;
752 int result, i, count=0;
753 struct resource *res, *prevres = NULL;
755 * Decoding IO_ADDR_EN only works for Built-in Dino
756 * since PDC has already initialized this.
759 io_addr = gsc_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
760 if (io_addr == 0) {
761 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
762 return -ENODEV;
765 res = &dino_dev->hba.lmmio_space;
766 for (i = 0; i < 32; i++) {
767 unsigned long start, end;
769 if((io_addr & (1 << i)) == 0)
770 continue;
772 start = (unsigned long)(signed int)(0xf0000000 | (i << 23));
773 end = start + 8 * 1024 * 1024 - 1;
775 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
776 start, end);
778 if(prevres && prevres->end + 1 == start) {
779 prevres->end = end;
780 } else {
781 if(count >= DINO_MAX_LMMIO_RESOURCES) {
782 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
783 break;
785 prevres = res;
786 res->start = start;
787 res->end = end;
788 res->flags = IORESOURCE_MEM;
789 res->name = kmalloc(64, GFP_KERNEL);
790 if(res->name)
791 snprintf((char *)res->name, 64, "%s LMMIO %d",
792 name, count);
793 res++;
794 count++;
798 res = &dino_dev->hba.lmmio_space;
800 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
801 if(res[i].flags == 0)
802 break;
804 result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
805 if (result < 0) {
806 printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end);
807 return result;
810 return 0;
813 static int __init dino_common_init(struct parisc_device *dev,
814 struct dino_device *dino_dev, const char *name)
816 int status;
817 u32 eim;
818 struct gsc_irq gsc_irq;
819 struct resource *res;
821 pcibios_register_hba(&dino_dev->hba);
823 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
824 pci_port = &dino_port_ops;
827 ** Note: SMP systems can make use of IRR1/IAR1 registers
828 ** But it won't buy much performance except in very
829 ** specific applications/configurations. Note Dino
830 ** still only has 11 IRQ input lines - just map some of them
831 ** to a different processor.
833 dino_dev->irq = gsc_alloc_irq(&gsc_irq);
834 dino_dev->txn_addr = gsc_irq.txn_addr;
835 dino_dev->txn_data = gsc_irq.txn_data;
836 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
839 ** Dino needs a PA "IRQ" to get a processor's attention.
840 ** arch/parisc/kernel/irq.c returns an EIRR bit.
842 if (dino_dev->irq < 0) {
843 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
844 return 1;
847 status = request_irq(dino_dev->irq, dino_isr, 0, name, dino_dev);
848 if (status) {
849 printk(KERN_WARNING "%s: request_irq() failed with %d\n",
850 name, status);
851 return 1;
855 ** Tell generic interrupt support we have 11 bits which need
856 ** be checked in the interrupt handler.
858 dino_dev->dino_region = alloc_irq_region(DINO_IRQS, &dino_irq_ops,
859 name, dino_dev);
861 if (NULL == dino_dev->dino_region) {
862 printk(KERN_WARNING "%s: alloc_irq_region() failed\n", name);
863 return 1;
866 /* Support the serial port which is sometimes attached on built-in
867 * Dino / Cujo chips.
870 fixup_child_irqs(dev, dino_dev->dino_region->data.irqbase,
871 dino_choose_irq);
874 ** This enables DINO to generate interrupts when it sees
875 ** any of its inputs *change*. Just asserting an IRQ
876 ** before it's enabled (ie unmasked) isn't good enough.
878 gsc_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
881 ** Some platforms don't clear Dino's IRR0 register at boot time.
882 ** Reading will clear it now.
884 gsc_readl(dino_dev->hba.base_addr+DINO_IRR0);
886 /* allocate I/O Port resource region */
887 res = &dino_dev->hba.io_space;
888 if (dev->id.hversion == 0x680 || is_card_dino(&dev->id)) {
889 res->name = "Dino I/O Port";
890 } else {
891 res->name = "Cujo I/O Port";
893 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
894 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
895 res->flags = IORESOURCE_IO; /* do not mark it busy ! */
896 if (request_resource(&ioport_resource, res) < 0) {
897 printk(KERN_ERR "%s: request I/O Port region failed 0x%lx/%lx (hpa 0x%lx)\n",
898 name, res->start, res->end, dino_dev->hba.base_addr);
899 return 1;
902 return 0;
905 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
906 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
907 #define CUJO_RAVEN_BADPAGE 0x01003000UL
908 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
910 static const char *dino_vers[] = {
911 "2.0",
912 "2.1",
913 "3.0",
914 "3.1"
917 static const char *cujo_vers[] = {
918 "1.0",
919 "2.0"
922 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
925 ** Determine if dino should claim this chip (return 0) or not (return 1).
926 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
927 ** Much of the initialization is common though.
929 static int __init
930 dino_driver_callback(struct parisc_device *dev)
932 struct dino_device *dino_dev; // Dino specific control struct
933 const char *version = "unknown";
934 const int name_len = 32;
935 char hw_path[64];
936 char *name;
937 int is_cujo = 0;
938 struct pci_bus *bus;
940 name = kmalloc(name_len, GFP_KERNEL);
941 if(name) {
942 print_pa_hwpath(dev, hw_path);
943 snprintf(name, name_len, "Dino [%s]", hw_path);
945 else
946 name = "Dino";
948 if (is_card_dino(&dev->id)) {
949 version = "3.x (card mode)";
950 } else {
951 if(dev->id.hversion == 0x680) {
952 if (dev->id.hversion_rev < 4) {
953 version = dino_vers[dev->id.hversion_rev];
955 } else {
956 name = "Cujo";
957 is_cujo = 1;
958 if (dev->id.hversion_rev < 2) {
959 version = cujo_vers[dev->id.hversion_rev];
964 printk("%s version %s found at 0x%lx\n", name, version, dev->hpa);
966 if (!request_mem_region(dev->hpa, PAGE_SIZE, name)) {
967 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
968 dev->hpa);
969 return 1;
972 /* Check for bugs */
973 if (is_cujo && dev->id.hversion_rev == 1) {
974 #ifdef CONFIG_IOMMU_CCIO
975 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
976 if (dev->hpa == (unsigned long)CUJO_RAVEN_ADDR) {
977 ccio_cujo20_fixup(dev->parent, CUJO_RAVEN_BADPAGE);
978 } else if (dev->hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
979 ccio_cujo20_fixup(dev->parent, CUJO_FIREHAWK_BADPAGE);
980 } else {
981 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", dev->hpa);
983 #endif
984 } else if (!is_cujo && !is_card_dino(&dev->id) &&
985 dev->id.hversion_rev < 3) {
986 printk(KERN_WARNING
987 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
988 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
989 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
990 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
991 dev->id.hversion_rev);
992 /* REVISIT: why are C200/C240 listed in the README table but not
993 ** "Models affected"? Could be an omission in the original literature.
997 dino_dev = kmalloc(sizeof(struct dino_device), GFP_KERNEL);
998 if (!dino_dev) {
999 printk("dino_init_chip - couldn't alloc dino_device\n");
1000 return 1;
1003 memset(dino_dev, 0, sizeof(struct dino_device));
1005 dino_dev->hba.dev = dev;
1006 dino_dev->hba.base_addr = dev->hpa; /* faster access */
1007 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */
1008 dino_dev->dinosaur_pen = SPIN_LOCK_UNLOCKED;
1009 dino_dev->hba.iommu = ccio_get_iommu(dev);
1011 if (is_card_dino(&dev->id)) {
1012 dino_card_init(dino_dev);
1013 } else {
1014 dino_bridge_init(dino_dev, name);
1017 if (dino_common_init(dev, dino_dev, name))
1018 return 1;
1020 dev->dev.platform_data = dino_dev;
1023 ** It's not used to avoid chicken/egg problems
1024 ** with configuration accessor functions.
1026 bus = pci_scan_bus_parented(&dev->dev, dino_current_bus,
1027 &dino_cfg_ops, NULL);
1028 if(bus) {
1029 /* This code *depends* on scanning being single threaded
1030 * if it isn't, this global bus number count will fail
1032 dino_current_bus = bus->subordinate + 1;
1033 pci_bus_assign_resources(bus);
1034 } else {
1035 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus);
1036 /* increment the bus number in case of duplicates */
1037 dino_current_bus++;
1039 dino_dev->hba.hba_bus = bus;
1040 return 0;
1044 * Normally, we would just test sversion. But the Elroy PCI adapter has
1045 * the same sversion as Dino, so we have to check hversion as well.
1046 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1047 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1048 * For card-mode Dino, most machines report an sversion of 9D. But 715
1049 * and 725 firmware misreport it as 0x08080 for no adequately explained
1050 * reason.
1052 static struct parisc_device_id dino_tbl[] = {
1053 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1054 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1055 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1056 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1057 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1058 { 0, }
1061 static struct parisc_driver dino_driver = {
1062 .name = "Dino",
1063 .id_table = dino_tbl,
1064 .probe = dino_driver_callback,
1068 * One time initialization to let the world know Dino is here.
1069 * This is the only routine which is NOT static.
1070 * Must be called exactly once before pci_init().
1072 int __init dino_init(void)
1074 register_parisc_driver(&dino_driver);
1075 return 0;