drivers/mtd/maps/integrator-flash-v24.c

   1 /*======================================================================
   2
   3     drivers/mtd/maps/armflash.c: ARM Flash Layout/Partitioning
   4
   5     Copyright (C) 2000 ARM Limited
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20
  21    This is access code for flashes using ARM's flash partitioning
  22    standards.
  23
  24    $Id: integrator-flash-v24.c,v 1.13 2004/07/12 21:59:44 dwmw2 Exp $
  25
  26 ======================================================================*/
  27
  28 #include <linux/config.h>
  29 #include <linux/module.h>
  30 #include <linux/types.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/ioport.h>
  34 #include <linux/init.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/map.h>
  38 #include <linux/mtd/partitions.h>
  39
  40 #include <asm/hardware.h>
  41 #include <asm/io.h>
  42 #include <asm/system.h>
  43
  44 // board specific stuff - sorry, it should be in arch/arm/mach-*.
  45 #ifdef CONFIG_ARCH_INTEGRATOR
  46
  47 #define FLASH_BASE      INTEGRATOR_FLASH_BASE
  48 #define FLASH_SIZE      INTEGRATOR_FLASH_SIZE
  49
  50 #define FLASH_PART_SIZE 0x400000
  51
  52 #define SC_CTRLC        (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
  53 #define SC_CTRLS        (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
  54 #define EBI_CSR1        (IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_CSR1_OFFSET)
  55 #define EBI_LOCK        (IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_LOCK_OFFSET)
  56
  57 /*
  58  * Initialise the flash access systems:
  59  *  - Disable VPP
  60  *  - Assert WP
  61  *  - Set write enable bit in EBI reg
  62  */
  63 static void armflash_flash_init(void)
  64 {
  65         unsigned int tmp;
  66
  67         __raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
  68
  69         tmp = __raw_readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
  70         __raw_writel(tmp, EBI_CSR1);
  71
  72         if (!(__raw_readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
  73                 __raw_writel(0xa05f, EBI_LOCK);
  74                 __raw_writel(tmp, EBI_CSR1);
  75                 __raw_writel(0, EBI_LOCK);
  76         }
  77 }
  78
  79 /*
  80  * Shutdown the flash access systems:
  81  *  - Disable VPP
  82  *  - Assert WP
  83  *  - Clear write enable bit in EBI reg
  84  */
  85 static void armflash_flash_exit(void)
  86 {
  87         unsigned int tmp;
  88
  89         __raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
  90
  91         /*
  92          * Clear the write enable bit in system controller EBI register.
  93          */
  94         tmp = __raw_readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
  95         __raw_writel(tmp, EBI_CSR1);
  96
  97         if (__raw_readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
  98                 __raw_writel(0xa05f, EBI_LOCK);
  99                 __raw_writel(tmp, EBI_CSR1);
 100                 __raw_writel(0, EBI_LOCK);
 101         }
 102 }
 103
 104 static void armflash_flash_wp(int on)
 105 {
 106         unsigned int reg;
 107
 108         if (on)
 109                 reg = SC_CTRLC;
 110         else
 111                 reg = SC_CTRLS;
 112
 113         __raw_writel(INTEGRATOR_SC_CTRL_nFLWP, reg);
 114 }
 115
 116 static void armflash_set_vpp(struct map_info *map, int on)
 117 {
 118         unsigned int reg;
 119
 120         if (on)
 121                 reg = SC_CTRLS;
 122         else
 123                 reg = SC_CTRLC;
 124
 125         __raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 126 }
 127 #endif
 128
 129 #ifdef CONFIG_ARCH_P720T
 130
 131 #define FLASH_BASE              (0x04000000)
 132 #define FLASH_SIZE              (64*1024*1024)
 133
 134 #define FLASH_PART_SIZE         (4*1024*1024)
 135 #define FLASH_BLOCK_SIZE        (128*1024)
 136
 137 static void armflash_flash_init(void)
 138 {
 139 }
 140
 141 static void armflash_flash_exit(void)
 142 {
 143 }
 144
 145 static void armflash_flash_wp(int on)
 146 {
 147 }
 148
 149 static void armflash_set_vpp(struct map_info *map, int on)
 150 {
 151 }
 152 #endif
 153
 154
 155 static struct map_info armflash_map =
 156 {
 157         .name =         "AFS",
 158         .set_vpp =      armflash_set_vpp,
 159         .phys =         FLASH_BASE,
 160 };
 161
 162 static struct mtd_info *mtd;
 163 static struct mtd_partition *parts;
 164 static const char *probes[] = { "RedBoot", "afs", NULL };
 165
 166 static int __init armflash_cfi_init(void *base, u_int size)
 167 {
 168         int ret;
 169
 170         armflash_flash_init();
 171         armflash_flash_wp(1);
 172
 173         /*
 174          * look for CFI based flash parts fitted to this board
 175          */
 176         armflash_map.size       = size;
 177         armflash_map.bankwidth   = 4;
 178         armflash_map.virt = (unsigned long) base;
 179
 180         simple_map_init(&armflash_map);
 181
 182         /*
 183          * Also, the CFI layer automatically works out what size
 184          * of chips we have, and does the necessary identification
 185          * for us automatically.
 186          */
 187         mtd = do_map_probe("cfi_probe", &armflash_map);
 188         if (!mtd)
 189                 return -ENXIO;
 190
 191         mtd->owner = THIS_MODULE;
 192
 193         ret = parse_mtd_partitions(mtd, probes, &parts, (void *)0);
 194         if (ret > 0) {
 195                 ret = add_mtd_partitions(mtd, parts, ret);
 196                 if (ret)
 197                         printk(KERN_ERR "mtd partition registration "
 198                                 "failed: %d\n", ret);
 199         }
 200
 201         /*
 202          * If we got an error, free all resources.
 203          */
 204         if (ret < 0) {
 205                 del_mtd_partitions(mtd);
 206                 map_destroy(mtd);
 207         }
 208
 209         return ret;
 210 }
 211
 212 static void armflash_cfi_exit(void)
 213 {
 214         if (mtd) {
 215                 del_mtd_partitions(mtd);
 216                 map_destroy(mtd);
 217         }
 218         if (parts)
 219                 kfree(parts);
 220 }
 221
 222 static int __init armflash_init(void)
 223 {
 224         int err = -EBUSY;
 225         void *base;
 226
 227         if (request_mem_region(FLASH_BASE, FLASH_SIZE, "flash") == NULL)
 228                 goto out;
 229
 230         base = ioremap(FLASH_BASE, FLASH_SIZE);
 231         err = -ENOMEM;
 232         if (base == NULL)
 233                 goto release;
 234
 235         err = armflash_cfi_init(base, FLASH_SIZE);
 236         if (err) {
 237                 iounmap(base);
 238 release:
 239                 release_mem_region(FLASH_BASE, FLASH_SIZE);
 240         }
 241 out:
 242         return err;
 243 }
 244
 245 static void __exit armflash_exit(void)
 246 {
 247         armflash_cfi_exit();
 248         iounmap((void *)armflash_map.virt);
 249         release_mem_region(FLASH_BASE, FLASH_SIZE);
 250         armflash_flash_exit();
 251 }
 252
 253 module_init(armflash_init);
 254 module_exit(armflash_exit);
 255
 256 MODULE_AUTHOR("ARM Ltd");
 257 MODULE_DESCRIPTION("ARM Integrator CFI map driver");
 258 MODULE_LICENSE("GPL");