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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / ide / pci / cmd64x.c
blobabea997dc29f5c12bcf2a71eb6187e75b7b6466e
1 /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2 *
3 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
4 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
10 *
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
13 *
14 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
15 */
16
17 #include <linux/config.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/hdreg.h>
23 #include <linux/ide.h>
24 #include <linux/init.h>
25
26 #include <asm/io.h>
27
28 #include "cmd64x.h"
29
30 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
31 #include <linux/stat.h>
32 #include <linux/proc_fs.h>
33
34 static u8 cmd64x_proc = 0;
35
36 #define CMD_MAX_DEVS 5
37
38 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
39 static int n_cmd_devs;
40
41 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
42 {
43 char *p = buf;
44
45 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
46 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
47 u8 reg72 = 0, reg73 = 0; /* primary */
48 u8 reg7a = 0, reg7b = 0; /* secondary */
49 u8 reg50 = 0, reg71 = 0; /* extra */
50
51 p += sprintf(p, "\nController: %d\n", index);
52 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
53 (void) pci_read_config_byte(dev, CFR, &reg50);
54 (void) pci_read_config_byte(dev, ARTTIM0, &reg53);
55 (void) pci_read_config_byte(dev, DRWTIM0, &reg54);
56 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
57 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
58 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
59 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
60 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
61 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
62 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
63 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
64 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
65 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
66
67 p += sprintf(p, "--------------- Primary Channel "
68 "---------------- Secondary Channel "
69 "-------------\n");
70 p += sprintf(p, " %sabled "
71 " %sabled\n",
72 (reg72&0x80)?"dis":" en",
73 (reg7a&0x80)?"dis":" en");
74 p += sprintf(p, "--------------- drive0 "
75 "--------- drive1 -------- drive0 "
76 "---------- drive1 ------\n");
77 p += sprintf(p, "DMA enabled: %s %s"
78 " %s %s\n",
79 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
80 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
81
82 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
83 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
84 (reg72&0x20)?(
85 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
86 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
87 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
88 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
89 "X"):"?",
90 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
91 (reg72&0x40)?(
92 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
93 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
94 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
95 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
96 "X"):"?");
97 p += sprintf(p, " %s(%s) %s(%s)\n",
98 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
99 (reg7a&0x20)?(
100 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
101 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
102 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
103 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
104 "X"):"?",
105 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
106 (reg7a&0x40)?(
107 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
108 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
109 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
110 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
111 "X"):"?" );
112 p += sprintf(p, "PIO Mode: %s %s"
113 " %s %s\n",
114 "?", "?", "?", "?");
115 p += sprintf(p, " %s %s\n",
116 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
117 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
118 p += sprintf(p, " %s %s\n",
119 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
120 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
121 p += sprintf(p, " %s %s\n",
122 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
123 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
124
125 return (char *)p;
126 }
127
128 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
129 {
130 char *p = buffer;
131 int i;
132
133 p += sprintf(p, "\n");
134 for (i = 0; i < n_cmd_devs; i++) {
135 struct pci_dev *dev = cmd_devs[i];
136 p = print_cmd64x_get_info(p, dev, i);
137 }
138 return p-buffer; /* => must be less than 4k! */
139 }
140
141 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
142
143 /*
144 * Registers and masks for easy access by drive index:
145 */
146 #if 0
147 static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
148 static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
149 #endif
150
151 /*
152 * This routine writes the prepared setup/active/recovery counts
153 * for a drive into the cmd646 chipset registers to active them.
154 */
155 static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
156 {
157 unsigned long flags;
158 struct pci_dev *dev = HWIF(drive)->pci_dev;
159 ide_drive_t *drives = HWIF(drive)->drives;
160 u8 temp_b;
161 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
162 static const u8 recovery_counts[] =
163 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
164 static const u8 arttim_regs[2][2] = {
165 { ARTTIM0, ARTTIM1 },
166 { ARTTIM23, ARTTIM23 }
167 };
168 static const u8 drwtim_regs[2][2] = {
169 { DRWTIM0, DRWTIM1 },
170 { DRWTIM2, DRWTIM3 }
171 };
172 int channel = (int) HWIF(drive)->channel;
173 int slave = (drives != drive); /* Is this really the best way to determine this?? */
174
175 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
176 setup_count, active_count, recovery_count, drive->present);
177 /*
178 * Set up address setup count registers.
179 * Primary interface has individual count/timing registers for
180 * each drive. Secondary interface has one common set of registers,
181 * for address setup so we merge these timings, using the slowest
182 * value.
183 */
184 if (channel) {
185 drive->drive_data = setup_count;
186 setup_count = max(drives[0].drive_data,
187 drives[1].drive_data);
188 cmdprintk("Secondary interface, setup_count = %d\n",
189 setup_count);
190 }
191
192 /*
193 * Convert values to internal chipset representation
194 */
195 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
196 active_count &= 0xf; /* Remember, max value is 16 */
197 recovery_count = (int) recovery_counts[recovery_count];
198
199 cmdprintk("Final values = %d,%d,%d\n",
200 setup_count, active_count, recovery_count);
201
202 /*
203 * Now that everything is ready, program the new timings
204 */
205 local_irq_save(flags);
206 /*
207 * Program the address_setup clocks into ARTTIM reg,
208 * and then the active/recovery counts into the DRWTIM reg
209 */
210 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
211 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
212 ((u8) setup_count) | (temp_b & 0x3f));
213 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
214 (u8) ((active_count << 4) | recovery_count));
215 cmdprintk ("Write %x to %x\n",
216 ((u8) setup_count) | (temp_b & 0x3f),
217 arttim_regs[channel][slave]);
218 cmdprintk ("Write %x to %x\n",
219 (u8) ((active_count << 4) | recovery_count),
220 drwtim_regs[channel][slave]);
221 local_irq_restore(flags);
222 }
223
224 /*
225 * Attempts to set the interface PIO mode.
226 * The preferred method of selecting PIO modes (e.g. mode 4) is
227 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
228 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
229 * Called with 255 at boot time.
230 */
231
232 static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted)
233 {
234 int setup_time, active_time, recovery_time;
235 int clock_time, pio_mode, cycle_time;
236 u8 recovery_count2, cycle_count;
237 int setup_count, active_count, recovery_count;
238 int bus_speed = system_bus_clock();
239 /*byte b;*/
240 ide_pio_data_t d;
241
242 switch (mode_wanted) {
243 case 8: /* set prefetch off */
244 case 9: /* set prefetch on */
245 mode_wanted &= 1;
246 /*set_prefetch_mode(index, mode_wanted);*/
247 cmdprintk("%s: %sabled cmd640 prefetch\n",
248 drive->name, mode_wanted ? "en" : "dis");
249 return;
250 }
251
252 mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
253 pio_mode = d.pio_mode;
254 cycle_time = d.cycle_time;
255
256 /*
257 * I copied all this complicated stuff from cmd640.c and made a few
258 * minor changes. For now I am just going to pray that it is correct.
259 */
260 if (pio_mode > 5)
261 pio_mode = 5;
262 setup_time = ide_pio_timings[pio_mode].setup_time;
263 active_time = ide_pio_timings[pio_mode].active_time;
264 recovery_time = cycle_time - (setup_time + active_time);
265 clock_time = 1000 / bus_speed;
266 cycle_count = (cycle_time + clock_time - 1) / clock_time;
267
268 setup_count = (setup_time + clock_time - 1) / clock_time;
269
270 active_count = (active_time + clock_time - 1) / clock_time;
271
272 recovery_count = (recovery_time + clock_time - 1) / clock_time;
273 recovery_count2 = cycle_count - (setup_count + active_count);
274 if (recovery_count2 > recovery_count)
275 recovery_count = recovery_count2;
276 if (recovery_count > 16) {
277 active_count += recovery_count - 16;
278 recovery_count = 16;
279 }
280 if (active_count > 16)
281 active_count = 16; /* maximum allowed by cmd646 */
282
283 /*
284 * In a perfect world, we might set the drive pio mode here
285 * (using WIN_SETFEATURE) before continuing.
286 *
287 * But we do not, because:
288 * 1) this is the wrong place to do it
289 * (proper is do_special() in ide.c)
290 * 2) in practice this is rarely, if ever, necessary
291 */
292 program_drive_counts (drive, setup_count, active_count, recovery_count);
293
294 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, "
295 "clocks=%d/%d/%d\n",
296 drive->name, pio_mode, mode_wanted, cycle_time,
297 d.overridden ? " (overriding vendor mode)" : "",
298 setup_count, active_count, recovery_count);
299 }
300
301 static u8 cmd64x_ratemask (ide_drive_t *drive)
302 {
303 struct pci_dev *dev = HWIF(drive)->pci_dev;
304 u8 mode = 0;
305
306 switch(dev->device) {
307 case PCI_DEVICE_ID_CMD_649:
308 mode = 3;
309 break;
310 case PCI_DEVICE_ID_CMD_648:
311 mode = 2;
312 break;
313 case PCI_DEVICE_ID_CMD_643:
314 return 0;
315
316 case PCI_DEVICE_ID_CMD_646:
317 {
318 unsigned int class_rev = 0;
319 pci_read_config_dword(dev,
320 PCI_CLASS_REVISION, &class_rev);
321 class_rev &= 0xff;
322 /*
323 * UltraDMA only supported on PCI646U and PCI646U2, which
324 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
325 * Actually, although the CMD tech support people won't
326 * tell me the details, the 0x03 revision cannot support
327 * UDMA correctly without hardware modifications, and even
328 * then it only works with Quantum disks due to some
329 * hold time assumptions in the 646U part which are fixed
330 * in the 646U2.
331 *
332 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
333 */
334 switch(class_rev) {
335 case 0x07:
336 case 0x05:
337 return 1;
338 case 0x03:
339 case 0x01:
340 default:
341 return 0;
342 }
343 }
344 }
345 if (!eighty_ninty_three(drive))
346 mode = min(mode, (u8)1);
347 return mode;
348 }
349
350 static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
351 {
352 u8 speed = 0x00;
353 u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
354
355 cmd64x_tuneproc(drive, set_pio);
356 speed = XFER_PIO_0 + set_pio;
357 if (set_speed)
358 (void) ide_config_drive_speed(drive, speed);
359 }
360
361 static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
362 {
363 config_cmd64x_chipset_for_pio(drive, set_speed);
364 }
365
366 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
367 {
368 ide_hwif_t *hwif = HWIF(drive);
369 struct pci_dev *dev = hwif->pci_dev;
370
371 u8 unit = (drive->select.b.unit & 0x01);
372 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
373 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
374
375 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
376
377 if (speed > XFER_PIO_4) {
378 (void) pci_read_config_byte(dev, pciD, &regD);
379 (void) pci_read_config_byte(dev, pciU, &regU);
380 regD &= ~(unit ? 0x40 : 0x20);
381 regU &= ~(unit ? 0xCA : 0x35);
382 (void) pci_write_config_byte(dev, pciD, regD);
383 (void) pci_write_config_byte(dev, pciU, regU);
384 (void) pci_read_config_byte(dev, pciD, &regD);
385 (void) pci_read_config_byte(dev, pciU, &regU);
386 }
387
388 switch(speed) {
389 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
390 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
391 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
392 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
393 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
394 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
395 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
396 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
397 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
398 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
399 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
400 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
401 case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break;
402 case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break;
403 case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break;
404 case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break;
405 case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break;
406
407 default:
408 return 1;
409 }
410
411 if (speed > XFER_PIO_4) {
412 (void) pci_write_config_byte(dev, pciU, regU);
413 regD |= (unit ? 0x40 : 0x20);
414 (void) pci_write_config_byte(dev, pciD, regD);
415 }
416
417 return (ide_config_drive_speed(drive, speed));
418 }
419
420 static int config_chipset_for_dma (ide_drive_t *drive)
421 {
422 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
423
424 config_chipset_for_pio(drive, !speed);
425
426 if (!speed)
427 return 0;
428
429 if(ide_set_xfer_rate(drive, speed))
430 return 0;
431
432 if (!drive->init_speed)
433 drive->init_speed = speed;
434
435 return ide_dma_enable(drive);
436 }
437
438 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
439 {
440 ide_hwif_t *hwif = HWIF(drive);
441 struct hd_driveid *id = drive->id;
442
443 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
444 /* Consult the list of known "bad" drives */
445 if (__ide_dma_bad_drive(drive))
446 goto fast_ata_pio;
447 if ((id->field_valid & 4) && cmd64x_ratemask(drive)) {
448 if (id->dma_ultra & hwif->ultra_mask) {
449 /* Force if Capable UltraDMA */
450 int dma = config_chipset_for_dma(drive);
451 if ((id->field_valid & 2) && !dma)
452 goto try_dma_modes;
453 }
454 } else if (id->field_valid & 2) {
455 try_dma_modes:
456 if ((id->dma_mword & hwif->mwdma_mask) ||
457 (id->dma_1word & hwif->swdma_mask)) {
458 /* Force if Capable regular DMA modes */
459 if (!config_chipset_for_dma(drive))
460 goto no_dma_set;
461 }
462 } else if (__ide_dma_good_drive(drive) &&
463 (id->eide_dma_time < 150)) {
464 /* Consult the list of known "good" drives */
465 if (!config_chipset_for_dma(drive))
466 goto no_dma_set;
467 } else {
468 goto fast_ata_pio;
469 }
470 return hwif->ide_dma_on(drive);
471 } else if ((id->capability & 8) || (id->field_valid & 2)) {
472 fast_ata_pio:
473 no_dma_set:
474 config_chipset_for_pio(drive, 1);
475 return hwif->ide_dma_off_quietly(drive);
476 }
477 /* IORDY not supported */
478 return 0;
479 }
480
481 static int cmd64x_alt_dma_status (struct pci_dev *dev)
482 {
483 switch(dev->device) {
484 case PCI_DEVICE_ID_CMD_648:
485 case PCI_DEVICE_ID_CMD_649:
486 return 1;
487 default:
488 break;
489 }
490 return 0;
491 }
492
493 static int cmd64x_ide_dma_end (ide_drive_t *drive)
494 {
495 u8 dma_stat = 0, dma_cmd = 0;
496 ide_hwif_t *hwif = HWIF(drive);
497 struct pci_dev *dev = hwif->pci_dev;
498
499 drive->waiting_for_dma = 0;
500 /* read DMA command state */
501 dma_cmd = hwif->INB(hwif->dma_command);
502 /* stop DMA */
503 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
504 /* get DMA status */
505 dma_stat = hwif->INB(hwif->dma_status);
506 /* clear the INTR & ERROR bits */
507 hwif->OUTB(dma_stat|6, hwif->dma_status);
508 if (cmd64x_alt_dma_status(dev)) {
509 u8 dma_intr = 0;
510 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
511 CFR_INTR_CH0;
512 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
513 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
514 /* clear the INTR bit */
515 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
516 }
517 /* purge DMA mappings */
518 ide_destroy_dmatable(drive);
519 /* verify good DMA status */
520 return (dma_stat & 7) != 4;
521 }
522
523 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
524 {
525 ide_hwif_t *hwif = HWIF(drive);
526 struct pci_dev *dev = hwif->pci_dev;
527 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
528 MRDMODE_INTR_CH0;
529 u8 dma_stat = hwif->INB(hwif->dma_status);
530
531 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
532 #ifdef DEBUG
533 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
534 "0x%02x mask: 0x%02x\n", drive->name,
535 dma_stat, dma_alt_stat, mask);
536 #endif
537 if (!(dma_alt_stat & mask))
538 return 0;
539
540 /* return 1 if INTR asserted */
541 if ((dma_stat & 4) == 4)
542 return 1;
543
544 return 0;
545 }
546
547 /*
548 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
549 * event order for DMA transfers.
550 */
551
552 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
553 {
554 ide_hwif_t *hwif = HWIF(drive);
555 u8 dma_stat = 0, dma_cmd = 0;
556
557 drive->waiting_for_dma = 0;
558 /* get DMA status */
559 dma_stat = hwif->INB(hwif->dma_status);
560 /* read DMA command state */
561 dma_cmd = hwif->INB(hwif->dma_command);
562 /* stop DMA */
563 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
564 /* clear the INTR & ERROR bits */
565 hwif->OUTB(dma_stat|6, hwif->dma_status);
566 /* and free any DMA resources */
567 ide_destroy_dmatable(drive);
568 /* verify good DMA status */
569 return (dma_stat & 7) != 4;
570 }
571
572 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
573 {
574 u32 class_rev = 0;
575 u8 mrdmode = 0;
576
577 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
578 class_rev &= 0xff;
579
580 #ifdef __i386__
581 if (dev->resource[PCI_ROM_RESOURCE].start) {
582 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
583 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
584 }
585 #endif
586
587 switch(dev->device) {
588 case PCI_DEVICE_ID_CMD_643:
589 break;
590 case PCI_DEVICE_ID_CMD_646:
591 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
592 switch(class_rev) {
593 case 0x07:
594 case 0x05:
595 printk("UltraDMA Capable");
596 break;
597 case 0x03:
598 printk("MultiWord DMA Force Limited");
599 break;
600 case 0x01:
601 default:
602 printk("MultiWord DMA Limited, IRQ workaround enabled");
603 break;
604 }
605 printk("\n");
606 break;
607 case PCI_DEVICE_ID_CMD_648:
608 case PCI_DEVICE_ID_CMD_649:
609 break;
610 default:
611 break;
612 }
613
614 /* Set a good latency timer and cache line size value. */
615 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
616 /* FIXME: pci_set_master() to ensure a good latency timer value */
617
618 /* Setup interrupts. */
619 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
620 mrdmode &= ~(0x30);
621 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
622
623 /* Use MEMORY READ LINE for reads.
624 * NOTE: Although not mentioned in the PCI0646U specs,
625 * these bits are write only and won't be read
626 * back as set or not. The PCI0646U2 specs clarify
627 * this point.
628 */
629 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
630
631 /* Set reasonable active/recovery/address-setup values. */
632 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
633 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
634 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
635 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
636 #ifdef __i386__
637 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
638 #else
639 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
640 #endif
641 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
642 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
643 #ifdef CONFIG_PPC
644 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
645 #endif /* CONFIG_PPC */
646
647 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
648
649 cmd_devs[n_cmd_devs++] = dev;
650
651 if (!cmd64x_proc) {
652 cmd64x_proc = 1;
653 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
654 }
655 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
656
657 return 0;
658 }
659
660 static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
661 {
662 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
663
664 switch(hwif->pci_dev->device) {
665 case PCI_DEVICE_ID_CMD_643:
666 case PCI_DEVICE_ID_CMD_646:
667 return ata66;
668 default:
669 break;
670 }
671 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
672 return (ata66 & mask) ? 1 : 0;
673 }
674
675 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
676 {
677 struct pci_dev *dev = hwif->pci_dev;
678 unsigned int class_rev;
679
680 hwif->autodma = 0;
681 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
682 class_rev &= 0xff;
683
684 hwif->tuneproc = &cmd64x_tuneproc;
685 hwif->speedproc = &cmd64x_tune_chipset;
686
687 if (!hwif->dma_base) {
688 hwif->drives[0].autotune = 1;
689 hwif->drives[1].autotune = 1;
690 return;
691 }
692
693 hwif->atapi_dma = 1;
694
695 hwif->ultra_mask = 0x3f;
696 hwif->mwdma_mask = 0x07;
697 hwif->swdma_mask = 0x07;
698
699 if (dev->device == PCI_DEVICE_ID_CMD_643)
700 hwif->ultra_mask = 0x80;
701 if (dev->device == PCI_DEVICE_ID_CMD_646)
702 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
703 if (dev->device == PCI_DEVICE_ID_CMD_648)
704 hwif->ultra_mask = 0x1f;
705
706 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
707 if (!(hwif->udma_four))
708 hwif->udma_four = ata66_cmd64x(hwif);
709
710 if (dev->device == PCI_DEVICE_ID_CMD_646) {
711 hwif->chipset = ide_cmd646;
712 if (class_rev == 0x01) {
713 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
714 } else {
715 hwif->ide_dma_end = &cmd64x_ide_dma_end;
716 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
717 }
718 } else {
719 hwif->ide_dma_end = &cmd64x_ide_dma_end;
720 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
721 }
722
723
724 if (!noautodma)
725 hwif->autodma = 1;
726 hwif->drives[0].autodma = hwif->autodma;
727 hwif->drives[1].autodma = hwif->autodma;
728 }
729
730 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
731 {
732 ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
733 return 0;
734 }
735
736 static struct pci_device_id cmd64x_pci_tbl[] = {
737 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
738 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
739 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
740 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
741 { 0, },
742 };
743 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
744
745 static struct pci_driver driver = {
746 .name = "CMD64x_IDE",
747 .id_table = cmd64x_pci_tbl,
748 .probe = cmd64x_init_one,
749 };
750
751 static int cmd64x_ide_init(void)
752 {
753 return ide_pci_register_driver(&driver);
754 }
755
756 module_init(cmd64x_ide_init);
757
758 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
759 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
760 MODULE_LICENSE("GPL");
MOXA 2.6.9 from sdlinux-moxaart.tgz