2 * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
12 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 **********************************************************************
15 * 9/7/99 --Parts from the above author are included and need to be
16 * converted into standard interface, once I finish the thought.
19 * Don't use LBA48 mode on ALi <= 0xC4
20 * Don't poke 0x79 with a non ALi northbridge
21 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
22 * Allow UDMA6 on revisions > 0xC4
25 * Chipset documentation available under NDA only
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/kernel.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
41 #define DISPLAY_ALI_TIMINGS
44 * ALi devices are not plug in. Otherwise these static values would
45 * need to go. They ought to go away anyway
48 static u8 m5229_revision
;
49 static u8 chip_is_1543c_e
;
50 static struct pci_dev
*isa_dev
;
52 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
53 #include <linux/stat.h>
54 #include <linux/proc_fs.h>
56 static u8 ali_proc
= 0;
58 static struct pci_dev
*bmide_dev
;
60 static char *fifo
[4] = {
66 static char *udmaT
[8] = {
77 static char *channel_status
[8] = {
89 * ali_get_info - generate proc file for ALi IDE
90 * @buffer: buffer to fill
91 * @addr: address of user start in buffer
92 * @offset: offset into 'file'
93 * @count: buffer count
95 * Walks the Ali devices and outputs summary data on the tuning and
96 * anything else that will help with debugging
99 static int ali_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
102 u8 reg53h
, reg5xh
, reg5yh
, reg5xh1
, reg5yh1
, c0
, c1
, rev
, tmp
;
103 char *q
, *p
= buffer
;
106 pci_read_config_byte(bmide_dev
, 0x08, &rev
);
107 if (rev
>= 0xc1) /* M1543C or newer */
112 /* first fetch bibma: */
114 bibma
= pci_resource_start(bmide_dev
, 4);
117 * at that point bibma+0x2 et bibma+0xa are byte
118 * registers to investigate:
120 c0
= inb(bibma
+ 0x02);
121 c1
= inb(bibma
+ 0x0a);
124 "\n Ali M15x3 Chipset.\n");
126 " ------------------\n");
127 pci_read_config_byte(bmide_dev
, 0x78, ®53h
);
128 p
+= sprintf(p
, "PCI Clock: %d.\n", reg53h
);
130 pci_read_config_byte(bmide_dev
, 0x53, ®53h
);
132 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
133 (reg53h
& 0x02) ? "Yes" : "No ",
134 (reg53h
& 0x01) ? "Yes" : "No " );
135 pci_read_config_byte(bmide_dev
, 0x74, ®53h
);
137 "FIFO Status: contains %d Words, runs%s%s\n\n",
139 (reg53h
& 0x40) ? " OVERWR" : "",
140 (reg53h
& 0x80) ? " OVERRD." : "." );
143 "-------------------primary channel"
144 "-------------------secondary channel"
147 pci_read_config_byte(bmide_dev
, 0x09, ®53h
);
151 (reg53h
& 0x20) ? "On " : "Off",
152 (reg53h
& 0x10) ? "On " : "Off" );
155 "both channels togth: %s"
157 (c0
&0x80) ? "No " : "Yes",
158 (c1
&0x80) ? "No " : "Yes" );
160 pci_read_config_byte(bmide_dev
, 0x76, ®53h
);
162 "Channel state: %s %s\n",
163 channel_status
[reg53h
& 0x07],
164 channel_status
[(reg53h
& 0x70) >> 4] );
166 pci_read_config_byte(bmide_dev
, 0x58, ®5xh
);
167 pci_read_config_byte(bmide_dev
, 0x5c, ®5yh
);
169 "Add. Setup Timing: %dT"
171 (reg5xh
& 0x07) ? (reg5xh
& 0x07) : 8,
172 (reg5yh
& 0x07) ? (reg5yh
& 0x07) : 8 );
174 pci_read_config_byte(bmide_dev
, 0x59, ®5xh
);
175 pci_read_config_byte(bmide_dev
, 0x5d, ®5yh
);
177 "Command Act. Count: %dT"
179 "Command Rec. Count: %dT"
181 (reg5xh
& 0x70) ? ((reg5xh
& 0x70) >> 4) : 8,
182 (reg5yh
& 0x70) ? ((reg5yh
& 0x70) >> 4) : 8,
183 (reg5xh
& 0x0f) ? (reg5xh
& 0x0f) : 16,
184 (reg5yh
& 0x0f) ? (reg5yh
& 0x0f) : 16 );
187 "----------------drive0-----------drive1"
188 "------------drive0-----------drive1------\n\n");
192 (c0
&0x20) ? "Yes" : "No ",
193 (c0
&0x40) ? "Yes" : "No ",
194 (c1
&0x20) ? "Yes" : "No ",
195 (c1
&0x40) ? "Yes" : "No " );
197 pci_read_config_byte(bmide_dev
, 0x54, ®5xh
);
198 pci_read_config_byte(bmide_dev
, 0x55, ®5yh
);
199 q
= "FIFO threshold: %2d Words %2d Words"
200 " %2d Words %2d Words\n";
203 (pci_read_config_byte(bmide_dev
, 0x4f, &tmp
), (tmp
&= 0x20))) {
204 p
+= sprintf(p
, q
, 8, 8, 8, 8);
207 (reg5xh
& 0x03) + 12,
208 ((reg5xh
& 0x30)>>4) + 12,
209 (reg5yh
& 0x03) + 12,
210 ((reg5yh
& 0x30)>>4) + 12 );
213 int t1
= (tmp
= (reg5xh
& 0x03)) ? (tmp
<< 3) : 4;
214 int t2
= (tmp
= ((reg5xh
& 0x30)>>4)) ? (tmp
<< 3) : 4;
215 int t3
= (tmp
= (reg5yh
& 0x03)) ? (tmp
<< 3) : 4;
216 int t4
= (tmp
= ((reg5yh
& 0x30)>>4)) ? (tmp
<< 3) : 4;
217 p
+= sprintf(p
, q
, t1
, t2
, t3
, t4
);
222 "FIFO threshold: %2d Words %2d Words"
223 " %2d Words %2d Words\n",
224 (reg5xh
& 0x03) + 12,
225 ((reg5xh
& 0x30)>>4) + 12,
226 (reg5yh
& 0x03) + 12,
227 ((reg5yh
& 0x30)>>4) + 12 );
231 "FIFO mode: %s %s %s %s\n",
232 fifo
[((reg5xh
& 0x0c) >> 2)],
233 fifo
[((reg5xh
& 0xc0) >> 6)],
234 fifo
[((reg5yh
& 0x0c) >> 2)],
235 fifo
[((reg5yh
& 0xc0) >> 6)] );
237 pci_read_config_byte(bmide_dev
, 0x5a, ®5xh
);
238 pci_read_config_byte(bmide_dev
, 0x5b, ®5xh1
);
239 pci_read_config_byte(bmide_dev
, 0x5e, ®5yh
);
240 pci_read_config_byte(bmide_dev
, 0x5f, ®5yh1
);
243 "------------------drive0-----------drive1"
244 "------------drive0-----------drive1------\n")*/
245 "Dt RW act. Cnt %2dT %2dT"
247 "Dt RW rec. Cnt %2dT %2dT"
249 (reg5xh
& 0x70) ? ((reg5xh
& 0x70) >> 4) : 8,
250 (reg5xh1
& 0x70) ? ((reg5xh1
& 0x70) >> 4) : 8,
251 (reg5yh
& 0x70) ? ((reg5yh
& 0x70) >> 4) : 8,
252 (reg5yh1
& 0x70) ? ((reg5yh1
& 0x70) >> 4) : 8,
253 (reg5xh
& 0x0f) ? (reg5xh
& 0x0f) : 16,
254 (reg5xh1
& 0x0f) ? (reg5xh1
& 0x0f) : 16,
255 (reg5yh
& 0x0f) ? (reg5yh
& 0x0f) : 16,
256 (reg5yh1
& 0x0f) ? (reg5yh1
& 0x0f) : 16 );
259 "-----------------------------------UDMA Timings"
260 "--------------------------------\n\n");
262 pci_read_config_byte(bmide_dev
, 0x56, ®5xh
);
263 pci_read_config_byte(bmide_dev
, 0x57, ®5yh
);
267 "UDMA timings: %s %s"
269 (reg5xh
& 0x08) ? "OK" : "No",
270 (reg5xh
& 0x80) ? "OK" : "No",
271 (reg5yh
& 0x08) ? "OK" : "No",
272 (reg5yh
& 0x80) ? "OK" : "No",
273 udmaT
[(reg5xh
& 0x07)],
274 udmaT
[(reg5xh
& 0x70) >> 4],
275 udmaT
[reg5yh
& 0x07],
276 udmaT
[(reg5yh
& 0x70) >> 4] );
278 return p
-buffer
; /* => must be less than 4k! */
280 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
283 * ali15x3_tune_drive - set up a drive
284 * @drive: drive to tune
287 * Select the best PIO timing for the drive in question. Then
288 * program the controller for this drive set up
291 static void ali15x3_tune_drive (ide_drive_t
*drive
, u8 pio
)
294 ide_hwif_t
*hwif
= HWIF(drive
);
295 struct pci_dev
*dev
= hwif
->pci_dev
;
296 int s_time
, a_time
, c_time
;
297 u8 s_clc
, a_clc
, r_clc
;
299 int bus_speed
= system_bus_clock();
300 int port
= hwif
->channel
? 0x5c : 0x58;
301 int portFIFO
= hwif
->channel
? 0x55 : 0x54;
303 int unit
= drive
->select
.b
.unit
& 1;
305 pio
= ide_get_best_pio_mode(drive
, pio
, 5, &d
);
306 s_time
= ide_pio_timings
[pio
].setup_time
;
307 a_time
= ide_pio_timings
[pio
].active_time
;
308 if ((s_clc
= (s_time
* bus_speed
+ 999) / 1000) >= 8)
310 if ((a_clc
= (a_time
* bus_speed
+ 999) / 1000) >= 8)
312 c_time
= ide_pio_timings
[pio
].cycle_time
;
315 if ((r_clc
= ((c_time
- s_time
- a_time
) * bus_speed
+ 999) / 1000) >= 16)
319 if (!(r_clc
= (c_time
* bus_speed
+ 999) / 1000 - a_clc
- s_clc
)) {
325 local_irq_save(flags
);
328 * PIO mode => ATA FIFO on, ATAPI FIFO off
330 pci_read_config_byte(dev
, portFIFO
, &cd_dma_fifo
);
331 if (drive
->media
==ide_disk
) {
333 pci_write_config_byte(dev
, portFIFO
, (cd_dma_fifo
& 0x0F) | 0x50);
335 pci_write_config_byte(dev
, portFIFO
, (cd_dma_fifo
& 0xF0) | 0x05);
339 pci_write_config_byte(dev
, portFIFO
, cd_dma_fifo
& 0x0F);
341 pci_write_config_byte(dev
, portFIFO
, cd_dma_fifo
& 0xF0);
345 pci_write_config_byte(dev
, port
, s_clc
);
346 pci_write_config_byte(dev
, port
+drive
->select
.b
.unit
+2, (a_clc
<< 4) | r_clc
);
347 local_irq_restore(flags
);
351 * { 70, 165, 365 }, PIO Mode 0
352 * { 50, 125, 208 }, PIO Mode 1
353 * { 30, 100, 110 }, PIO Mode 2
354 * { 30, 80, 70 }, PIO Mode 3 with IORDY
355 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
356 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
362 * ali15x3_can_ultra - check for ultra DMA support
363 * @drive: drive to do the check
365 * Check the drive and controller revisions. Return 0 if UDMA is
366 * not available, or 1 if UDMA can be used. The actual rules for
368 * No UDMA on revisions <= 0x20
369 * Disk only for revisions < 0xC2
370 * Not WDC drives for revisions < 0xC2
372 * FIXME: WDC ifdef needs to die
375 static u8
ali15x3_can_ultra (ide_drive_t
*drive
)
377 #ifndef CONFIG_WDC_ALI15X3
378 struct hd_driveid
*id
= drive
->id
;
379 #endif /* CONFIG_WDC_ALI15X3 */
381 if (m5229_revision
<= 0x20) {
383 } else if ((m5229_revision
< 0xC2) &&
384 #ifndef CONFIG_WDC_ALI15X3
385 ((chip_is_1543c_e
&& strstr(id
->model
, "WDC ")) ||
386 (drive
->media
!=ide_disk
))) {
387 #else /* CONFIG_WDC_ALI15X3 */
388 (drive
->media
!=ide_disk
)) {
389 #endif /* CONFIG_WDC_ALI15X3 */
397 * ali15x3_ratemask - generate DMA mode list
398 * @drive: drive to compute against
400 * Generate a list of the available DMA modes for the drive.
401 * FIXME: this function contains lots of bogus masking we can dump
403 * Return the highest available mode (UDMA33, UDMA66, UDMA100,..)
406 static u8
ali15x3_ratemask (ide_drive_t
*drive
)
408 u8 mode
= 0, can_ultra
= ali15x3_can_ultra(drive
);
410 if (m5229_revision
> 0xC4 && can_ultra
) {
412 } else if (m5229_revision
== 0xC4 && can_ultra
) {
414 } else if (m5229_revision
>= 0xC2 && can_ultra
) {
416 } else if (can_ultra
) {
423 * If the drive sees no suitable cable then UDMA 33
424 * is the highest permitted mode
427 if (!eighty_ninty_three(drive
))
428 mode
= min(mode
, (u8
)1);
433 * ali15x3_tune_chipset - set up chiset for new speed
434 * @drive: drive to configure for
435 * @xferspeed: desired speed
437 * Configure the hardware for the desired IDE transfer mode.
438 * We also do the needed drive configuration through helpers
441 static int ali15x3_tune_chipset (ide_drive_t
*drive
, u8 xferspeed
)
443 ide_hwif_t
*hwif
= HWIF(drive
);
444 struct pci_dev
*dev
= hwif
->pci_dev
;
445 u8 speed
= ide_rate_filter(ali15x3_ratemask(drive
), xferspeed
);
447 u8 unit
= (drive
->select
.b
.unit
& 0x01);
449 int m5229_udma
= (hwif
->channel
) ? 0x57 : 0x56;
451 if (speed
== XFER_UDMA_6
)
454 if (speed
< XFER_UDMA_0
) {
455 u8 ultra_enable
= (unit
) ? 0x7f : 0xf7;
457 * clear "ultra enable" bit
459 pci_read_config_byte(dev
, m5229_udma
, &tmpbyte
);
460 tmpbyte
&= ultra_enable
;
461 pci_write_config_byte(dev
, m5229_udma
, tmpbyte
);
463 if (speed
< XFER_SW_DMA_0
)
464 ali15x3_tune_drive(drive
, speed
);
466 pci_read_config_byte(dev
, m5229_udma
, &tmpbyte
);
467 tmpbyte
&= (0x0f << ((1-unit
) << 2));
469 * enable ultra dma and set timing
471 tmpbyte
|= ((0x08 | ((4-speed1
)&0x07)) << (unit
<< 2));
472 pci_write_config_byte(dev
, m5229_udma
, tmpbyte
);
473 if (speed
>= XFER_UDMA_3
) {
474 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
476 pci_write_config_byte(dev
, 0x4b, tmpbyte
);
479 return (ide_config_drive_speed(drive
, speed
));
484 * config_chipset_for_dma - set up DMA mode
485 * @drive: drive to configure for
487 * Place a drive into DMA mode and tune the chipset for
488 * the selected speed.
490 * Returns true if DMA mode can be used
493 static int config_chipset_for_dma (ide_drive_t
*drive
)
495 u8 speed
= ide_dma_speed(drive
, ali15x3_ratemask(drive
));
500 (void) ali15x3_tune_chipset(drive
, speed
);
501 return ide_dma_enable(drive
);
505 * ali15x3_config_drive_for_dma - configure for DMA
506 * @drive: drive to configure
508 * Configure a drive for DMA operation. If DMA is not possible we
509 * drop the drive into PIO mode instead.
511 * FIXME: exactly what are we trying to return here
514 static int ali15x3_config_drive_for_dma(ide_drive_t
*drive
)
516 ide_hwif_t
*hwif
= HWIF(drive
);
517 struct hd_driveid
*id
= drive
->id
;
519 if ((m5229_revision
<=0x20) && (drive
->media
!=ide_disk
))
520 return hwif
->ide_dma_off_quietly(drive
);
522 drive
->init_speed
= 0;
524 if ((id
!= NULL
) && ((id
->capability
& 1) != 0) && drive
->autodma
) {
525 /* Consult the list of known "bad" drives */
526 if (__ide_dma_bad_drive(drive
))
528 if ((id
->field_valid
& 4) && (m5229_revision
>= 0xC2)) {
529 if (id
->dma_ultra
& hwif
->ultra_mask
) {
530 /* Force if Capable UltraDMA */
531 int dma
= config_chipset_for_dma(drive
);
532 if ((id
->field_valid
& 2) && !dma
)
535 } else if (id
->field_valid
& 2) {
537 if ((id
->dma_mword
& hwif
->mwdma_mask
) ||
538 (id
->dma_1word
& hwif
->swdma_mask
)) {
539 /* Force if Capable regular DMA modes */
540 if (!config_chipset_for_dma(drive
))
543 } else if (__ide_dma_good_drive(drive
) &&
544 (id
->eide_dma_time
< 150)) {
545 /* Consult the list of known "good" drives */
546 if (!config_chipset_for_dma(drive
))
553 hwif
->tuneproc(drive
, 255);
555 return hwif
->ide_dma_off_quietly(drive
);
557 return hwif
->ide_dma_on(drive
);
561 * ali15x3_dma_write - do a DMA IDE write
562 * @drive: drive to issue write for
564 * Returns 1 if the DMA write cannot be performed, zero on
568 static int ali15x3_dma_write (ide_drive_t
*drive
)
570 if ((m5229_revision
< 0xC2) && (drive
->media
!= ide_disk
))
571 return 1; /* try PIO instead of DMA */
572 return __ide_dma_write(drive
);
576 * init_chipset_ali15x3 - Initialise an ALi IDE controller
578 * @name: Name of the controller
580 * This function initializes the ALI IDE controller and where
581 * appropriate also sets up the 1533 southbridge.
584 static unsigned int __init
init_chipset_ali15x3 (struct pci_dev
*dev
, const char *name
)
588 struct pci_dev
*north
= pci_find_slot(0, PCI_DEVFN(0,0));
590 pci_read_config_byte(dev
, PCI_REVISION_ID
, &m5229_revision
);
592 isa_dev
= pci_find_device(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, NULL
);
594 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
598 ide_pci_create_host_proc("ali", ali_get_info
);
600 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
602 local_irq_save(flags
);
604 if (m5229_revision
< 0xC2) {
606 * revision 0x20 (1543-E, 1543-F)
607 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
608 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
610 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
614 pci_write_config_byte(dev
, 0x4b, tmpbyte
& 0x7F);
615 local_irq_restore(flags
);
620 * 1543C-B?, 1535, 1535D, 1553
621 * Note 1: not all "motherboard" support this detection
622 * Note 2: if no udma 66 device, the detection may "error".
623 * but in this case, we will not set the device to
624 * ultra 66, the detection result is not important
628 * enable "Cable Detection", m5229, 0x4b, bit3
630 pci_read_config_byte(dev
, 0x4b, &tmpbyte
);
631 pci_write_config_byte(dev
, 0x4b, tmpbyte
| 0x08);
634 * We should only tune the 1533 enable if we are using an ALi
635 * North bridge. We might have no north found on some zany
636 * box without a device at 0:0.0. The ALi bridge will be at
637 * 0:0.0 so if we didn't find one we know what is cooking.
639 if (north
&& north
->vendor
!= PCI_VENDOR_ID_AL
) {
640 local_irq_restore(flags
);
644 if (m5229_revision
< 0xC5 && isa_dev
)
647 * set south-bridge's enable bit, m1533, 0x79
650 pci_read_config_byte(isa_dev
, 0x79, &tmpbyte
);
651 if (m5229_revision
== 0xC2) {
653 * 1543C-B0 (m1533, 0x79, bit 2)
655 pci_write_config_byte(isa_dev
, 0x79, tmpbyte
| 0x04);
656 } else if (m5229_revision
>= 0xC3) {
658 * 1553/1535 (m1533, 0x79, bit 1)
660 pci_write_config_byte(isa_dev
, 0x79, tmpbyte
| 0x02);
663 local_irq_restore(flags
);
668 * ata66_ali15x3 - check for UDMA 66 support
669 * @hwif: IDE interface
671 * This checks if the controller and the cable are capable
672 * of UDMA66 transfers. It doesn't check the drives.
673 * But see note 2 below!
675 * FIXME: frobs bits that are not defined on newer ALi devicea
678 static unsigned int __init
ata66_ali15x3 (ide_hwif_t
*hwif
)
680 struct pci_dev
*dev
= hwif
->pci_dev
;
681 unsigned int ata66
= 0;
682 u8 cable_80_pin
[2] = { 0, 0 };
687 local_irq_save(flags
);
689 if (m5229_revision
>= 0xC2) {
691 * Ultra66 cable detection (from Host View)
692 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
694 pci_read_config_byte(dev
, 0x4a, &tmpbyte
);
696 * 0x4a, bit0 is 0 => primary channel
697 * has 80-pin (from host view)
699 if (!(tmpbyte
& 0x01)) cable_80_pin
[0] = 1;
701 * 0x4a, bit1 is 0 => secondary channel
702 * has 80-pin (from host view)
704 if (!(tmpbyte
& 0x02)) cable_80_pin
[1] = 1;
706 * Allow ata66 if cable of current channel has 80 pins
708 ata66
= (hwif
->channel
)?cable_80_pin
[1]:cable_80_pin
[0];
711 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
713 pci_read_config_byte(isa_dev
, 0x5e, &tmpbyte
);
714 chip_is_1543c_e
= ((tmpbyte
& 0x1e) == 0x12) ? 1: 0;
718 * CD_ROM DMA on (m5229, 0x53, bit0)
719 * Enable this bit even if we want to use PIO
720 * PIO FIFO off (m5229, 0x53, bit1)
721 * The hardware will use 0x54h and 0x55h to control PIO FIFO
722 * (Not on later devices it seems)
724 * 0x53 changes meaning on later revs - we must no touch
725 * bit 1 on them. Need to check if 0x20 is the right break
728 pci_read_config_byte(dev
, 0x53, &tmpbyte
);
730 if(m5229_revision
<= 0x20)
731 tmpbyte
= (tmpbyte
& (~0x02)) | 0x01;
735 pci_write_config_byte(dev
, 0x53, tmpbyte
);
737 local_irq_restore(flags
);
743 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
744 * @hwif: IDE interface
746 * Initialize the IDE structure side of the ALi 15x3 driver.
749 static void __init
init_hwif_common_ali15x3 (ide_hwif_t
*hwif
)
752 hwif
->tuneproc
= &ali15x3_tune_drive
;
753 hwif
->speedproc
= &ali15x3_tune_chipset
;
755 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
756 hwif
->no_lba48_dma
= (m5229_revision
<= 0xC4) ? 1 : 0;
758 if (!hwif
->dma_base
) {
759 hwif
->drives
[0].autotune
= 1;
760 hwif
->drives
[1].autotune
= 1;
766 if (m5229_revision
> 0x20)
767 hwif
->ultra_mask
= 0x7f;
768 hwif
->mwdma_mask
= 0x07;
769 hwif
->swdma_mask
= 0x07;
771 if (m5229_revision
>= 0x20) {
773 * M1543C or newer for DMAing
775 hwif
->ide_dma_check
= &ali15x3_config_drive_for_dma
;
776 hwif
->ide_dma_write
= &ali15x3_dma_write
;
779 if (!(hwif
->udma_four
))
780 hwif
->udma_four
= ata66_ali15x3(hwif
);
782 hwif
->drives
[0].autodma
= hwif
->autodma
;
783 hwif
->drives
[1].autodma
= hwif
->autodma
;
787 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
788 * @hwif: interface to configure
790 * Obtain the IRQ tables for an ALi based IDE solution on the PC
791 * class platforms. This part of the code isn't applicable to the
795 static void __init
init_hwif_ali15x3 (ide_hwif_t
*hwif
)
798 s8 irq_routing_table
[] = { -1, 9, 3, 10, 4, 5, 7, 6,
799 1, 11, 0, 12, 0, 14, 0, 15 };
802 hwif
->irq
= hwif
->channel
? 15 : 14;
806 * read IDE interface control
808 pci_read_config_byte(isa_dev
, 0x58, &ideic
);
811 ideic
= ideic
& 0x03;
813 /* get IRQ for IDE Controller */
814 if ((hwif
->channel
&& ideic
== 0x03) ||
815 (!hwif
->channel
&& !ideic
)) {
817 * get SIRQ1 routing table
819 pci_read_config_byte(isa_dev
, 0x44, &inmir
);
820 inmir
= inmir
& 0x0f;
821 irq
= irq_routing_table
[inmir
];
822 } else if (hwif
->channel
&& !(ideic
& 0x01)) {
824 * get SIRQ2 routing table
826 pci_read_config_byte(isa_dev
, 0x75, &inmir
);
827 inmir
= inmir
& 0x0f;
828 irq
= irq_routing_table
[inmir
];
834 init_hwif_common_ali15x3(hwif
);
838 * init_dma_ali15x3 - set up DMA on ALi15x3
839 * @hwif: IDE interface
840 * @dmabase: DMA interface base PCI address
842 * Set up the DMA functionality on the ALi 15x3. For the ALi
843 * controllers this is generic so we can let the generic code do
847 static void __init
init_dma_ali15x3 (ide_hwif_t
*hwif
, unsigned long dmabase
)
849 if (m5229_revision
< 0x20)
851 if (!(hwif
->channel
))
852 hwif
->OUTB(hwif
->INB(dmabase
+2) & 0x60, dmabase
+2);
853 ide_setup_dma(hwif
, dmabase
, 8);
856 static ide_pci_device_t ali15x3_chipset __devinitdata
= {
858 .init_chipset
= init_chipset_ali15x3
,
859 .init_hwif
= init_hwif_ali15x3
,
860 .init_dma
= init_dma_ali15x3
,
863 .bootable
= ON_BOARD
,
867 * alim15x3_init_one - set up an ALi15x3 IDE controller
868 * @dev: PCI device to set up
870 * Perform the actual set up for an ALi15x3 that has been found by the
874 static int __devinit
alim15x3_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
876 ide_pci_device_t
*d
= &ali15x3_chipset
;
878 if(pci_find_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, NULL
))
879 printk(KERN_ERR
"Warning: ATI Radeon IGP Northbridge is not yet fully tested.\n");
881 #if defined(CONFIG_SPARC64)
882 d
->init_hwif
= init_hwif_common_ali15x3
;
883 #endif /* CONFIG_SPARC64 */
884 ide_setup_pci_device(dev
, d
);
889 static struct pci_device_id alim15x3_pci_tbl
[] = {
890 { PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M5229
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
893 MODULE_DEVICE_TABLE(pci
, alim15x3_pci_tbl
);
895 static struct pci_driver driver
= {
896 .name
= "ALI15x3_IDE",
897 .id_table
= alim15x3_pci_tbl
,
898 .probe
= alim15x3_init_one
,
901 static int ali15x3_ide_init(void)
903 return ide_pci_register_driver(&driver
);
906 module_init(ali15x3_ide_init
);
908 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
909 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
910 MODULE_LICENSE("GPL");