drivers/char/drm/radeon_drm.h

   1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  */
  32
  33 #ifndef __RADEON_DRM_H__
  34 #define __RADEON_DRM_H__
  35
  36 /* WARNING: If you change any of these defines, make sure to change the
  37  * defines in the X server file (radeon_sarea.h)
  38  */
  39 #ifndef __RADEON_SAREA_DEFINES__
  40 #define __RADEON_SAREA_DEFINES__
  41
  42 /* Old style state flags, required for sarea interface (1.1 and 1.2
  43  * clears) and 1.2 drm_vertex2 ioctl.
  44  */
  45 #define RADEON_UPLOAD_CONTEXT           0x00000001
  46 #define RADEON_UPLOAD_VERTFMT           0x00000002
  47 #define RADEON_UPLOAD_LINE              0x00000004
  48 #define RADEON_UPLOAD_BUMPMAP           0x00000008
  49 #define RADEON_UPLOAD_MASKS             0x00000010
  50 #define RADEON_UPLOAD_VIEWPORT          0x00000020
  51 #define RADEON_UPLOAD_SETUP             0x00000040
  52 #define RADEON_UPLOAD_TCL               0x00000080
  53 #define RADEON_UPLOAD_MISC              0x00000100
  54 #define RADEON_UPLOAD_TEX0              0x00000200
  55 #define RADEON_UPLOAD_TEX1              0x00000400
  56 #define RADEON_UPLOAD_TEX2              0x00000800
  57 #define RADEON_UPLOAD_TEX0IMAGES        0x00001000
  58 #define RADEON_UPLOAD_TEX1IMAGES        0x00002000
  59 #define RADEON_UPLOAD_TEX2IMAGES        0x00004000
  60 #define RADEON_UPLOAD_CLIPRECTS         0x00008000 /* handled client-side */
  61 #define RADEON_REQUIRE_QUIESCENCE       0x00010000
  62 #define RADEON_UPLOAD_ZBIAS             0x00020000 /* version 1.2 and newer */
  63 #define RADEON_UPLOAD_ALL               0x003effff
  64 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
  65
  66
  67 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  68  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  69  * state bits and the packet size:
  70  */
  71 #define RADEON_EMIT_PP_MISC                         0 /* context/7 */
  72 #define RADEON_EMIT_PP_CNTL                         1 /* context/3 */
  73 #define RADEON_EMIT_RB3D_COLORPITCH                 2 /* context/1 */
  74 #define RADEON_EMIT_RE_LINE_PATTERN                 3 /* line/2 */
  75 #define RADEON_EMIT_SE_LINE_WIDTH                   4 /* line/1 */
  76 #define RADEON_EMIT_PP_LUM_MATRIX                   5 /* bumpmap/1 */
  77 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6 /* bumpmap/2 */
  78 #define RADEON_EMIT_RB3D_STENCILREFMASK             7 /* masks/3 */
  79 #define RADEON_EMIT_SE_VPORT_XSCALE                 8 /* viewport/6 */
  80 #define RADEON_EMIT_SE_CNTL                         9 /* setup/2 */
  81 #define RADEON_EMIT_SE_CNTL_STATUS                  10 /* setup/1 */
  82 #define RADEON_EMIT_RE_MISC                         11 /* misc/1 */
  83 #define RADEON_EMIT_PP_TXFILTER_0                   12 /* tex0/6 */
  84 #define RADEON_EMIT_PP_BORDER_COLOR_0               13 /* tex0/1 */
  85 #define RADEON_EMIT_PP_TXFILTER_1                   14 /* tex1/6 */
  86 #define RADEON_EMIT_PP_BORDER_COLOR_1               15 /* tex1/1 */
  87 #define RADEON_EMIT_PP_TXFILTER_2                   16 /* tex2/6 */
  88 #define RADEON_EMIT_PP_BORDER_COLOR_2               17 /* tex2/1 */
  89 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18 /* zbias/2 */
  90 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19 /* tcl/11 */
  91 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
  92 #define R200_EMIT_PP_TXCBLEND_0                     21 /* tex0/4 */
  93 #define R200_EMIT_PP_TXCBLEND_1                     22 /* tex1/4 */
  94 #define R200_EMIT_PP_TXCBLEND_2                     23 /* tex2/4 */
  95 #define R200_EMIT_PP_TXCBLEND_3                     24 /* tex3/4 */
  96 #define R200_EMIT_PP_TXCBLEND_4                     25 /* tex4/4 */
  97 #define R200_EMIT_PP_TXCBLEND_5                     26 /* tex5/4 */
  98 #define R200_EMIT_PP_TXCBLEND_6                     27 /* /4 */
  99 #define R200_EMIT_PP_TXCBLEND_7                     28 /* /4 */
 100 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29 /* tcl/7 */
 101 #define R200_EMIT_TFACTOR_0                         30 /* tf/7 */
 102 #define R200_EMIT_VTX_FMT_0                         31 /* vtx/5 */
 103 #define R200_EMIT_VAP_CTL                           32 /* vap/1 */
 104 #define R200_EMIT_MATRIX_SELECT_0                   33 /* msl/5 */
 105 #define R200_EMIT_TEX_PROC_CTL_2                    34 /* tcg/5 */
 106 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35 /* tcl/1 */
 107 #define R200_EMIT_PP_TXFILTER_0                     36 /* tex0/6 */
 108 #define R200_EMIT_PP_TXFILTER_1                     37 /* tex1/6 */
 109 #define R200_EMIT_PP_TXFILTER_2                     38 /* tex2/6 */
 110 #define R200_EMIT_PP_TXFILTER_3                     39 /* tex3/6 */
 111 #define R200_EMIT_PP_TXFILTER_4                     40 /* tex4/6 */
 112 #define R200_EMIT_PP_TXFILTER_5                     41 /* tex5/6 */
 113 #define R200_EMIT_PP_TXOFFSET_0                     42 /* tex0/1 */
 114 #define R200_EMIT_PP_TXOFFSET_1                     43 /* tex1/1 */
 115 #define R200_EMIT_PP_TXOFFSET_2                     44 /* tex2/1 */
 116 #define R200_EMIT_PP_TXOFFSET_3                     45 /* tex3/1 */
 117 #define R200_EMIT_PP_TXOFFSET_4                     46 /* tex4/1 */
 118 #define R200_EMIT_PP_TXOFFSET_5                     47 /* tex5/1 */
 119 #define R200_EMIT_VTE_CNTL                          48 /* vte/1 */
 120 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49 /* vtx/1 */
 121 #define R200_EMIT_PP_TAM_DEBUG3                     50 /* tam/1 */
 122 #define R200_EMIT_PP_CNTL_X                         51 /* cst/1 */
 123 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52 /* cst/1 */
 124 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53 /* cst/1 */
 125 #define R200_EMIT_RE_SCISSOR_TL_0                   54 /* cst/2 */
 126 #define R200_EMIT_RE_SCISSOR_TL_1                   55 /* cst/2 */
 127 #define R200_EMIT_RE_SCISSOR_TL_2                   56 /* cst/2 */
 128 #define R200_EMIT_SE_VAP_CNTL_STATUS                57 /* cst/1 */
 129 #define R200_EMIT_SE_VTX_STATE_CNTL                 58 /* cst/1 */
 130 #define R200_EMIT_RE_POINTSIZE                      59 /* cst/1 */
 131 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60 /* cst/4 */
 132 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 133 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 134 #define R200_EMIT_PP_CUBIC_FACES_1                  63
 135 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
 136 #define R200_EMIT_PP_CUBIC_FACES_2                  65
 137 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
 138 #define R200_EMIT_PP_CUBIC_FACES_3                  67
 139 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
 140 #define R200_EMIT_PP_CUBIC_FACES_4                  69
 141 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 142 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 143 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
 144 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 145 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 146 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
 147 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 148 #define RADEON_MAX_STATE_PACKETS                    77
 149
 150
 151 /* Commands understood by cmd_buffer ioctl.  More can be added but
 152  * obviously these can't be removed or changed:
 153  */
 154 #define RADEON_CMD_PACKET      1 /* emit one of the register packets above */
 155 #define RADEON_CMD_SCALARS     2 /* emit scalar data */
 156 #define RADEON_CMD_VECTORS     3 /* emit vector data */
 157 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
 158 #define RADEON_CMD_PACKET3     5 /* emit hw packet */
 159 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
 160 #define RADEON_CMD_SCALARS2     7 /* r200 stopgap */
 161 #define RADEON_CMD_WAIT         8 /* emit hw wait commands -- note:
 162                                    *  doesn't make the cpu wait, just
 163                                    *  the graphics hardware */
 164
 165
 166 typedef union {
 167         int i;
 168         struct {
 169                 unsigned char cmd_type, pad0, pad1, pad2;
 170         } header;
 171         struct {
 172                 unsigned char cmd_type, packet_id, pad0, pad1;
 173         } packet;
 174         struct {
 175                 unsigned char cmd_type, offset, stride, count;
 176         } scalars;
 177         struct {
 178                 unsigned char cmd_type, offset, stride, count;
 179         } vectors;
 180         struct {
 181                 unsigned char cmd_type, buf_idx, pad0, pad1;
 182         } dma;
 183         struct {
 184                 unsigned char cmd_type, flags, pad0, pad1;
 185         } wait;
 186 } drm_radeon_cmd_header_t;
 187
 188 #define RADEON_WAIT_2D  0x1
 189 #define RADEON_WAIT_3D  0x2
 190
 191
 192 #define RADEON_FRONT                    0x1
 193 #define RADEON_BACK                     0x2
 194 #define RADEON_DEPTH                    0x4
 195 #define RADEON_STENCIL                  0x8
 196
 197 /* Primitive types
 198  */
 199 #define RADEON_POINTS                   0x1
 200 #define RADEON_LINES                    0x2
 201 #define RADEON_LINE_STRIP               0x3
 202 #define RADEON_TRIANGLES                0x4
 203 #define RADEON_TRIANGLE_FAN             0x5
 204 #define RADEON_TRIANGLE_STRIP           0x6
 205
 206 /* Vertex/indirect buffer size
 207  */
 208 #define RADEON_BUFFER_SIZE              65536
 209
 210 /* Byte offsets for indirect buffer data
 211  */
 212 #define RADEON_INDEX_PRIM_OFFSET        20
 213
 214 #define RADEON_SCRATCH_REG_OFFSET       32
 215
 216 #define RADEON_NR_SAREA_CLIPRECTS       12
 217
 218 /* There are 2 heaps (local/GART).  Each region within a heap is a
 219  * minimum of 64k, and there are at most 64 of them per heap.
 220  */
 221 #define RADEON_LOCAL_TEX_HEAP           0
 222 #define RADEON_GART_TEX_HEAP            1
 223 #define RADEON_NR_TEX_HEAPS             2
 224 #define RADEON_NR_TEX_REGIONS           64
 225 #define RADEON_LOG_TEX_GRANULARITY      16
 226
 227 #define RADEON_MAX_TEXTURE_LEVELS       12
 228 #define RADEON_MAX_TEXTURE_UNITS        3
 229
 230 /* Blits have strict offset rules.  All blit offset must be aligned on
 231  * a 1K-byte boundary.
 232  */
 233 #define RADEON_OFFSET_SHIFT             10
 234 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 235 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 236
 237 #endif /* __RADEON_SAREA_DEFINES__ */
 238
 239 typedef struct {
 240         unsigned int red;
 241         unsigned int green;
 242         unsigned int blue;
 243         unsigned int alpha;
 244 } radeon_color_regs_t;
 245
 246 typedef struct {
 247         /* Context state */
 248         unsigned int pp_misc;                           /* 0x1c14 */
 249         unsigned int pp_fog_color;
 250         unsigned int re_solid_color;
 251         unsigned int rb3d_blendcntl;
 252         unsigned int rb3d_depthoffset;
 253         unsigned int rb3d_depthpitch;
 254         unsigned int rb3d_zstencilcntl;
 255
 256         unsigned int pp_cntl;                           /* 0x1c38 */
 257         unsigned int rb3d_cntl;
 258         unsigned int rb3d_coloroffset;
 259         unsigned int re_width_height;
 260         unsigned int rb3d_colorpitch;
 261         unsigned int se_cntl;
 262
 263         /* Vertex format state */
 264         unsigned int se_coord_fmt;                      /* 0x1c50 */
 265
 266         /* Line state */
 267         unsigned int re_line_pattern;                   /* 0x1cd0 */
 268         unsigned int re_line_state;
 269
 270         unsigned int se_line_width;                     /* 0x1db8 */
 271
 272         /* Bumpmap state */
 273         unsigned int pp_lum_matrix;                     /* 0x1d00 */
 274
 275         unsigned int pp_rot_matrix_0;                   /* 0x1d58 */
 276         unsigned int pp_rot_matrix_1;
 277
 278         /* Mask state */
 279         unsigned int rb3d_stencilrefmask;               /* 0x1d7c */
 280         unsigned int rb3d_ropcntl;
 281         unsigned int rb3d_planemask;
 282
 283         /* Viewport state */
 284         unsigned int se_vport_xscale;                   /* 0x1d98 */
 285         unsigned int se_vport_xoffset;
 286         unsigned int se_vport_yscale;
 287         unsigned int se_vport_yoffset;
 288         unsigned int se_vport_zscale;
 289         unsigned int se_vport_zoffset;
 290
 291         /* Setup state */
 292         unsigned int se_cntl_status;                    /* 0x2140 */
 293
 294         /* Misc state */
 295         unsigned int re_top_left;                       /* 0x26c0 */
 296         unsigned int re_misc;
 297 } drm_radeon_context_regs_t;
 298
 299 typedef struct {
 300         /* Zbias state */
 301         unsigned int se_zbias_factor;                   /* 0x1dac */
 302         unsigned int se_zbias_constant;
 303 } drm_radeon_context2_regs_t;
 304
 305
 306 /* Setup registers for each texture unit
 307  */
 308 typedef struct {
 309         unsigned int pp_txfilter;
 310         unsigned int pp_txformat;
 311         unsigned int pp_txoffset;
 312         unsigned int pp_txcblend;
 313         unsigned int pp_txablend;
 314         unsigned int pp_tfactor;
 315         unsigned int pp_border_color;
 316 } drm_radeon_texture_regs_t;
 317
 318 typedef struct {
 319         unsigned int start;
 320         unsigned int finish;
 321         unsigned int prim:8;
 322         unsigned int stateidx:8;
 323         unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
 324         unsigned int vc_format;   /* vertex format */
 325 } drm_radeon_prim_t;
 326
 327
 328 typedef struct {
 329         drm_radeon_context_regs_t context;
 330         drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
 331         drm_radeon_context2_regs_t context2;
 332         unsigned int dirty;
 333 } drm_radeon_state_t;
 334
 335
 336 typedef struct {
 337         /* The channel for communication of state information to the
 338          * kernel on firing a vertex buffer with either of the
 339          * obsoleted vertex/index ioctls.
 340          */
 341         drm_radeon_context_regs_t context_state;
 342         drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 343         unsigned int dirty;
 344         unsigned int vertsize;
 345         unsigned int vc_format;
 346
 347         /* The current cliprects, or a subset thereof.
 348          */
 349         drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
 350         unsigned int nbox;
 351
 352         /* Counters for client-side throttling of rendering clients.
 353          */
 354         unsigned int last_frame;
 355         unsigned int last_dispatch;
 356         unsigned int last_clear;
 357
 358         drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
 359         unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 360         int ctx_owner;
 361         int pfState;                /* number of 3d windows (0,1,2ormore) */
 362         int pfCurrentPage;          /* which buffer is being displayed? */
 363         int crtc2_base;             /* CRTC2 frame offset */
 364 } drm_radeon_sarea_t;
 365
 366
 367 /* WARNING: If you change any of these defines, make sure to change the
 368  * defines in the Xserver file (xf86drmRadeon.h)
 369  *
 370  * KW: actually it's illegal to change any of this (backwards compatibility).
 371  */
 372
 373 /* Radeon specific ioctls
 374  * The device specific ioctl range is 0x40 to 0x79.
 375  */
 376 #define DRM_RADEON_CP_INIT    0x00
 377 #define DRM_RADEON_CP_START   0x01
 378 #define DRM_RADEON_CP_STOP    0x02
 379 #define DRM_RADEON_CP_RESET   0x03
 380 #define DRM_RADEON_CP_IDLE    0x04
 381 #define DRM_RADEON_RESET      0x05
 382 #define DRM_RADEON_FULLSCREEN 0x06
 383 #define DRM_RADEON_SWAP       0x07
 384 #define DRM_RADEON_CLEAR      0x08
 385 #define DRM_RADEON_VERTEX     0x09
 386 #define DRM_RADEON_INDICES    0x0A
 387 #define DRM_RADEON_NOT_USED
 388 #define DRM_RADEON_STIPPLE    0x0C
 389 #define DRM_RADEON_INDIRECT   0x0D
 390 #define DRM_RADEON_TEXTURE    0x0E
 391 #define DRM_RADEON_VERTEX2    0x0F
 392 #define DRM_RADEON_CMDBUF     0x10
 393 #define DRM_RADEON_GETPARAM   0x11
 394 #define DRM_RADEON_FLIP       0x12
 395 #define DRM_RADEON_ALLOC      0x13
 396 #define DRM_RADEON_FREE       0x14
 397 #define DRM_RADEON_INIT_HEAP  0x15
 398 #define DRM_RADEON_IRQ_EMIT   0x16
 399 #define DRM_RADEON_IRQ_WAIT   0x17
 400 #define DRM_RADEON_CP_RESUME  0x18
 401 #define DRM_RADEON_SETPARAM   0x19
 402
 403 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 404 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 405 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 406 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 407 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 408 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
 409 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 410 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 411 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 412 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 413 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 414 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 415 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 416 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 417 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 418 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 419 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 420 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 421 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 422 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 423 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 424 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 425 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 426 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 427 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 428
 429 typedef struct drm_radeon_init {
 430         enum {
 431                 RADEON_INIT_CP    = 0x01,
 432                 RADEON_CLEANUP_CP = 0x02,
 433                 RADEON_INIT_R200_CP = 0x03
 434         } func;
 435         unsigned long sarea_priv_offset;
 436         int is_pci;
 437         int cp_mode;
 438         int gart_size;
 439         int ring_size;
 440         int usec_timeout;
 441
 442         unsigned int fb_bpp;
 443         unsigned int front_offset, front_pitch;
 444         unsigned int back_offset, back_pitch;
 445         unsigned int depth_bpp;
 446         unsigned int depth_offset, depth_pitch;
 447
 448         unsigned long fb_offset;
 449         unsigned long mmio_offset;
 450         unsigned long ring_offset;
 451         unsigned long ring_rptr_offset;
 452         unsigned long buffers_offset;
 453         unsigned long gart_textures_offset;
 454 } drm_radeon_init_t;
 455
 456 typedef struct drm_radeon_cp_stop {
 457         int flush;
 458         int idle;
 459 } drm_radeon_cp_stop_t;
 460
 461 typedef struct drm_radeon_fullscreen {
 462         enum {
 463                 RADEON_INIT_FULLSCREEN    = 0x01,
 464                 RADEON_CLEANUP_FULLSCREEN = 0x02
 465         } func;
 466 } drm_radeon_fullscreen_t;
 467
 468 #define CLEAR_X1        0
 469 #define CLEAR_Y1        1
 470 #define CLEAR_X2        2
 471 #define CLEAR_Y2        3
 472 #define CLEAR_DEPTH     4
 473
 474 typedef union drm_radeon_clear_rect {
 475         float f[5];
 476         unsigned int ui[5];
 477 } drm_radeon_clear_rect_t;
 478
 479 typedef struct drm_radeon_clear {
 480         unsigned int flags;
 481         unsigned int clear_color;
 482         unsigned int clear_depth;
 483         unsigned int color_mask;
 484         unsigned int depth_mask;   /* misnamed field:  should be stencil */
 485         drm_radeon_clear_rect_t __user *depth_boxes;
 486 } drm_radeon_clear_t;
 487
 488 typedef struct drm_radeon_vertex {
 489         int prim;
 490         int idx;                        /* Index of vertex buffer */
 491         int count;                      /* Number of vertices in buffer */
 492         int discard;                    /* Client finished with buffer? */
 493 } drm_radeon_vertex_t;
 494
 495 typedef struct drm_radeon_indices {
 496         int prim;
 497         int idx;
 498         int start;
 499         int end;
 500         int discard;                    /* Client finished with buffer? */
 501 } drm_radeon_indices_t;
 502
 503 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
 504  *      - allows multiple primitives and state changes in a single ioctl
 505  *      - supports driver change to emit native primitives
 506  */
 507 typedef struct drm_radeon_vertex2 {
 508         int idx;                        /* Index of vertex buffer */
 509         int discard;                    /* Client finished with buffer? */
 510         int nr_states;
 511         drm_radeon_state_t __user *state;
 512         int nr_prims;
 513         drm_radeon_prim_t __user *prim;
 514 } drm_radeon_vertex2_t;
 515
 516 /* v1.3 - obsoletes drm_radeon_vertex2
 517  *      - allows arbitarily large cliprect list
 518  *      - allows updating of tcl packet, vector and scalar state
 519  *      - allows memory-efficient description of state updates
 520  *      - allows state to be emitted without a primitive
 521  *           (for clears, ctx switches)
 522  *      - allows more than one dma buffer to be referenced per ioctl
 523  *      - supports tcl driver
 524  *      - may be extended in future versions with new cmd types, packets
 525  */
 526 typedef struct drm_radeon_cmd_buffer {
 527         int bufsz;
 528         char __user *buf;
 529         int nbox;
 530         drm_clip_rect_t __user *boxes;
 531 } drm_radeon_cmd_buffer_t;
 532
 533 typedef struct drm_radeon_tex_image {
 534         unsigned int x, y;              /* Blit coordinates */
 535         unsigned int width, height;
 536         const void __user *data;
 537 } drm_radeon_tex_image_t;
 538
 539 typedef struct drm_radeon_texture {
 540         unsigned int offset;
 541         int pitch;
 542         int format;
 543         int width;                      /* Texture image coordinates */
 544         int height;
 545         drm_radeon_tex_image_t __user *image;
 546 } drm_radeon_texture_t;
 547
 548 typedef struct drm_radeon_stipple {
 549         unsigned int __user *mask;
 550 } drm_radeon_stipple_t;
 551
 552 typedef struct drm_radeon_indirect {
 553         int idx;
 554         int start;
 555         int end;
 556         int discard;
 557 } drm_radeon_indirect_t;
 558
 559
 560 /* 1.3: An ioctl to get parameters that aren't available to the 3d
 561  * client any other way.
 562  */
 563 #define RADEON_PARAM_GART_BUFFER_OFFSET    1 /* card offset of 1st GART buffer */
 564 #define RADEON_PARAM_LAST_FRAME            2
 565 #define RADEON_PARAM_LAST_DISPATCH         3
 566 #define RADEON_PARAM_LAST_CLEAR            4
 567 /* Added with DRM version 1.6. */
 568 #define RADEON_PARAM_IRQ_NR                5
 569 #define RADEON_PARAM_GART_BASE             6 /* card offset of GART base */
 570 /* Added with DRM version 1.8. */
 571 #define RADEON_PARAM_REGISTER_HANDLE       7 /* for drmMap() */
 572 #define RADEON_PARAM_STATUS_HANDLE         8
 573 #define RADEON_PARAM_SAREA_HANDLE          9
 574 #define RADEON_PARAM_GART_TEX_HANDLE       10
 575 #define RADEON_PARAM_SCRATCH_OFFSET        11
 576
 577 typedef struct drm_radeon_getparam {
 578         int param;
 579         void __user *value;
 580 } drm_radeon_getparam_t;
 581
 582 /* 1.6: Set up a memory manager for regions of shared memory:
 583  */
 584 #define RADEON_MEM_REGION_GART 1
 585 #define RADEON_MEM_REGION_FB   2
 586
 587 typedef struct drm_radeon_mem_alloc {
 588         int region;
 589         int alignment;
 590         int size;
 591         int __user *region_offset;      /* offset from start of fb or GART */
 592 } drm_radeon_mem_alloc_t;
 593
 594 typedef struct drm_radeon_mem_free {
 595         int region;
 596         int region_offset;
 597 } drm_radeon_mem_free_t;
 598
 599 typedef struct drm_radeon_mem_init_heap {
 600         int region;
 601         int size;
 602         int start;
 603 } drm_radeon_mem_init_heap_t;
 604
 605
 606 /* 1.6: Userspace can request & wait on irq's:
 607  */
 608 typedef struct drm_radeon_irq_emit {
 609         int __user *irq_seq;
 610 } drm_radeon_irq_emit_t;
 611
 612 typedef struct drm_radeon_irq_wait {
 613         int irq_seq;
 614 } drm_radeon_irq_wait_t;
 615
 616
 617 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
 618  * the card's address space, via a new generic ioctl to set parameters
 619  */
 620
 621 typedef struct drm_radeon_setparam {
 622         unsigned int param;
 623         int64_t      value;
 624 } drm_radeon_setparam_t;
 625
 626 #define RADEON_SETPARAM_FB_LOCATION    1 /* determined framebuffer location */
 627
 628
 629 #endif