2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/kernel/entry.S
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2004 Paul Mundt
10 * Copyright (C) 2003, 2004 Richard Curnow
14 #include <linux/config.h>
15 #include <linux/errno.h>
16 #include <linux/sys.h>
18 #include <asm/processor.h>
19 #include <asm/registers.h>
20 #include <asm/unistd.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-offsets.h>
27 #define SR_ASID_MASK 0x00ff0000
28 #define SR_FD_MASK 0x00008000
29 #define SR_SS 0x08000000
30 #define SR_BL 0x10000000
31 #define SR_MD 0x40000000
36 #define EVENT_INTERRUPT 0
37 #define EVENT_FAULT_TLB 1
38 #define EVENT_FAULT_NOT_TLB 2
42 #define RESET_CAUSE 0x20
43 #define DEBUGSS_CAUSE 0x980
46 * Frame layout. Quad index.
48 #define FRAME_T(x) FRAME_TBASE+(x*8)
49 #define FRAME_R(x) FRAME_RBASE+(x*8)
50 #define FRAME_S(x) FRAME_SBASE+(x*8)
55 /* Arrange the save frame to be a multiple of 32 bytes long */
57 #define FRAME_RBASE (FRAME_SBASE+(3*8)) /* SYSCALL_ID - SSR - SPC */
58 #define FRAME_TBASE (FRAME_RBASE+(63*8)) /* r0 - r62 */
59 #define FRAME_PBASE (FRAME_TBASE+(8*8)) /* tr0 -tr7 */
60 #define FRAME_SIZE (FRAME_PBASE+(2*8)) /* pad0-pad1 */
62 #define FP_FRAME_SIZE FP_FRAME_BASE+(33*8) /* dr0 - dr31 + fpscr */
63 #define FP_FRAME_BASE 0
73 /* These are the registers saved in the TLB path that aren't saved in the first
74 level of the normal one. */
75 #define TLB_SAVED_R25 7*8
76 #define TLB_SAVED_TR1 8*8
77 #define TLB_SAVED_TR2 9*8
78 #define TLB_SAVED_TR3 10*8
79 #define TLB_SAVED_TR4 11*8
80 /* Save R0/R1 : PT-migrating compiler currently dishounours -ffixed-r0 and -ffixed-r1 causing
81 breakage otherwise. */
82 #define TLB_SAVED_R0 12*8
83 #define TLB_SAVED_R1 13*8
96 # define preempt_stop() CLI()
98 # define preempt_stop()
99 # define resume_kernel restore_all
104 #define FAST_TLBMISS_STACK_CACHELINES 4
105 #define FAST_TLBMISS_STACK_QUADWORDS (4*FAST_TLBMISS_STACK_CACHELINES)
107 /* Register back-up area for all exceptions */
109 /* Allow for 16 quadwords to be pushed by fast tlbmiss handling
110 * register saves etc. */
111 .fill FAST_TLBMISS_STACK_QUADWORDS, 8, 0x0
112 /* This is 32 byte aligned by construction */
113 /* Register back-up area for all exceptions */
133 /* Save area for RESVEC exceptions. We cannot use reg_save_area because of
134 * reentrancy. Note this area may be accessed via physical address.
135 * Align so this fits a whole single cache line, for ease of purging.
146 /* Jump table of 3rd level handlers */
148 .long do_exception_error /* 0x000 */
149 .long do_exception_error /* 0x020 */
150 .long tlb_miss_load /* 0x040 */
151 .long tlb_miss_store /* 0x060 */
152 ! ARTIFICIAL pseudo-EXPEVT setting
153 .long do_debug_interrupt /* 0x080 */
154 .long tlb_miss_load /* 0x0A0 */
155 .long tlb_miss_store /* 0x0C0 */
156 .long do_address_error_load /* 0x0E0 */
157 .long do_address_error_store /* 0x100 */
158 #ifndef CONFIG_NOFPU_SUPPORT
159 .long do_fpu_error /* 0x120 */
161 .long do_exception_error /* 0x120 */
163 .long do_exception_error /* 0x140 */
164 .long system_call /* 0x160 */
165 .long do_reserved_inst /* 0x180 */
166 .long do_illegal_slot_inst /* 0x1A0 */
167 .long do_NMI /* 0x1C0 */
168 .long do_exception_error /* 0x1E0 */
170 .long do_IRQ /* 0x200 - 0x3C0 */
172 .long do_exception_error /* 0x3E0 */
174 .long do_IRQ /* 0x400 - 0x7E0 */
176 .long fpu_error_or_IRQA /* 0x800 */
177 .long fpu_error_or_IRQB /* 0x820 */
178 .long do_IRQ /* 0x840 */
179 .long do_IRQ /* 0x860 */
181 .long do_exception_error /* 0x880 - 0x920 */
183 .long do_software_break_point /* 0x940 */
184 .long do_exception_error /* 0x960 */
185 .long do_single_step /* 0x980 */
188 .long do_exception_error /* 0x9A0 - 0x9E0 */
190 .long do_IRQ /* 0xA00 */
191 .long do_IRQ /* 0xA20 */
192 .long itlb_miss_or_IRQ /* 0xA40 */
193 .long do_IRQ /* 0xA60 */
194 .long do_IRQ /* 0xA80 */
195 .long itlb_miss_or_IRQ /* 0xAA0 */
196 .long do_exception_error /* 0xAC0 */
197 .long do_address_error_exec /* 0xAE0 */
199 .long do_exception_error /* 0xB00 - 0xBE0 */
202 .long do_IRQ /* 0xC00 - 0xE20 */
205 .section .text64, "ax"
208 * --- Exception/Interrupt/Event Handling Section
212 * VBR and RESVEC blocks.
214 * First level handler for VBR-based exceptions.
216 * To avoid waste of space, align to the maximum text block size.
217 * This is assumed to be at most 128 bytes or 32 instructions.
218 * DO NOT EXCEED 32 instructions on the first level handlers !
220 * Also note that RESVEC is contained within the VBR block
221 * where the room left (1KB - TEXT_SIZE) allows placing
222 * the RESVEC block (at most 512B + TEXT_SIZE).
224 * So first (and only) level handler for RESVEC-based exceptions.
226 * Where the fault/interrupt is handled (not_a_tlb_miss, tlb_miss
227 * and interrupt) we are a lot tight with register space until
228 * saving onto the stack frame, which is done in handle_exception().
232 #define TEXT_SIZE 128
233 #define BLOCK_SIZE 1664 /* Dynamic check, 13*128 */
237 .space 256, 0 /* Power-on class handler, */
238 /* not required here */
240 /* Save original stack pointer into KCR1 */
243 /* Save other original registers into reg_save_area */
244 movi reg_save_area, SP
245 st.q SP, SAVED_R2, r2
246 st.q SP, SAVED_R3, r3
247 st.q SP, SAVED_R4, r4
248 st.q SP, SAVED_R5, r5
249 st.q SP, SAVED_R6, r6
250 st.q SP, SAVED_R18, r18
252 st.q SP, SAVED_TR0, r3
254 /* Set args for Non-debug, Not a TLB miss class handler */
256 movi ret_from_exception, r3
258 movi EVENT_FAULT_NOT_TLB, r4
261 pta handle_exception, tr0
272 * Instead of the natural .balign 1024 place RESVEC here
273 * respecting the final 1KB alignment.
277 * Instead of '.space 1024-TEXT_SIZE' place the RESVEC
278 * block making sure the final alignment is correct.
282 movi reg_save_area, SP
283 /* SP is guaranteed 32-byte aligned. */
284 st.q SP, TLB_SAVED_R0 , r0
285 st.q SP, TLB_SAVED_R1 , r1
286 st.q SP, SAVED_R2 , r2
287 st.q SP, SAVED_R3 , r3
288 st.q SP, SAVED_R4 , r4
289 st.q SP, SAVED_R5 , r5
290 st.q SP, SAVED_R6 , r6
291 st.q SP, SAVED_R18, r18
293 /* Save R25 for safety; as/ld may want to use it to achieve the call to
294 * the code in mm/tlbmiss.c */
295 st.q SP, TLB_SAVED_R25, r25
301 st.q SP, SAVED_TR0 , r2
302 st.q SP, TLB_SAVED_TR1 , r3
303 st.q SP, TLB_SAVED_TR2 , r4
304 st.q SP, TLB_SAVED_TR3 , r5
305 st.q SP, TLB_SAVED_TR4 , r18
307 pt do_fast_page_fault, tr0
312 andi r2, 1, r2 /* r2 = SSR.MD */
315 pt fixup_to_invoke_general_handler, tr1
317 /* If the fast path handler fixed the fault, just drop through quickly
318 to the restore code right away to return to the excepting context.
322 fast_tlb_miss_restore:
323 ld.q SP, SAVED_TR0, r2
324 ld.q SP, TLB_SAVED_TR1, r3
325 ld.q SP, TLB_SAVED_TR2, r4
327 ld.q SP, TLB_SAVED_TR3, r5
328 ld.q SP, TLB_SAVED_TR4, r18
336 ld.q SP, TLB_SAVED_R0, r0
337 ld.q SP, TLB_SAVED_R1, r1
338 ld.q SP, SAVED_R2, r2
339 ld.q SP, SAVED_R3, r3
340 ld.q SP, SAVED_R4, r4
341 ld.q SP, SAVED_R5, r5
342 ld.q SP, SAVED_R6, r6
343 ld.q SP, SAVED_R18, r18
344 ld.q SP, TLB_SAVED_R25, r25
348 nop /* for safety, in case the code is run on sh5-101 cut1.x */
350 fixup_to_invoke_general_handler:
352 /* OK, new method. Restore stuff that's not expected to get saved into
353 the 'first-level' reg save area, then just fall through to setting
354 up the registers and calling the second-level handler. */
356 /* 2nd level expects r2,3,4,5,6,18,tr0 to be saved. So we must restore
357 r25,tr1-4 and save r6 to get into the right state. */
359 ld.q SP, TLB_SAVED_TR1, r3
360 ld.q SP, TLB_SAVED_TR2, r4
361 ld.q SP, TLB_SAVED_TR3, r5
362 ld.q SP, TLB_SAVED_TR4, r18
363 ld.q SP, TLB_SAVED_R25, r25
365 ld.q SP, TLB_SAVED_R0, r0
366 ld.q SP, TLB_SAVED_R1, r1
373 /* Set args for Non-debug, TLB miss class handler */
375 movi ret_from_exception, r3
377 movi EVENT_FAULT_TLB, r4
380 pta handle_exception, tr0
383 /* NB TAKE GREAT CARE HERE TO ENSURE THAT THE INTERRUPT CODE
384 DOES END UP AT VBR+0x600 */
396 /* Save original stack pointer into KCR1 */
399 /* Save other original registers into reg_save_area */
400 movi reg_save_area, SP
401 st.q SP, SAVED_R2, r2
402 st.q SP, SAVED_R3, r3
403 st.q SP, SAVED_R4, r4
404 st.q SP, SAVED_R5, r5
405 st.q SP, SAVED_R6, r6
406 st.q SP, SAVED_R18, r18
408 st.q SP, SAVED_TR0, r3
410 /* Set args for interrupt class handler */
412 movi ret_from_irq, r3
414 movi EVENT_INTERRUPT, r4
417 pta handle_exception, tr0
419 .balign TEXT_SIZE /* let's waste the bare minimum */
421 LVBR_block_end: /* Marker. Used for total checking */
425 /* Panic handler. Called with MMU off. Possible causes/actions:
426 * - Reset: Jump to program start.
427 * - Single Step: Turn off Single Step & return.
428 * - Others: Call panic handler, passing PC as arg.
429 * (this may need to be extended...)
433 /* First save r0-1 and tr0, as we need to use these */
434 movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
443 sub r1, r0, r1 /* r1=0 if reset */
444 movi _stext-CONFIG_CACHED_MEMORY_OFFSET, r0
447 beqi r1, 0, tr0 /* Jump to start address if reset */
450 movi DEBUGSS_CAUSE, r1
451 sub r1, r0, r1 /* r1=0 if single step */
452 pta single_step_panic, tr0
453 beqi r1, 0, tr0 /* jump if single step */
455 /* Now jump to where we save the registers. */
456 movi panic_stash_regs-CONFIG_CACHED_MEMORY_OFFSET, r1
461 /* We are in a handler with Single Step set. We need to resume the
462 * handler, by turning on MMU & turning off Single Step. */
469 /* Restore EXPEVT, as the rte won't do this */
485 * Single step/software_break_point first level handler.
486 * Called with MMU off, so the first thing we do is enable it
487 * by doing an rte with appropriate SSR.
490 /* Save SSR & SPC, together with R0 & R1, as we need to use 2 regs. */
491 movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
493 /* With the MMU off, we are bypassing the cache, so purge any
494 * data that will be made stale by the following stores.
506 /* Enable MMU, block exceptions, set priv mode, disable single step */
507 movi SR_MMU | SR_BL | SR_MD, r1
512 /* Force control to debug_exception_2 when rte is executed */
513 movi debug_exeception_2, r0
514 ori r0, 1, r0 /* force SHmedia, just in case */
520 /* Restore saved regs */
522 movi resvec_save_area, SP
530 /* Save other original registers into reg_save_area */
531 movi reg_save_area, SP
532 st.q SP, SAVED_R2, r2
533 st.q SP, SAVED_R3, r3
534 st.q SP, SAVED_R4, r4
535 st.q SP, SAVED_R5, r5
536 st.q SP, SAVED_R6, r6
537 st.q SP, SAVED_R18, r18
539 st.q SP, SAVED_TR0, r3
541 /* Set args for debug class handler */
543 movi ret_from_exception, r3
548 pta handle_exception, tr0
553 /* !!! WE COME HERE IN REAL MODE !!! */
554 /* Hook-up debug interrupt to allow various debugging options to be
555 * hooked into its handler. */
556 /* Save original stack pointer into KCR1 */
559 movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
564 /* Save other original registers into reg_save_area thru real addresses */
565 st.q SP, SAVED_R2, r2
566 st.q SP, SAVED_R3, r3
567 st.q SP, SAVED_R4, r4
568 st.q SP, SAVED_R5, r5
569 st.q SP, SAVED_R6, r6
570 st.q SP, SAVED_R18, r18
572 st.q SP, SAVED_TR0, r3
574 /* move (spc,ssr)->(pspc,pssr). The rte will shift
575 them back again, so that they look like the originals
576 as far as the real handler code is concerned. */
582 ! construct useful SR for handle_exception
589 ! SSR is now the current SR with the MD and MMU bits set
590 ! i.e. the rte will switch back to priv mode and put
594 movi handle_exception, r18
595 ori r18, 1, r18 ! for safety (do we need this?)
598 /* Set args for Non-debug, Not a TLB miss class handler */
600 ! EXPEVT==0x80 is unused, so 'steal' this value to put the
601 ! debug interrupt handler in the vectoring table
603 movi ret_from_exception, r3
605 movi EVENT_FAULT_NOT_TLB, r4
608 movi CONFIG_CACHED_MEMORY_OFFSET, r6
613 rte ! -> handle_exception, switch back to priv mode again
615 LRESVEC_block_end: /* Marker. Unused. */
620 * Second level handler for VBR-based exceptions. Pre-handler.
621 * In common to all stack-frame sensitive handlers.
624 * (KCR0) Current [current task union]
627 * (r3) appropriate return address
628 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault, 3=debug)
629 * (r5) Pointer to reg_save_area
632 * Available registers:
639 /* Common 2nd level handler. */
641 /* First thing we need an appropriate stack pointer */
646 bne r6, ZERO, tr0 /* Original stack pointer is fine */
648 /* Set stack pointer for user fault */
650 movi THREAD_SIZE, r6 /* Point to the end */
655 /* DEBUG : check for underflow/overflow of the kernel stack */
656 pta no_underflow, tr0
660 bge SP, r6, tr0 ! ? below 1k from bottom of stack : danger zone
662 /* Just panic to cause a crash. */
670 movi THREAD_SIZE, r18
672 bgt SP, r6, tr0 ! sp above the stack
674 /* Make some room for the BASIC frame. */
675 movi -(FRAME_SIZE), r6
678 /* Could do this with no stalling if we had another spare register, but the
679 code below will be OK. */
680 ld.q r5, SAVED_R2, r6
681 ld.q r5, SAVED_R3, r18
682 st.q SP, FRAME_R(2), r6
683 ld.q r5, SAVED_R4, r6
684 st.q SP, FRAME_R(3), r18
685 ld.q r5, SAVED_R5, r18
686 st.q SP, FRAME_R(4), r6
687 ld.q r5, SAVED_R6, r6
688 st.q SP, FRAME_R(5), r18
689 ld.q r5, SAVED_R18, r18
690 st.q SP, FRAME_R(6), r6
691 ld.q r5, SAVED_TR0, r6
692 st.q SP, FRAME_R(18), r18
693 st.q SP, FRAME_T(0), r6
695 /* Keep old SP around */
698 /* Save the rest of the general purpose registers */
699 st.q SP, FRAME_R(0), r0
700 st.q SP, FRAME_R(1), r1
701 st.q SP, FRAME_R(7), r7
702 st.q SP, FRAME_R(8), r8
703 st.q SP, FRAME_R(9), r9
704 st.q SP, FRAME_R(10), r10
705 st.q SP, FRAME_R(11), r11
706 st.q SP, FRAME_R(12), r12
707 st.q SP, FRAME_R(13), r13
708 st.q SP, FRAME_R(14), r14
710 /* SP is somewhere else */
711 st.q SP, FRAME_R(15), r6
713 st.q SP, FRAME_R(16), r16
714 st.q SP, FRAME_R(17), r17
715 /* r18 is saved earlier. */
716 st.q SP, FRAME_R(19), r19
717 st.q SP, FRAME_R(20), r20
718 st.q SP, FRAME_R(21), r21
719 st.q SP, FRAME_R(22), r22
720 st.q SP, FRAME_R(23), r23
721 st.q SP, FRAME_R(24), r24
722 st.q SP, FRAME_R(25), r25
723 st.q SP, FRAME_R(26), r26
724 st.q SP, FRAME_R(27), r27
725 st.q SP, FRAME_R(28), r28
726 st.q SP, FRAME_R(29), r29
727 st.q SP, FRAME_R(30), r30
728 st.q SP, FRAME_R(31), r31
729 st.q SP, FRAME_R(32), r32
730 st.q SP, FRAME_R(33), r33
731 st.q SP, FRAME_R(34), r34
732 st.q SP, FRAME_R(35), r35
733 st.q SP, FRAME_R(36), r36
734 st.q SP, FRAME_R(37), r37
735 st.q SP, FRAME_R(38), r38
736 st.q SP, FRAME_R(39), r39
737 st.q SP, FRAME_R(40), r40
738 st.q SP, FRAME_R(41), r41
739 st.q SP, FRAME_R(42), r42
740 st.q SP, FRAME_R(43), r43
741 st.q SP, FRAME_R(44), r44
742 st.q SP, FRAME_R(45), r45
743 st.q SP, FRAME_R(46), r46
744 st.q SP, FRAME_R(47), r47
745 st.q SP, FRAME_R(48), r48
746 st.q SP, FRAME_R(49), r49
747 st.q SP, FRAME_R(50), r50
748 st.q SP, FRAME_R(51), r51
749 st.q SP, FRAME_R(52), r52
750 st.q SP, FRAME_R(53), r53
751 st.q SP, FRAME_R(54), r54
752 st.q SP, FRAME_R(55), r55
753 st.q SP, FRAME_R(56), r56
754 st.q SP, FRAME_R(57), r57
755 st.q SP, FRAME_R(58), r58
756 st.q SP, FRAME_R(59), r59
757 st.q SP, FRAME_R(60), r60
758 st.q SP, FRAME_R(61), r61
759 st.q SP, FRAME_R(62), r62
762 * Save the S* registers.
765 st.q SP, FRAME_S(FSSR), r61
767 st.q SP, FRAME_S(FSPC), r62
768 movi -1, r62 /* Reset syscall_nr */
769 st.q SP, FRAME_S(FSYSCALL_ID), r62
771 /* Save the rest of the target registers */
773 st.q SP, FRAME_T(1), r6
775 st.q SP, FRAME_T(2), r6
777 st.q SP, FRAME_T(3), r6
779 st.q SP, FRAME_T(4), r6
781 st.q SP, FRAME_T(5), r6
783 st.q SP, FRAME_T(6), r6
785 st.q SP, FRAME_T(7), r6
787 ! setup FP so that unwinder can wind back through nested kernel mode
791 #define POOR_MANS_STRACE 0
794 /* We've pushed all the registers now, so only r2-r4 hold anything
795 * useful. Move them into callee save registers */
800 /* Preserve r2 as the event code */
815 /* For syscall and debug race condition, get TRA now */
818 /* We are in a safe position to turn SR.BL off, but set IMASK=0xf
819 * Also set FD, to catch FPU usage in the kernel.
821 * benedict.gaster@superh.com 29/07/2002
823 * On all SH5-101 revisions it is unsafe to raise the IMASK and at the
824 * same time change BL from 1->0, as any pending interrupt of a level
825 * higher than he previous value of IMASK will leak through and be
826 * taken unexpectedly.
828 * To avoid this we raise the IMASK and then issue another PUTCON to
832 movi SR_IMASK | SR_FD, r7
835 movi SR_UNBLOCK_EXC, r7
840 /* Now call the appropriate 3rd level handler */
851 * Second level handler for VBR-based exceptions. Post-handlers.
853 * Post-handlers for interrupts (ret_from_irq), exceptions
854 * (ret_from_exception) and common reentrance doors (restore_all
855 * to get back to the original context, ret_from_syscall loop to
856 * check kernel exiting).
858 * ret_with_reschedule and work_notifysig are an inner lables of
859 * the ret_from_syscall loop.
861 * In common to all stack-frame sensitive handlers.
864 * (SP) struct pt_regs *, original register's frame pointer (basic)
870 pta evt_debug_ret_from_irq, tr0
874 ld.q SP, FRAME_S(FSSR), r6
877 pta resume_kernel, tr0
878 bne r6, ZERO, tr0 /* no further checks */
880 pta ret_with_reschedule, tr0
881 blink tr0, ZERO /* Do not check softirqs */
883 .global ret_from_exception
888 pta evt_debug_ret_from_exc, tr0
893 ld.q SP, FRAME_S(FSSR), r6
896 pta resume_kernel, tr0
897 bne r6, ZERO, tr0 /* no further checks */
901 #ifdef CONFIG_PREEMPT
902 pta ret_from_syscall, tr0
909 ld.l r6, TI_PRE_COUNT, r7
913 ld.l r6, TI_FLAGS, r7
914 movi (1 << TIF_NEED_RESCHED), r8
922 movi ((PREEMPT_ACTIVE >> 16) & 65535), r8
923 shori (PREEMPT_ACTIVE & 65535), r8
924 st.l r6, TI_PRE_COUNT, r8
932 st.l r6, TI_PRE_COUNT, ZERO
935 pta need_resched, tr1
939 .global ret_from_syscall
943 getcon KCR0, r6 ! r6 contains current_thread_info
944 ld.l r6, TI_FLAGS, r7 ! r7 contains current_thread_info->flags
947 ! no handling of TIF_SYSCALL_TRACE yet!!
949 movi (1 << TIF_NEED_RESCHED), r8
951 pta work_resched, tr0
956 movi (1 << TIF_SIGPENDING), r8
958 pta work_notifysig, tr0
964 pta ret_from_syscall, tr0
968 blink tr0, ZERO /* Call schedule(), return on top */
977 blink tr0, LINK /* Call do_signal(regs, 0), return here */
982 ld.q SP, FRAME_T(0), r6
983 ld.q SP, FRAME_T(1), r7
984 ld.q SP, FRAME_T(2), r8
985 ld.q SP, FRAME_T(3), r9
990 ld.q SP, FRAME_T(4), r6
991 ld.q SP, FRAME_T(5), r7
992 ld.q SP, FRAME_T(6), r8
993 ld.q SP, FRAME_T(7), r9
999 ld.q SP, FRAME_R(0), r0
1000 ld.q SP, FRAME_R(1), r1
1001 ld.q SP, FRAME_R(2), r2
1002 ld.q SP, FRAME_R(3), r3
1003 ld.q SP, FRAME_R(4), r4
1004 ld.q SP, FRAME_R(5), r5
1005 ld.q SP, FRAME_R(6), r6
1006 ld.q SP, FRAME_R(7), r7
1007 ld.q SP, FRAME_R(8), r8
1008 ld.q SP, FRAME_R(9), r9
1009 ld.q SP, FRAME_R(10), r10
1010 ld.q SP, FRAME_R(11), r11
1011 ld.q SP, FRAME_R(12), r12
1012 ld.q SP, FRAME_R(13), r13
1013 ld.q SP, FRAME_R(14), r14
1015 ld.q SP, FRAME_R(16), r16
1016 ld.q SP, FRAME_R(17), r17
1017 ld.q SP, FRAME_R(18), r18
1018 ld.q SP, FRAME_R(19), r19
1019 ld.q SP, FRAME_R(20), r20
1020 ld.q SP, FRAME_R(21), r21
1021 ld.q SP, FRAME_R(22), r22
1022 ld.q SP, FRAME_R(23), r23
1023 ld.q SP, FRAME_R(24), r24
1024 ld.q SP, FRAME_R(25), r25
1025 ld.q SP, FRAME_R(26), r26
1026 ld.q SP, FRAME_R(27), r27
1027 ld.q SP, FRAME_R(28), r28
1028 ld.q SP, FRAME_R(29), r29
1029 ld.q SP, FRAME_R(30), r30
1030 ld.q SP, FRAME_R(31), r31
1031 ld.q SP, FRAME_R(32), r32
1032 ld.q SP, FRAME_R(33), r33
1033 ld.q SP, FRAME_R(34), r34
1034 ld.q SP, FRAME_R(35), r35
1035 ld.q SP, FRAME_R(36), r36
1036 ld.q SP, FRAME_R(37), r37
1037 ld.q SP, FRAME_R(38), r38
1038 ld.q SP, FRAME_R(39), r39
1039 ld.q SP, FRAME_R(40), r40
1040 ld.q SP, FRAME_R(41), r41
1041 ld.q SP, FRAME_R(42), r42
1042 ld.q SP, FRAME_R(43), r43
1043 ld.q SP, FRAME_R(44), r44
1044 ld.q SP, FRAME_R(45), r45
1045 ld.q SP, FRAME_R(46), r46
1046 ld.q SP, FRAME_R(47), r47
1047 ld.q SP, FRAME_R(48), r48
1048 ld.q SP, FRAME_R(49), r49
1049 ld.q SP, FRAME_R(50), r50
1050 ld.q SP, FRAME_R(51), r51
1051 ld.q SP, FRAME_R(52), r52
1052 ld.q SP, FRAME_R(53), r53
1053 ld.q SP, FRAME_R(54), r54
1054 ld.q SP, FRAME_R(55), r55
1055 ld.q SP, FRAME_R(56), r56
1056 ld.q SP, FRAME_R(57), r57
1057 ld.q SP, FRAME_R(58), r58
1060 movi SR_BLOCK_EXC, r60
1062 putcon r59, SR /* SR.BL = 1, keep nesting out */
1063 ld.q SP, FRAME_S(FSSR), r61
1064 ld.q SP, FRAME_S(FSPC), r62
1065 movi SR_ASID_MASK, r60
1067 andc r61, r60, r61 /* Clear out older ASID */
1068 or r59, r61, r61 /* Retain current ASID */
1072 /* Ignore FSYSCALL_ID */
1074 ld.q SP, FRAME_R(59), r59
1075 ld.q SP, FRAME_R(60), r60
1076 ld.q SP, FRAME_R(61), r61
1077 ld.q SP, FRAME_R(62), r62
1080 ld.q SP, FRAME_R(15), SP
1085 * Third level handlers for VBR-based exceptions. Adapting args to
1086 * and/or deflecting to fourth level handlers.
1088 * Fourth level handlers interface.
1089 * Most are C-coded handlers directly pointed by the trap_jtable.
1090 * (Third = Fourth level)
1092 * (r2) fault/interrupt code, entry number (e.g. NMI = 14,
1093 * IRL0-3 (0000) = 16, RTLBMISS = 2, SYSCALL = 11, etc ...)
1094 * (r3) struct pt_regs *, original register's frame pointer
1095 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault)
1096 * (r5) TRA control register (for syscall/debug benefit only)
1097 * (LINK) return address
1100 * Kernel TLB fault handlers will get a slightly different interface.
1101 * (r2) struct pt_regs *, original register's frame pointer
1102 * (r3) writeaccess, whether it's a store fault as opposed to load fault
1103 * (r4) execaccess, whether it's a ITLB fault as opposed to DTLB fault
1104 * (r5) Effective Address of fault
1105 * (LINK) return address
1108 * fpu_error_or_IRQ? is a helper to deflect to the right cause.
1113 or ZERO, ZERO, r3 /* Read */
1114 or ZERO, ZERO, r4 /* Data */
1116 pta call_do_page_fault, tr0
1121 movi 1, r3 /* Write */
1122 or ZERO, ZERO, r4 /* Data */
1124 pta call_do_page_fault, tr0
1129 beqi/u r4, EVENT_INTERRUPT, tr0
1131 or ZERO, ZERO, r3 /* Read */
1132 movi 1, r4 /* Text */
1137 movi do_page_fault, r6
1143 beqi/l r4, EVENT_INTERRUPT, tr0
1144 #ifndef CONFIG_NOFPU_SUPPORT
1145 movi do_fpu_state_restore, r6
1147 movi do_exception_error, r6
1154 beqi/l r4, EVENT_INTERRUPT, tr0
1155 #ifndef CONFIG_NOFPU_SUPPORT
1156 movi do_fpu_state_restore, r6
1158 movi do_exception_error, r6
1169 * system_call/unknown_trap third level handler:
1172 * (r2) fault/interrupt code, entry number (TRAP = 11)
1173 * (r3) struct pt_regs *, original register's frame pointer
1174 * (r4) Not used. Event (0=interrupt, 1=TLB miss fault, 2=Not TLB miss fault)
1175 * (r5) TRA Control Reg (0x00xyzzzz: x=1 SYSCALL, y = #args, z=nr)
1177 * (LINK) return address: ret_from_exception
1178 * (*r3) Syscall parms: SC#, arg0, arg1, ..., arg5 in order (Saved r2/r7)
1181 * (*r3) Syscall reply (Saved r2)
1182 * (LINK) In case of syscall only it can be scrapped.
1183 * Common second level post handler will be ret_from_syscall.
1184 * Common (non-trace) exit point to that is syscall_ret (saving
1185 * result to r2). Common bad exit point is syscall_bad (returning
1186 * ENOSYS then saved to r2).
1191 /* Unknown Trap or User Trace */
1192 movi do_unknown_trapa, r6
1194 ld.q r3, FRAME_R(9), r2 /* r2 = #arg << 16 | syscall # */
1195 andi r2, 0x1ff, r2 /* r2 = syscall # */
1198 pta syscall_ret, tr0
1201 /* New syscall implementation*/
1203 pta unknown_trap, tr0
1204 or r5, ZERO, r4 /* TRA (=r5) -> r4 */
1206 bnei r4, 1, tr0 /* unknown_trap if not 0x1yzzzz */
1208 /* It's a system call */
1209 st.q r3, FRAME_S(FSYSCALL_ID), r5 /* ID (0x1yzzzz) -> stack */
1210 andi r5, 0x1ff, r5 /* syscall # -> r5 */
1214 pta syscall_allowed, tr0
1215 movi NR_syscalls - 1, r4 /* Last valid */
1219 /* Return ENOSYS ! */
1220 movi -(ENOSYS), r2 /* Fall-through */
1224 st.q SP, FRAME_R(9), r2 /* Expecting SP back to BASIC frame */
1226 #if POOR_MANS_STRACE
1227 /* nothing useful in registers at this point */
1232 ld.q SP, FRAME_R(9), r2
1237 ld.q SP, FRAME_S(FSPC), r2
1238 addi r2, 4, r2 /* Move PC, being pre-execution event */
1239 st.q SP, FRAME_S(FSPC), r2
1240 pta ret_from_syscall, tr0
1244 /* A different return path for ret_from_fork, because we now need
1245 * to call schedule_tail with the later kernels. Because prev is
1246 * loaded into r2 by switch_to() means we can just call it straight away
1249 .global ret_from_fork
1252 movi schedule_tail,r5
1257 #if POOR_MANS_STRACE
1258 /* nothing useful in registers at this point */
1263 ld.q SP, FRAME_R(9), r2
1268 ld.q SP, FRAME_S(FSPC), r2
1269 addi r2, 4, r2 /* Move PC, being pre-execution event */
1270 st.q SP, FRAME_S(FSPC), r2
1271 pta ret_from_syscall, tr0
1277 /* Use LINK to deflect the exit point, default is syscall_ret */
1278 pta syscall_ret, tr0
1280 pta syscall_notrace, tr0
1283 ld.l r2, TI_FLAGS, r4
1284 movi (1 << TIF_SYSCALL_TRACE), r6
1288 /* Trace it by calling syscall_trace before and after */
1289 movi syscall_trace, r4
1292 /* Reload syscall number as r5 is trashed by syscall_trace */
1293 ld.q SP, FRAME_S(FSYSCALL_ID), r5
1296 pta syscall_ret_trace, tr0
1300 /* Now point to the appropriate 4th level syscall handler */
1301 movi sys_call_table, r4
1306 /* Prepare original args */
1307 ld.q SP, FRAME_R(2), r2
1308 ld.q SP, FRAME_R(3), r3
1309 ld.q SP, FRAME_R(4), r4
1310 ld.q SP, FRAME_R(5), r5
1311 ld.q SP, FRAME_R(6), r6
1312 ld.q SP, FRAME_R(7), r7
1314 /* And now the trick for those syscalls requiring regs * ! */
1318 blink tr0, ZERO /* LINK is already properly set */
1321 /* We get back here only if under trace */
1322 st.q SP, FRAME_R(9), r2 /* Save return value */
1324 movi syscall_trace, LINK
1328 /* This needs to be done after any syscall tracing */
1329 ld.q SP, FRAME_S(FSPC), r2
1330 addi r2, 4, r2 /* Move PC, being pre-execution event */
1331 st.q SP, FRAME_S(FSPC), r2
1333 pta ret_from_syscall, tr0
1334 blink tr0, ZERO /* Resume normal return sequence */
1337 * --- Switch to running under a particular ASID and return the previous ASID value
1338 * --- The caller is assumed to have done a cli before calling this.
1340 * Input r2 : new ASID
1341 * Output r2 : old ASID
1344 .global switch_and_save_asid
1345 switch_and_save_asid:
1348 shlli r4, 16, r4 /* r4 = mask to select ASID */
1349 and r0, r4, r3 /* r3 = shifted old ASID */
1350 andi r2, 255, r2 /* mask down new ASID */
1351 shlli r2, 16, r2 /* align new ASID against SR.ASID */
1352 andc r0, r4, r0 /* efface old ASID from SR */
1353 or r0, r2, r0 /* insert the new ASID */
1361 shlri r3, 16, r2 /* r2 = old ASID */
1364 .global route_to_panic_handler
1365 route_to_panic_handler:
1366 /* Switch to real mode, goto panic_handler, don't return. Useful for
1367 last-chance debugging, e.g. if no output wants to go to the console.
1370 movi panic_handler - CONFIG_CACHED_MEMORY_OFFSET, r1
1382 1: /* Now in real mode */
1386 .global peek_real_address_q
1387 peek_real_address_q:
1389 r2 : real mode address to peek
1390 r2(out) : result quadword
1392 This is provided as a cheapskate way of manipulating device
1393 registers for debugging (to avoid the need to onchip_remap the debug
1394 module, and to avoid the need to onchip_remap the watchpoint
1395 controller in a way that identity maps sufficient bits to avoid the
1396 SH5-101 cut2 silicon defect).
1398 This code is not performance critical
1401 add.l r2, r63, r2 /* sign extend address */
1402 getcon sr, r0 /* r0 = saved original SR */
1405 or r0, r1, r1 /* r0 with block bit set */
1406 putcon r1, sr /* now in critical section */
1409 andc r1, r36, r1 /* turn sr.mmu off in real mode section */
1412 movi .peek0 - CONFIG_CACHED_MEMORY_OFFSET, r36 /* real mode target address */
1413 movi 1f, r37 /* virtual mode return addr */
1420 .peek0: /* come here in real mode, don't touch caches!!
1421 still in critical section (sr.bl==1) */
1424 /* Here's the actual peek. If the address is bad, all bets are now off
1425 * what will happen (handlers invoked in real-mode = bad news) */
1428 rte /* Back to virtual mode */
1435 .global poke_real_address_q
1436 poke_real_address_q:
1438 r2 : real mode address to poke
1439 r3 : quadword value to write.
1441 This is provided as a cheapskate way of manipulating device
1442 registers for debugging (to avoid the need to onchip_remap the debug
1443 module, and to avoid the need to onchip_remap the watchpoint
1444 controller in a way that identity maps sufficient bits to avoid the
1445 SH5-101 cut2 silicon defect).
1447 This code is not performance critical
1450 add.l r2, r63, r2 /* sign extend address */
1451 getcon sr, r0 /* r0 = saved original SR */
1454 or r0, r1, r1 /* r0 with block bit set */
1455 putcon r1, sr /* now in critical section */
1458 andc r1, r36, r1 /* turn sr.mmu off in real mode section */
1461 movi .poke0-CONFIG_CACHED_MEMORY_OFFSET, r36 /* real mode target address */
1462 movi 1f, r37 /* virtual mode return addr */
1469 .poke0: /* come here in real mode, don't touch caches!!
1470 still in critical section (sr.bl==1) */
1473 /* Here's the actual poke. If the address is bad, all bets are now off
1474 * what will happen (handlers invoked in real-mode = bad news) */
1477 rte /* Back to virtual mode */
1485 * --- User Access Handling Section
1489 * User Access support. It all moved to non inlined Assembler
1490 * functions in here.
1492 * __kernel_size_t __copy_user(void *__to, const void *__from,
1493 * __kernel_size_t __n)
1496 * (r2) target address
1497 * (r3) source address
1498 * (r4) size in bytes
1502 * (r2) non-copied bytes
1504 * If a fault occurs on the user pointer, bail out early and return the
1505 * number of bytes not copied in r2.
1506 * Strategy : for large blocks, call a real memcpy function which can
1507 * move >1 byte at a time using unaligned ld/st instructions, and can
1508 * manipulate the cache using prefetch + alloco to improve the speed
1509 * further. If a fault occurs in that function, just revert to the
1510 * byte-by-byte approach used for small blocks; this is rare so the
1511 * performance hit for that case does not matter.
1513 * For small blocks it's not worth the overhead of setting up and calling
1514 * the memcpy routine; do the copy a byte at a time.
1519 pta __copy_user_byte_by_byte, tr1
1520 movi 16, r0 ! this value is a best guess, should tune it by benchmarking
1522 pta copy_user_memcpy, tr0
1524 /* Save arguments in case we have to fix-up unhandled page fault */
1528 st.q SP, 24, r35 ! r35 is callee-save
1529 /* Save LINK in a register to reduce RTS time later (otherwise
1530 ld SP,*,LINK;ptabs LINK;trn;blink trn,r63 becomes a critical path) */
1534 /* Copy completed normally if we get back here */
1537 /* don't restore r2-r4, pointless */
1538 /* set result=r2 to zero as the copy must have succeeded. */
1541 blink tr0, r63 ! RTS
1543 .global __copy_user_fixup
1545 /* Restore stack frame */
1552 /* Fall through to original code, in the 'same' state we entered with */
1554 /* The slow byte-by-byte method is used if the fast copy traps due to a bad
1555 user address. In that rare case, the speed drop can be tolerated. */
1556 __copy_user_byte_by_byte:
1557 pta ___copy_user_exit, tr1
1558 pta ___copy_user1, tr0
1559 beq/u r4, r63, tr1 /* early exit for zero length copy */
1564 ld.b r3, 0, r5 /* Fault address 1 */
1566 /* Could rewrite this to use just 1 add, but the second comes 'free'
1567 due to load latency */
1569 addi r4, -1, r4 /* No real fixup required */
1571 stx.b r3, r0, r5 /* Fault address 2 */
1580 * __kernel_size_t __clear_user(void *addr, __kernel_size_t size)
1583 * (r2) target address
1584 * (r3) size in bytes
1587 * (*r2) zero-ed target data
1588 * (r2) non-zero-ed bytes
1590 .global __clear_user
1592 pta ___clear_user_exit, tr1
1593 pta ___clear_user1, tr0
1597 st.b r2, 0, ZERO /* Fault address */
1599 addi r3, -1, r3 /* No real fixup required */
1609 * int __strncpy_from_user(unsigned long __dest, unsigned long __src,
1613 * (r2) target address
1614 * (r3) source address
1615 * (r4) maximum size in bytes
1619 * (r2) -EFAULT (in case of faulting)
1620 * copied data (otherwise)
1622 .global __strncpy_from_user
1623 __strncpy_from_user:
1624 pta ___strncpy_from_user1, tr0
1625 pta ___strncpy_from_user_done, tr1
1626 or r4, ZERO, r5 /* r5 = original count */
1627 beq/u r4, r63, tr1 /* early exit if r4==0 */
1628 movi -(EFAULT), r6 /* r6 = reply, no real fixup */
1629 or ZERO, ZERO, r7 /* r7 = data, clear top byte of data */
1631 ___strncpy_from_user1:
1632 ld.b r3, 0, r7 /* Fault address: only in reading */
1637 addi r4, -1, r4 /* return real number of copied bytes */
1640 ___strncpy_from_user_done:
1641 sub r5, r4, r6 /* If done, return copied */
1643 ___strncpy_from_user_exit:
1649 * extern long __strnlen_user(const char *__s, long __n)
1652 * (r2) source address
1653 * (r3) source size in bytes
1656 * (r2) -EFAULT (in case of faulting)
1657 * string length (otherwise)
1659 .global __strnlen_user
1661 pta ___strnlen_user_set_reply, tr0
1662 pta ___strnlen_user1, tr1
1663 or ZERO, ZERO, r5 /* r5 = counter */
1664 movi -(EFAULT), r6 /* r6 = reply, no real fixup */
1665 or ZERO, ZERO, r7 /* r7 = data, clear top byte of data */
1669 ldx.b r2, r5, r7 /* Fault address: only in reading */
1670 addi r3, -1, r3 /* No real fixup */
1674 ! The line below used to be active. This meant led to a junk byte lying between each pair
1675 ! of entries in the argv & envp structures in memory. Whilst the program saw the right data
1676 ! via the argv and envp arguments to main, it meant the 'flat' representation visible through
1677 ! /proc/$pid/cmdline was corrupt, causing trouble with ps, for example.
1678 ! addi r5, 1, r5 /* Include '\0' */
1680 ___strnlen_user_set_reply:
1681 or r5, ZERO, r6 /* If done, return counter */
1683 ___strnlen_user_exit:
1689 * extern long __get_user_asm_?(void *val, long addr)
1693 * (r3) source address (in User Space)
1696 * (r2) -EFAULT (faulting)
1699 .global __get_user_asm_b
1702 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1705 ld.b r3, 0, r5 /* r5 = data */
1709 ___get_user_asm_b_exit:
1714 .global __get_user_asm_w
1717 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1720 ld.w r3, 0, r5 /* r5 = data */
1724 ___get_user_asm_w_exit:
1729 .global __get_user_asm_l
1732 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1735 ld.l r3, 0, r5 /* r5 = data */
1739 ___get_user_asm_l_exit:
1744 .global __get_user_asm_q
1747 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1750 ld.q r3, 0, r5 /* r5 = data */
1754 ___get_user_asm_q_exit:
1759 * extern long __put_user_asm_?(void *pval, long addr)
1762 * (r2) kernel pointer to value
1763 * (r3) dest address (in User Space)
1766 * (r2) -EFAULT (faulting)
1769 .global __put_user_asm_b
1771 ld.b r2, 0, r4 /* r4 = data */
1772 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1778 ___put_user_asm_b_exit:
1783 .global __put_user_asm_w
1785 ld.w r2, 0, r4 /* r4 = data */
1786 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1792 ___put_user_asm_w_exit:
1797 .global __put_user_asm_l
1799 ld.l r2, 0, r4 /* r4 = data */
1800 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1806 ___put_user_asm_l_exit:
1811 .global __put_user_asm_q
1813 ld.q r2, 0, r4 /* r4 = data */
1814 movi -(EFAULT), r2 /* r2 = reply, no real fixup */
1820 ___put_user_asm_q_exit:
1825 /* The idea is : when we get an unhandled panic, we dump the registers
1826 to a known memory location, the just sit in a tight loop.
1827 This allows the human to look at the memory region through the GDB
1828 session (assuming the debug module's SHwy initiator isn't locked up
1829 or anything), to hopefully analyze the cause of the panic. */
1831 /* On entry, former r15 (SP) is in DCR
1832 former r0 is at resvec_saved_area + 0
1833 former r1 is at resvec_saved_area + 8
1834 former tr0 is at resvec_saved_area + 32
1835 DCR is the only register whose value is lost altogether.
1838 movi 0xffffffff80000000, r0 ! phy of dump area
1839 ld.q SP, 0x000, r1 ! former r0
1841 ld.q SP, 0x008, r1 ! former r1
1905 st.q r0, 0x1f8, r63 ! bogus, but for consistency's sake...
1907 ld.q SP, 0x020, r1 ! former tr0
1957 /* Prepare to jump to C - physical address */
1958 movi panic_handler-CONFIG_CACHED_MEMORY_OFFSET, r1
1972 * --- Signal Handling Section
1976 * extern long long _sa_default_rt_restorer
1977 * extern long long _sa_default_restorer
1981 * extern void _sa_default_rt_restorer(void)
1982 * extern void _sa_default_restorer(void)
1984 * Code prototypes to do a sys_rt_sigreturn() or sys_sysreturn()
1985 * from user space. Copied into user space by signal management.
1986 * Both must be quad aligned and 2 quad long (4 instructions).
1990 .global sa_default_rt_restorer
1991 sa_default_rt_restorer:
1993 shori __NR_rt_sigreturn, r9
1998 .global sa_default_restorer
1999 sa_default_restorer:
2001 shori __NR_sigreturn, r9
2006 * --- __ex_table Section
2010 * User Access Exception Table.
2012 .section __ex_table, "a"
2014 .global asm_uaccess_start /* Just a marker */
2017 .long ___copy_user1, ___copy_user_exit
2018 .long ___copy_user2, ___copy_user_exit
2019 .long ___clear_user1, ___clear_user_exit
2020 .long ___strncpy_from_user1, ___strncpy_from_user_exit
2021 .long ___strnlen_user1, ___strnlen_user_exit
2022 .long ___get_user_asm_b1, ___get_user_asm_b_exit
2023 .long ___get_user_asm_w1, ___get_user_asm_w_exit
2024 .long ___get_user_asm_l1, ___get_user_asm_l_exit
2025 .long ___get_user_asm_q1, ___get_user_asm_q_exit
2026 .long ___put_user_asm_b1, ___put_user_asm_b_exit
2027 .long ___put_user_asm_w1, ___put_user_asm_w_exit
2028 .long ___put_user_asm_l1, ___put_user_asm_l_exit
2029 .long ___put_user_asm_q1, ___put_user_asm_q_exit
2031 .global asm_uaccess_end /* Just a marker */
2038 * --- .text.init Section
2041 .section .text.init, "ax"
2044 * void trap_init (void)
2049 addi SP, -24, SP /* Room to save r28/r29/r30 */
2054 /* Set VBR and RESVEC */
2055 movi LVBR_block, r19
2056 andi r19, -4, r19 /* reset MMUOFF + reserved */
2057 /* For RESVEC exceptions we force the MMU off, which means we need the
2058 physical address. */
2059 movi LRESVEC_block-CONFIG_CACHED_MEMORY_OFFSET, r20
2060 andi r20, -4, r20 /* reset reserved */
2061 ori r20, 1, r20 /* set MMUOFF */
2066 movi LVBR_block_end, r21
2068 movi BLOCK_SIZE, r29 /* r29 = expected size */
2073 * Ugly, but better loop forever now than crash afterwards.
2074 * We should print a message, but if we touch LVBR or
2075 * LRESVEC blocks we should not be surprised if we get stuck
2078 pta trap_init_loop, tr1
2079 gettr tr1, r28 /* r28 = trap_init_loop */
2080 sub r21, r30, r30 /* r30 = actual size */
2083 * VBR/RESVEC handlers overlap by being bigger than
2084 * allowed. Very bad. Just loop forever.
2085 * (r28) panic/loop address
2086 * (r29) expected size
2092 /* Now that exception vectors are set up reset SR.BL */
2094 movi SR_UNBLOCK_EXC, r23