2 * Modifications by Matt Porter (mporter@mvista.com) to support
3 * PPC44x Book E processors.
5 * This file contains the routines for initializing the MMU
6 * on the 4xx series of chips.
9 * Derived from arch/ppc/mm/init.c:
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
12 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
13 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
14 * Copyright (C) 1996 Paul Mackerras
15 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
17 * Derived from "arch/i386/mm/init.c"
18 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
27 #include <linux/config.h>
28 #include <linux/signal.h>
29 #include <linux/sched.h>
30 #include <linux/kernel.h>
31 #include <linux/errno.h>
32 #include <linux/string.h>
33 #include <linux/types.h>
34 #include <linux/ptrace.h>
35 #include <linux/mman.h>
37 #include <linux/swap.h>
38 #include <linux/stddef.h>
39 #include <linux/vmalloc.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/bootmem.h>
43 #include <linux/highmem.h>
45 #include <asm/pgalloc.h>
48 #include <asm/mmu_context.h>
49 #include <asm/pgtable.h>
51 #include <asm/uaccess.h>
53 #include <asm/bootx.h>
54 #include <asm/machdep.h>
55 #include <asm/setup.h>
58 #include "mem_pieces.h"
60 extern char etext
[], _stext
[];
61 extern struct mem_pieces phys_avail
;
63 /* Used by the 44x TLB replacement exception handler.
64 * Just needed it declared someplace.
66 unsigned int tlb_44x_index
= 0;
67 unsigned int tlb_44x_hwater
= 62;
70 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
73 ppc44x_pin_tlb(int slot
, unsigned int virt
, unsigned int phys
)
75 unsigned long attrib
= 0;
77 __asm__
__volatile__("\
87 : "r" (attrib
), "r" (phys
), "r" (virt
), "r" (slot
),
88 "i" (PPC44x_TLB_VALID
| PPC44x_TLB_256M
),
89 "i" (PPC44x_TLB_SW
| PPC44x_TLB_SR
| PPC44x_TLB_SX
| PPC44x_TLB_G
),
90 "i" (PPC44x_TLB_PAGEID
),
91 "i" (PPC44x_TLB_XLAT
),
92 "i" (PPC44x_TLB_ATTRIB
));
96 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
98 void __init
MMU_init_hw(void)
100 flush_instruction_cache();
103 unsigned long __init
mmu_mapin_ram(void)
105 unsigned int pinned_tlbs
= 1;
109 * If lowmem is not on a pin tlb entry size boundary,
110 * then reserve the last page of system memory. This
111 * eliminates the possibility of a speculative dcache
112 * fetch past the end of system memory that would
113 * result in a machine check exception.
115 if (total_lowmem
| (PPC44x_PIN_SIZE
- 1))
116 mem_pieces_remove(&phys_avail
, total_lowmem
- PAGE_SIZE
, PAGE_SIZE
, 1);
118 /* Determine number of entries necessary to cover lowmem */
119 pinned_tlbs
= (unsigned int)
120 (_ALIGN(total_lowmem
, PPC44x_PIN_SIZE
) >> PPC44x_PIN_SHIFT
);
122 /* Write upper watermark to save location */
123 tlb_44x_hwater
= PPC44x_LOW_SLOT
- pinned_tlbs
;
125 /* If necessary, set additional pinned TLBs */
127 for (i
= (PPC44x_LOW_SLOT
-(pinned_tlbs
-1)); i
< PPC44x_LOW_SLOT
; i
++) {
128 unsigned int phys_addr
= (PPC44x_LOW_SLOT
-i
) * PPC44x_PIN_SIZE
;
129 ppc44x_pin_tlb(i
, phys_addr
+PAGE_OFFSET
, phys_addr
);