2 * arch/ppc/kernel/head_e500.S
4 * Kernel execution entry point code.
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 * Copyright 2004 Freescale Semiconductor, Inc
27 * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the
31 * Free Software Foundation; either version 2 of the License, or (at your
32 * option) any later version.
35 #include <linux/config.h>
36 #include <asm/processor.h>
39 #include <asm/pgtable.h>
40 #include <asm/cputable.h>
41 #include <asm/thread_info.h>
42 #include <asm/ppc_asm.h>
43 #include <asm/offsets.h>
44 #include "head_booke.h"
46 /* As with the other PowerPC ports, it is expected that when code
47 * execution begins here, the following registers contain valid, yet
48 * optional, information:
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
53 * r6 - Start of kernel command line string (e.g. "mem=128")
54 * r7 - End of kernel command line string
61 * Reserve a word at a fixed location to store the address
66 * Save parameters we are passed
73 li r24,0 /* CPU number */
75 /* We try to not make any assumptions about how the boot loader
76 * setup or used the TLBs. We invalidate all mappings from the
77 * boot loader and load a single entry in TLB1[0] to map the
78 * first 16M of kernel memory. Any boot info passed from the
79 * bootloader needs to live in this first 16M.
81 * Requirement on bootloader:
82 * - The page we're executing in needs to reside in TLB1 and
83 * have IPROT=1. If not an invalidate broadcast could
84 * evict the entry we're currently executing in.
86 * r3 = Index of TLB1 were executing in
87 * r4 = Current MSR[IS]
88 * r5 = Index of TLB1 temp mapping
90 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
94 /* 1. Find the index of the entry we're executing in */
95 bl invstr /* Find our address */
96 invstr: mflr r6 /* Make it accessible */
98 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
103 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
105 andis. r7,r7,MAS1_VALID@h
111 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
113 andis. r7,r7,MAS1_VALID@h
119 tlbsx 0,r6 /* Fall through, we had to match */
122 rlwinm r3,r7,16,28,31 /* Extract MAS0(Entry) */
124 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
125 oris r7,r7,MAS1_IPROT@h
129 /* 2. Invalidate all entries except the entry we're executing in */
130 mfspr r9,SPRN_TLB1CFG
132 li r6,0 /* Set Entry counter to 0 */
133 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
134 rlwimi r7,r6,16,12,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
138 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
140 beq skpinv /* Dont update the current execution TLB */
144 skpinv: addi r6,r6,1 /* Increment */
145 cmpw r6,r9 /* Are we done? */
146 bne 1b /* If not, repeat */
148 /* Invalidate TLB0 */
154 /* Invalidate TLB1 */
162 /* 3. Setup a temp mapping and jump to it */
163 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
165 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
166 rlwimi r7,r3,16,12,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
170 /* Just modify the entry ID and EPN for the temp mapping */
171 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
172 rlwimi r7,r5,16,12,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
174 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
176 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
177 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
180 li r7,0 /* temp EPN = 0 */
186 slwi r6,r6,5 /* setup new context with other address space */
187 bl 1f /* Find our address */
195 /* 4. Clear out PIDs & Search info */
202 /* 5. Invalidate mapping we started in */
203 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
204 rlwimi r7,r3,16,12,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
210 /* Invalidate TLB1 */
218 /* 6. Setup KERNELBASE mapping in TLB1[0] */
219 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
221 lis r6,(MAS1_VALID|MAS1_IPROT)@h
222 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
226 ori r6,r6,KERNELBASE@l
229 li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
233 /* 7. Jump to KERNELBASE mapping */
235 bl 1f /* Find our address */
241 rfi /* start execution out of TLB1[0] entry */
243 /* 8. Clear out the temp mapping */
244 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
245 rlwimi r7,r5,16,12,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
250 /* Invalidate TLB1 */
258 /* Establish the interrupt vector offsets */
259 SET_IVOR(0, CriticalInput);
260 SET_IVOR(1, MachineCheck);
261 SET_IVOR(2, DataStorage);
262 SET_IVOR(3, InstructionStorage);
263 SET_IVOR(4, ExternalInput);
264 SET_IVOR(5, Alignment);
265 SET_IVOR(6, Program);
266 SET_IVOR(7, FloatingPointUnavailable);
267 SET_IVOR(8, SystemCall);
268 SET_IVOR(9, AuxillaryProcessorUnavailable);
269 SET_IVOR(10, Decrementer);
270 SET_IVOR(11, FixedIntervalTimer);
271 SET_IVOR(12, WatchdogTimer);
272 SET_IVOR(13, DataTLBError);
273 SET_IVOR(14, InstructionTLBError);
275 SET_IVOR(32, SPEUnavailable);
276 SET_IVOR(33, SPEFloatingPointData);
277 SET_IVOR(34, SPEFloatingPointRound);
278 SET_IVOR(35, PerformanceMonitor);
280 /* Establish the interrupt vector base */
281 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
284 /* Setup the defaults for TLB entries */
285 li r2,MAS4_TSIZED(BOOKE_PAGESZ_4K)
291 oris r2,r2,HID0_DOZE@h
296 * This is where the main kernel code starts.
301 ori r2,r2,init_task@l
303 /* ptr to current thread */
304 addi r4,r2,THREAD /* init task's THREAD */
308 lis r1,init_thread_union@h
309 ori r1,r1,init_thread_union@l
311 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
315 mfspr r3,SPRN_TLB1CFG
317 lis r4,num_tlbcam_entries@ha
318 stw r3,num_tlbcam_entries@l(r4)
320 * Decide what sort of machine this is and initialize the MMU.
330 /* Setup PTE pointers for the Abatron bdiGDB */
331 lis r6, swapper_pg_dir@h
332 ori r6, r6, swapper_pg_dir@l
333 lis r5, abatron_pteptrs@h
334 ori r5, r5, abatron_pteptrs@l
336 ori r4, r4, KERNELBASE@l
337 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
341 lis r4,start_kernel@h
342 ori r4,r4,start_kernel@l
344 ori r3,r3,MSR_KERNEL@l
347 rfi /* change context and jump to start_kernel */
350 * Interrupt vector entry code
352 * The Book E MMUs are always on so we don't need to handle
353 * interrupts in real mode as with previous PPC processors. In
354 * this case we handle interrupts in the kernel virtual address
357 * Interrupt vectors are dynamically placed relative to the
358 * interrupt prefix as determined by the address of interrupt_base.
359 * The interrupt vectors offsets are programmed using the labels
360 * for each interrupt vector entry.
362 * Interrupt vectors must be aligned on a 16 byte boundary.
363 * We align on a 32 byte cache line boundary for good measure.
367 /* Critical Input Interrupt */
368 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
370 /* Machine Check Interrupt */
371 MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
373 /* Data Storage Interrupt */
374 START_EXCEPTION(DataStorage)
375 mtspr SPRG0, r10 /* Save some working registers */
383 * Check if it was a store fault, if not then bail
384 * because a user tried to access a kernel or
385 * read-protected page. Otherwise, get the
386 * offending address and handle it.
389 andis. r10, r10, ESR_ST@h
392 mfspr r10, SPRN_DEAR /* Get faulting address */
394 /* If we are faulting a kernel address, we have to use the
395 * kernel page tables.
398 ori r11, r11, TASK_SIZE@l
402 /* Get the PGD for the current thread */
407 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
408 lwz r11, 0(r11) /* Get L1 entry */
409 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
410 beq 2f /* Bail if no table */
412 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
413 lwz r11, 0(r12) /* Get Linux PTE */
415 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
416 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
417 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
418 bne 2f /* Bail if not */
420 /* Update 'changed'. */
421 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
422 stw r11, 0(r12) /* Update Linux page table */
424 /* MAS2 not updated as the entry does exist in the tlb, this
425 fault taken to detect state transition (eg: COW -> DIRTY)
428 ori r12, r12, _PAGE_HWEXEC | MAS3_RPN@l
430 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
431 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
433 /* update search PID in MAS6, AS = 0 */
438 /* find the TLB index that caused the fault. It has to be here. */
444 /* Done...restore registers and get out of here. */
451 rfi /* Force context change */
455 * The bailout. Restore registers to pre-exception conditions
456 * and call the heavyweights to help us out.
466 /* Instruction Storage Interrupt */
467 START_EXCEPTION(InstructionStorage)
468 NORMAL_EXCEPTION_PROLOG
469 mfspr r5,SPRN_ESR /* Grab the ESR and save it */
471 mr r4,r12 /* Pass SRR0 as arg2 */
472 li r5,0 /* Pass zero as arg3 */
473 EXC_XFER_EE_LITE(0x0400, handle_page_fault)
475 /* External Input Interrupt */
476 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
478 /* Alignment Interrupt */
479 START_EXCEPTION(Alignment)
480 NORMAL_EXCEPTION_PROLOG
481 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
483 addi r3,r1,STACK_FRAME_OVERHEAD
484 EXC_XFER_EE(0x0600, AlignmentException)
486 /* Program Interrupt */
487 START_EXCEPTION(Program)
488 NORMAL_EXCEPTION_PROLOG
489 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
491 addi r3,r1,STACK_FRAME_OVERHEAD
492 EXC_XFER_STD(0x0700, ProgramCheckException)
494 /* Floating Point Unavailable Interrupt */
495 EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
497 /* System Call Interrupt */
498 START_EXCEPTION(SystemCall)
499 NORMAL_EXCEPTION_PROLOG
500 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
502 /* Auxillary Processor Unavailable Interrupt */
503 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
505 /* Decrementer Interrupt */
506 START_EXCEPTION(Decrementer)
507 NORMAL_EXCEPTION_PROLOG
508 lis r0,TSR_DIS@h /* Setup the DEC interrupt mask */
509 mtspr SPRN_TSR,r0 /* Clear the DEC interrupt */
510 addi r3,r1,STACK_FRAME_OVERHEAD
511 EXC_XFER_LITE(0x0900, timer_interrupt)
513 /* Fixed Internal Timer Interrupt */
514 /* TODO: Add FIT support */
515 EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
517 /* Watchdog Timer Interrupt */
518 /* TODO: Add watchdog support */
519 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
521 /* Data TLB Error Interrupt */
522 START_EXCEPTION(DataTLBError)
523 mtspr SPRG0, r10 /* Save some working registers */
529 mfspr r10, SPRN_DEAR /* Get faulting address */
531 /* If we are faulting a kernel address, we have to use the
532 * kernel page tables.
535 ori r11, r11, TASK_SIZE@l
538 lis r11, swapper_pg_dir@h
539 ori r11, r11, swapper_pg_dir@l
541 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
548 /* Get the PGD for the current thread */
554 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
555 lwz r11, 0(r11) /* Get L1 entry */
556 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
557 beq 2f /* Bail if no table */
559 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
560 lwz r11, 0(r12) /* Get Linux PTE */
561 andi. r13, r11, _PAGE_PRESENT
564 ori r11, r11, _PAGE_ACCESSED
567 /* Jump to common tlb load */
570 /* The bailout. Restore registers to pre-exception conditions
571 * and call the heavyweights to help us out.
581 /* Instruction TLB Error Interrupt */
583 * Nearly the same as above, except we get our
584 * information from different registers and bailout
585 * to a different point.
587 START_EXCEPTION(InstructionTLBError)
588 mtspr SPRG0, r10 /* Save some working registers */
594 mfspr r10, SRR0 /* Get faulting address */
596 /* If we are faulting a kernel address, we have to use the
597 * kernel page tables.
600 ori r11, r11, TASK_SIZE@l
603 lis r11, swapper_pg_dir@h
604 ori r11, r11, swapper_pg_dir@l
606 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
613 /* Get the PGD for the current thread */
619 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
620 lwz r11, 0(r11) /* Get L1 entry */
621 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
622 beq 2f /* Bail if no table */
624 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
625 lwz r11, 0(r12) /* Get Linux PTE */
626 andi. r13, r11, _PAGE_PRESENT
629 ori r11, r11, _PAGE_ACCESSED
632 /* Jump to common TLB load point */
636 /* The bailout. Restore registers to pre-exception conditions
637 * and call the heavyweights to help us out.
648 /* SPE Unavailable */
649 START_EXCEPTION(SPEUnavailable)
650 NORMAL_EXCEPTION_PROLOG
652 addi r3,r1,STACK_FRAME_OVERHEAD
653 EXC_XFER_EE_LITE(0x2010, KernelSPE)
655 EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
656 #endif /* CONFIG_SPE */
658 /* SPE Floating Point Data */
660 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
662 EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
663 #endif /* CONFIG_SPE */
665 /* SPE Floating Point Round */
666 EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
668 /* Performance Monitor */
669 EXCEPTION(0x2060, PerformanceMonitor, UnknownException, EXC_XFER_EE)
671 /* Check for a single step debug exception while in an exception
672 * handler before state has been saved. This is to catch the case
673 * where an instruction that we are trying to single step causes
674 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
675 * the exception handler generates a single step debug exception.
677 * If we get a debug trap on the first instruction of an exception handler,
678 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
679 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
680 * The exception handler was handling a non-critical interrupt, so it will
681 * save (and later restore) the MSR via SPRN_SRR1, which will still have
682 * the MSR_DE bit set.
684 /* Debug Interrupt */
685 START_EXCEPTION(Debug)
686 CRITICAL_EXCEPTION_PROLOG
689 * If this is a single step or branch-taken exception in an
690 * exception entry sequence, it was probably meant to apply to
691 * the code where the exception occurred (since exception entry
692 * doesn't turn off DE automatically). We simulate the effect
693 * of turning off DE on entry to an exception handler by turning
694 * off DE in the CSRR1 value and clearing the debug status.
696 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
697 andis. r10,r10,(DBSR_IC|DBSR_BT)@h
699 andi. r0,r9,MSR_PR /* check supervisor */
700 beq 2f /* branch if we need to fix it up... */
702 /* continue normal handling for a critical exception... */
703 1: mfspr r4,SPRN_DBSR
704 addi r3,r1,STACK_FRAME_OVERHEAD
705 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
706 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
707 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
709 /* here it looks like we got an inappropriate debug exception. */
710 2: rlwinm r9,r9,0,~MSR_DE /* clear DE in the CSRR1 value */
711 mtspr SPRN_DBSR,r10 /* clear the IC/BT debug intr status */
712 /* restore state and get out */
721 mtspr SPRG2,r8; /* SPRG2 only used in criticals */
723 lwz r10,crit_r10@l(r8)
724 lwz r11,crit_r11@l(r8)
734 * Data TLB exceptions will bail out to this point
735 * if they can't resolve the lightweight TLB fault.
738 NORMAL_EXCEPTION_PROLOG
739 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
741 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
742 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
744 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
746 addi r3,r1,STACK_FRAME_OVERHEAD
747 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
751 * Both the instruction and data TLB miss get to this
752 * point to load the TLB.
754 * r11 - TLB (info from Linux PTE)
755 * r12, r13 - available to use
756 * CR5 - results of addr < TASK_SIZE
757 * MAS0, MAS1 - loaded with proper value when we get here
758 * MAS2, MAS3 - will need additional info from Linux PTE
759 * Upon exit, we reload everything and RFI.
763 * We set execute, because we don't have the granularity to
764 * properly set this at the page level (Linux problem).
765 * Many of these bits are software only. Bits we don't set
766 * here we (properly should) assume have the appropriate value.
770 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
775 /* addr > TASK_SIZE */
776 li r10, (MAS3_UX | MAS3_UW | MAS3_UR)
777 andi. r13, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
778 andi. r12, r11, _PAGE_USER /* Test for _PAGE_USER */
782 or r12, r12, r10 /* Copy user perms into supervisor */
785 /* addr <= TASK_SIZE */
786 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
787 ori r12, r12, (MAS3_SX | MAS3_SR)
789 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
793 /* Done...restore registers and get out of here. */
800 rfi /* Force context change */
803 /* Note that the SPE support is closely modeled after the AltiVec
804 * support. Changes to one are likely to be applicable to the
808 * Disable SPE for the task which had SPE previously,
809 * and save its SPE registers in its thread_struct.
810 * Enables SPE for use in the kernel on return.
811 * On SMP we know the SPE units are free, since we give it up every
816 mtmsr r5 /* enable use of SPE now */
819 * For SMP, we don't do lazy SPE switching because it just gets too
820 * horrendously complex, especially when a task switches from one CPU
821 * to another. Instead we call giveup_spe in switch_to.
824 lis r3,last_task_used_spe@ha
825 lwz r4,last_task_used_spe@l(r3)
828 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
830 evxor evr10, evr10, evr10 /* clear out evr10 */
831 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
833 evstddx evr10, r4, r5 /* save off accumulator */
835 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
837 andc r4,r4,r10 /* disable SPE for previous task */
838 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
840 #endif /* CONFIG_SMP */
841 /* enable use of SPE after return */
843 mfspr r5,SPRG3 /* current task's THREAD (phys) */
846 stw r4,THREAD_USED_SPE(r5)
852 stw r4,last_task_used_spe@l(r3)
853 #endif /* CONFIG_SMP */
854 /* restore registers and return */
855 2: REST_4GPRS(3, r11)
873 * SPE unavailable trap from kernel - print a message, but let
874 * the task use SPE in the kernel until it returns to user mode.
879 stw r3,_MSR(r1) /* enable use of SPE after return */
882 mr r4,r2 /* current */
886 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
889 #endif /* CONFIG_SPE */
896 * extern void loadcam_entry(unsigned int index)
898 * Load TLBCAM[index] entry in to the L2 CAM MMU
900 _GLOBAL(loadcam_entry)
918 * extern void giveup_altivec(struct task_struct *prev)
920 * The e500 core does not have an AltiVec unit.
922 _GLOBAL(giveup_altivec)
927 * extern void giveup_spe(struct task_struct *prev)
934 mtmsr r5 /* enable use of SPE now */
937 beqlr- /* if no previous owner, done */
938 addi r3,r3,THREAD /* want THREAD of task */
941 SAVE_32EVR(0, r4, r3)
942 evxor evr6, evr6, evr6 /* clear out evr6 */
943 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
945 evstddx evr6, r4, r3 /* save off accumulator */
946 mfspr r6,SPRN_SPEFSCR
947 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
949 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
951 andc r4,r4,r3 /* disable SPE for previous task */
952 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
956 lis r4,last_task_used_spe@ha
957 stw r5,last_task_used_spe@l(r4)
958 #endif /* CONFIG_SMP */
960 #endif /* CONFIG_SPE */
963 * extern void giveup_fpu(struct task_struct *prev)
965 * The e500 core does not have an FPU.
971 * extern void abort(void)
973 * At present, this routine just applies a system reset.
977 mtspr SPRN_DBCR0,r13 /* disable all debug events */
979 ori r13,r13,MSR_DE@l /* Enable Debug Events */
982 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
987 #ifdef CONFIG_BDI_SWITCH
988 /* Context switch the PTE pointer for the Abatron BDI2000.
989 * The PGDIR is the second parameter.
991 lis r5, abatron_pteptrs@h
992 ori r5, r5, abatron_pteptrs@l
996 isync /* Force context change */
1000 * We put a few things here that have to be page-aligned. This stuff
1001 * goes at the beginning of the data segment, which is page-aligned.
1005 _GLOBAL(empty_zero_page)
1007 _GLOBAL(swapper_pg_dir)
1011 /* Stack for handling critical exceptions from kernel mode */
1012 critical_stack_bottom:
1017 /* Stack for handling machine check exceptions from kernel mode */
1018 mcheck_stack_bottom:
1024 * This area is used for temporarily saving registers during the
1025 * critical and machine check exception prologs. It must always
1026 * follow the page aligned allocations, so it starts on a page
1027 * boundary, ensuring that all crit_save areas are in a single
1056 _GLOBAL(mcheck_save)
1062 _GLOBAL(mcheck_sprg0)
1064 _GLOBAL(mcheck_sprg1)
1066 _GLOBAL(mcheck_sprg4)
1068 _GLOBAL(mcheck_sprg5)
1070 _GLOBAL(mcheck_sprg7)
1074 _GLOBAL(mcheck_srr0)
1076 _GLOBAL(mcheck_srr1)
1078 _GLOBAL(mcheck_csrr0)
1080 _GLOBAL(mcheck_csrr1)
1084 * This space gets a copy of optional info passed to us by the bootstrap
1085 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1091 * Room for two PTE pointers, usually the kernel and current user pointers
1092 * to their respective root page table.