arch/mips/sibyte/sb1250/bcm1250_tbprof.c

   1 /*
   2  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #define SBPROF_TB_DEBUG 0
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/fs.h>
  29 #include <linux/errno.h>
  30 #include <linux/reboot.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/io.h>
  33 #include <asm/sibyte/sb1250.h>
  34 #include <asm/sibyte/sb1250_regs.h>
  35 #include <asm/sibyte/sb1250_scd.h>
  36 #include <asm/sibyte/sb1250_int.h>
  37 #include <asm/sibyte/trace_prof.h>
  38
  39 #define DEVNAME "bcm1250_tbprof"
  40
  41 static struct sbprof_tb sbp;
  42
  43 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
  44
  45 /************************************************************************
  46  * Support for ZBbus sampling using the trace buffer
  47  *
  48  * We use the SCD performance counter interrupt, caused by a Zclk counter
  49  * overflow, to trigger the start of tracing.
  50  *
  51  * We set the trace buffer to sample everything and freeze on
  52  * overflow.
  53  *
  54  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
  55  *
  56  ************************************************************************/
  57
  58 static u_int64_t tb_period;
  59
  60 static void arm_tb(void)
  61 {
  62         u_int64_t scdperfcnt;
  63         u_int64_t next = (1ULL << 40) - tb_period;
  64         u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
  65         /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
  66            trigger start of trace.  XXX vary sampling period */
  67         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
  68         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
  69         /* Unfortunately, in Pass 2 we must clear all counters to knock down
  70            a previous interrupt request.  This means that bus profiling
  71            requires ALL of the SCD perf counters. */
  72         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
  73                    M_SPC_CFG_ENABLE |            // enable counting
  74                    M_SPC_CFG_CLEAR |             // clear all counters
  75                    V_SPC_CFG_SRC1(1),            // counter 1 counts cycles
  76               IOADDR(A_SCD_PERF_CNT_CFG));
  77         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
  78         /* Reset the trace buffer */
  79         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
  80 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
  81         /* XXXKW may want to expose control to the data-collector */
  82         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
  83 #endif
  84         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
  85         sbp.tb_armed = 1;
  86 }
  87
  88 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
  89 {
  90         int i;
  91         DBG(printk(DEVNAME ": tb_intr\n"));
  92         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
  93                 /* XXX should use XKPHYS to make writes bypass L2 */
  94                 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
  95                 /* Read out trace */
  96                 __raw_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
  97                 __asm__ __volatile__ ("sync" : : : "memory");
  98                 /* Loop runs backwards because bundles are read out in reverse order */
  99                 for (i = 256 * 6; i > 0; i -= 6) {
 100                         // Subscripts decrease to put bundle in the order
 101                         //   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
 102                         p[i-1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
 103                         p[i-2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
 104                         p[i-3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
 105                         p[i-4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
 106                         p[i-5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
 107                         p[i-6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
 108                 }
 109                 if (!sbp.tb_enable) {
 110                         DBG(printk(DEVNAME ": tb_intr shutdown\n"));
 111                         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 112                         sbp.tb_armed = 0;
 113                         wake_up(&sbp.tb_sync);
 114                 } else {
 115                         arm_tb();       // knock down current interrupt and get another one later
 116                 }
 117         } else {
 118                 /* No more trace buffer samples */
 119                 DBG(printk(DEVNAME ": tb_intr full\n"));
 120                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 121                 sbp.tb_armed = 0;
 122                 if (!sbp.tb_enable) {
 123                         wake_up(&sbp.tb_sync);
 124                 }
 125                 wake_up(&sbp.tb_read);
 126         }
 127         return IRQ_HANDLED;
 128 }
 129
 130 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
 131 {
 132         printk(DEVNAME ": unexpected pc_intr");
 133         return IRQ_NONE;
 134 }
 135
 136 int sbprof_zbprof_start(struct file *filp)
 137 {
 138         u_int64_t scdperfcnt;
 139
 140         if (sbp.tb_enable)
 141                 return -EBUSY;
 142
 143         DBG(printk(DEVNAME ": starting\n"));
 144
 145         sbp.tb_enable = 1;
 146         sbp.next_tb_sample = 0;
 147         filp->f_pos = 0;
 148
 149         if (request_irq
 150             (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
 151                 return -EBUSY;
 152         }
 153         /* Make sure there isn't a perf-cnt interrupt waiting */
 154         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 155         /* Disable and clear counters, override SRC_1 */
 156         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 157                    M_SPC_CFG_ENABLE |
 158                    M_SPC_CFG_CLEAR |
 159                    V_SPC_CFG_SRC1(1),
 160               IOADDR(A_SCD_PERF_CNT_CFG));
 161
 162         /* We grab this interrupt to prevent others from trying to use
 163            it, even though we don't want to service the interrupts
 164            (they only feed into the trace-on-interrupt mechanism) */
 165         if (request_irq
 166             (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 167                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 168                 return -EBUSY;
 169         }
 170
 171         /* I need the core to mask these, but the interrupt mapper to
 172            pass them through.  I am exploiting my knowledge that
 173            cp0_status masks out IP[5]. krw */
 174         __raw_writeq(K_INT_MAP_I3,
 175                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_PERF_CNT<<3)));
 176
 177         /* Initialize address traps */
 178         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 179         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 180         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 181         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 182
 183         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 184         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 185         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 186         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 187
 188         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 189         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 190         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 191         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 192
 193         /* Initialize Trace Event 0-7 */
 194         //                              when interrupt
 195         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 196         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 197         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 198         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 199         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 200         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 201         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 202         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 203
 204         /* Initialize Trace Sequence 0-7 */
 205         //                                   Start on event 0 (interrupt)
 206         __raw_writeq(V_SCD_TRSEQ_FUNC_START|0x0fff,
 207                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 208         //                        dsamp when d used | asamp when a used
 209         __raw_writeq(M_SCD_TRSEQ_ASAMPLE|M_SCD_TRSEQ_DSAMPLE|K_SCD_TRSEQ_TRIGGER_ALL,
 210                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 211         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 212         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 213         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 214         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 215         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 216         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 217
 218         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 219         __raw_writeq((1ULL << K_INT_PERF_CNT), IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 220
 221         arm_tb();
 222
 223         DBG(printk(DEVNAME ": done starting\n"));
 224
 225         return 0;
 226 }
 227
 228 int sbprof_zbprof_stop(void)
 229 {
 230         DBG(printk(DEVNAME ": stopping\n"));
 231
 232         if (sbp.tb_enable) {
 233                 sbp.tb_enable = 0;
 234                 /* XXXKW there is a window here where the intr handler
 235                    may run, see the disable, and do the wake_up before
 236                    this sleep happens. */
 237                 if (sbp.tb_armed) {
 238                         DBG(printk(DEVNAME ": wait for disarm\n"));
 239                         interruptible_sleep_on(&sbp.tb_sync);
 240                         DBG(printk(DEVNAME ": disarm complete\n"));
 241                 }
 242                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 243                 free_irq(K_INT_PERF_CNT, &sbp);
 244         }
 245
 246         DBG(printk(DEVNAME ": done stopping\n"));
 247
 248         return 0;
 249 }
 250
 251 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 252 {
 253         int minor;
 254
 255         minor = iminor(inode);
 256         if (minor != 0) {
 257                 return -ENODEV;
 258         }
 259         if (sbp.open) {
 260                 return -EBUSY;
 261         }
 262
 263         memset(&sbp, 0, sizeof(struct sbprof_tb));
 264         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 265         if (!sbp.sbprof_tbbuf) {
 266                 return -ENOMEM;
 267         }
 268         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 269         init_waitqueue_head(&sbp.tb_sync);
 270         init_waitqueue_head(&sbp.tb_read);
 271         sbp.open = 1;
 272
 273         return 0;
 274 }
 275
 276 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 277 {
 278         int minor;
 279
 280         minor = iminor(inode);
 281         if (minor != 0 || !sbp.open) {
 282                 return -ENODEV;
 283         }
 284
 285         if (sbp.tb_armed || sbp.tb_enable) {
 286                 sbprof_zbprof_stop();
 287         }
 288
 289         vfree(sbp.sbprof_tbbuf);
 290         sbp.open = 0;
 291
 292         return 0;
 293 }
 294
 295 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 296                               size_t size, loff_t *offp)
 297 {
 298         int cur_sample, sample_off, cur_count, sample_left;
 299         char *src;
 300         int   count   =  0;
 301         char *dest    =  buf;
 302         long  cur_off = *offp;
 303
 304         count = 0;
 305         cur_sample = cur_off / TB_SAMPLE_SIZE;
 306         sample_off = cur_off % TB_SAMPLE_SIZE;
 307         sample_left = TB_SAMPLE_SIZE - sample_off;
 308         while (size && (cur_sample < sbp.next_tb_sample)) {
 309                 cur_count = size < sample_left ? size : sample_left;
 310                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 311                 copy_to_user(dest, src, cur_count);
 312                 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
 313                            cur_sample, cur_count));
 314                 size -= cur_count;
 315                 sample_left -= cur_count;
 316                 if (!sample_left) {
 317                         cur_sample++;
 318                         sample_off = 0;
 319                         sample_left = TB_SAMPLE_SIZE;
 320                 } else {
 321                         sample_off += cur_count;
 322                 }
 323                 cur_off += cur_count;
 324                 dest += cur_count;
 325                 count += cur_count;
 326         }
 327         *offp = cur_off;
 328
 329         return count;
 330 }
 331
 332 static int sbprof_tb_ioctl(struct inode *inode,
 333                            struct file *filp,
 334                            unsigned int command,
 335                            unsigned long arg)
 336 {
 337         int error = 0;
 338
 339         switch (command) {
 340         case SBPROF_ZBSTART:
 341                 error = sbprof_zbprof_start(filp);
 342                 break;
 343         case SBPROF_ZBSTOP:
 344                 error = sbprof_zbprof_stop();
 345                 break;
 346         case SBPROF_ZBWAITFULL:
 347                 interruptible_sleep_on(&sbp.tb_read);
 348                 /* XXXKW check if interrupted? */
 349                 return put_user(TB_FULL, (int *) arg);
 350         default:
 351                 error = -EINVAL;
 352                 break;
 353         }
 354
 355         return error;
 356 }
 357
 358 static struct file_operations sbprof_tb_fops = {
 359         .owner          = THIS_MODULE,
 360         .open           = sbprof_tb_open,
 361         .release        = sbprof_tb_release,
 362         .read           = sbprof_tb_read,
 363         .ioctl          = sbprof_tb_ioctl,
 364         .mmap           = NULL,
 365 };
 366
 367 static int __init sbprof_tb_init(void)
 368 {
 369         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 370                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 371                        SBPROF_TB_MAJOR);
 372                 return -EIO;
 373         }
 374         sbp.open = 0;
 375         tb_period = zbbus_mhz * 10000LL;
 376         printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
 377         return 0;
 378 }
 379
 380 static void __exit sbprof_tb_cleanup(void)
 381 {
 382         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 383 }
 384
 385 module_init(sbprof_tb_init);
 386 module_exit(sbprof_tb_cleanup);