2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
7 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <asm/sn/arch.h>
14 #include <asm/pci/bridge.h>
15 #include <asm/pci_channel.h>
16 #include <asm/paccess.h>
17 #include <asm/sn/intr.h>
18 #include <asm/sn/sn0/hub.h>
21 * Max #PCI busses we can handle; ie, max #PCI bridges.
23 #define MAX_PCI_BUSSES 40
26 * Max #PCI devices (like scsi controllers) we handle on a bus.
28 #define MAX_DEVICES_PER_PCIBUS 8
31 * XXX: No kmalloc available when we do our crosstalk scan,
32 * we should try to move it later in the boot process.
34 static struct bridge_controller bridges
[MAX_PCI_BUSSES
];
37 * Translate from irq to software PCI bus number and PCI slot.
39 struct bridge_controller
*irq_to_bridge
[MAX_PCI_BUSSES
* MAX_DEVICES_PER_PCIBUS
];
40 int irq_to_slot
[MAX_PCI_BUSSES
* MAX_DEVICES_PER_PCIBUS
];
43 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
44 * not really documented, so right now I can't write code which uses it.
45 * Therefore we use type 0 accesses for now even though they won't work
46 * correcly for PCI-to-PCI bridges.
48 * The function is complicated by the ultimate brokeness of the IOC3 chip
49 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
50 * accesses and does only decode parts of it's address space.
53 static int pci_conf0_read_config(struct pci_bus
*bus
, unsigned int devfn
,
54 int where
, int size
, u32
* value
)
56 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(bus
);
57 bridge_t
*bridge
= bc
->base
;
58 int slot
= PCI_SLOT(devfn
);
59 int fn
= PCI_FUNC(devfn
);
64 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].c
[PCI_VENDOR_ID
];
65 if (get_dbe(cf
, (u32
*) addr
))
66 return PCIBIOS_DEVICE_NOT_FOUND
;
69 * IOC3 is fucked fucked beyond believe ... Don't even give the
70 * generic PCI code a chance to look at it for real ...
72 if (cf
== (PCI_VENDOR_ID_SGI
| (PCI_DEVICE_ID_SGI_IOC3
<< 16)))
75 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].c
[where
^ (4 - size
)];
78 res
= get_dbe(*value
, (u8
*) addr
);
80 res
= get_dbe(*value
, (u16
*) addr
);
82 res
= get_dbe(*value
, (u32
*) addr
);
84 return PCIBIOS_SUCCESSFUL
;
89 * IOC3 is fucked fucked beyond believe ... Don't even give the
90 * generic PCI code a chance to look at the wrong register.
92 if ((where
>= 0x14 && where
< 0x40) || (where
>= 0x48)) {
94 return PCIBIOS_SUCCESSFUL
;
98 * IOC3 is fucked fucked beyond believe ... Don't try to access
99 * anything but 32-bit words ...
101 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].l
[where
>> 2];
103 if (get_dbe(cf
, (u32
*) addr
))
104 return PCIBIOS_DEVICE_NOT_FOUND
;
106 shift
= ((where
& 3) << 3);
107 mask
= (0xffffffffU
>> ((4 - size
) << 3));
108 *value
= (cf
>> shift
) & mask
;
110 return PCIBIOS_SUCCESSFUL
;
113 static int pci_conf0_write_config(struct pci_bus
*bus
, unsigned int devfn
,
114 int where
, int size
, u32 value
)
116 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(bus
);
117 bridge_t
*bridge
= bc
->base
;
118 int slot
= PCI_SLOT(devfn
);
119 int fn
= PCI_FUNC(devfn
);
121 u32 cf
, shift
, mask
, smask
;
124 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].c
[PCI_VENDOR_ID
];
125 if (get_dbe(cf
, (u32
*) addr
))
126 return PCIBIOS_DEVICE_NOT_FOUND
;
129 * IOC3 is fucked fucked beyond believe ... Don't even give the
130 * generic PCI code a chance to look at it for real ...
132 if (cf
== (PCI_VENDOR_ID_SGI
| (PCI_DEVICE_ID_SGI_IOC3
<< 16)))
135 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].c
[where
^ (4 - size
)];
138 res
= put_dbe(value
, (u8
*) addr
);
139 } else if (size
== 2) {
140 res
= put_dbe(value
, (u16
*) addr
);
142 res
= put_dbe(value
, (u32
*) addr
);
146 return PCIBIOS_DEVICE_NOT_FOUND
;
148 return PCIBIOS_SUCCESSFUL
;
153 * IOC3 is fucked fucked beyond believe ... Don't even give the
154 * generic PCI code a chance to touch the wrong register.
156 if ((where
>= 0x14 && where
< 0x40) || (where
>= 0x48))
157 return PCIBIOS_SUCCESSFUL
;
160 * IOC3 is fucked fucked beyond believe ... Don't try to access
161 * anything but 32-bit words ...
163 addr
= &bridge
->b_type0_cfg_dev
[slot
].f
[fn
].l
[where
>> 2];
165 if (get_dbe(cf
, (u32
*) addr
))
166 return PCIBIOS_DEVICE_NOT_FOUND
;
168 shift
= ((where
& 3) << 3);
169 mask
= (0xffffffffU
>> ((4 - size
) << 3));
170 smask
= mask
<< shift
;
172 cf
= (cf
& ~smask
) | ((value
& mask
) << shift
);
173 if (put_dbe(cf
, (u32
*) addr
))
174 return PCIBIOS_DEVICE_NOT_FOUND
;
176 return PCIBIOS_SUCCESSFUL
;
179 static struct pci_ops bridge_pci_ops
= {
180 .read
= pci_conf0_read_config
,
181 .write
= pci_conf0_write_config
,
184 int __init
bridge_probe(nasid_t nasid
, int widget_id
, int masterwid
)
186 struct bridge_controller
*bc
;
188 static int num_bridges
= 0;
190 printk("a bridge\n");
192 /* XXX: kludge alert.. */
194 ioport_resource
.end
= ~0UL;
196 bc
= &bridges
[num_bridges
++];
198 bc
->pc
.pci_ops
= &bridge_pci_ops
;
199 bc
->pc
.mem_resource
= &bc
->mem
;
200 bc
->pc
.io_resource
= &bc
->io
;
202 bc
->mem
.name
= "Bridge PCI MEM";
203 bc
->pc
.mem_offset
= 0;
206 bc
->mem
.flags
= IORESOURCE_MEM
;
208 bc
->io
.name
= "Bridge IO MEM";
210 bc
->pc
.io_offset
= 0UL;
212 bc
->io
.flags
= IORESOURCE_IO
;
214 bc
->irq_cpu
= smp_processor_id();
215 bc
->widget_id
= widget_id
;
218 bc
->baddr
= (u64
)masterwid
<< 60;
219 bc
->baddr
|= (1UL << 56); /* Barrier set */
222 * point to this bridge
224 bridge
= (bridge_t
*) RAW_NODE_SWIN_BASE(nasid
, widget_id
);
227 * Clear all pending interrupts.
229 bridge
->b_int_rst_stat
= BRIDGE_IRR_ALL_CLR
;
232 * Until otherwise set up, assume all interrupts are from slot 0
234 bridge
->b_int_device
= (u32
) 0x0;
237 * swap pio's to pci mem and io space (big windows)
239 bridge
->b_wid_control
|= BRIDGE_CTRL_IO_SWAP
|
240 BRIDGE_CTRL_MEM_SWAP
;
243 * Hmm... IRIX sets additional bits in the address which
244 * are documented as reserved in the bridge docs.
246 bridge
->b_wid_int_upper
= 0x8000 | (masterwid
<< 16);
247 bridge
->b_wid_int_lower
= 0x01800090; /* PI_INT_PEND_MOD off*/
248 bridge
->b_dir_map
= (masterwid
<< 20); /* DMA */
249 bridge
->b_int_enable
= 0;
251 bridge
->b_wid_tflush
; /* wait until Bridge PIO complete */
255 register_pci_controller(&bc
->pc
);
260 * All observed requests have pin == 1. We could have a global here, that
261 * gets incremented and returned every time - unfortunately, pci_map_irq
262 * may be called on the same device over and over, and need to return the
263 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
265 * A given PCI device, in general, should be able to intr any of the cpus
266 * on any one of the hubs connected to its xbow.
268 int __devinit
pcibios_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
270 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(dev
->bus
);
273 irq
= allocate_irqno();
276 * Argh... This API doesn't handle with errors at all ...
279 printk(KERN_ERR
"Can't allocate interrupt for PCI device %s\n",
284 irq_to_bridge
[irq
] = bc
;
285 irq_to_slot
[irq
] = slot
;
291 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
292 * to find the slot number in sense of the bridge device register.
293 * XXX This also means multiple devices might rely on conflicting bridge
297 static void __init
pci_disable_swapping(struct pci_dev
*dev
)
299 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(dev
->bus
);
300 bridge_t
*bridge
= bc
->base
;
301 int slot
= PCI_SLOT(dev
->devfn
);
303 /* Turn off byte swapping */
304 bridge
->b_device
[slot
].reg
&= ~BRIDGE_DEV_SWAP_DIR
;
305 bridge
->b_widget
.w_tflush
; /* Flush */
308 static void __init
pci_enable_swapping(struct pci_dev
*dev
)
310 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(dev
->bus
);
311 bridge_t
*bridge
= bc
->base
;
312 int slot
= PCI_SLOT(dev
->devfn
);
314 /* Turn on byte swapping */
315 bridge
->b_device
[slot
].reg
|= BRIDGE_DEV_SWAP_DIR
;
316 bridge
->b_widget
.w_tflush
; /* Flush */
319 static void __init
pci_fixup_ioc3(struct pci_dev
*d
)
321 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(d
->bus
);
322 unsigned long offset
= NODE_OFFSET(bc
->nasid
);
324 printk("PCI: Fixing base addresses for IOC3 device %s\n", pci_name(d
));
326 d
->resource
[0].start
|= offset
;
327 d
->resource
[0].end
|= offset
;
329 pci_disable_swapping(d
);
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
335 static void __init
pci_fixup_isp1020(struct pci_dev
*d
)
337 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(d
->bus
);
338 unsigned short command
;
340 d
->resource
[0].start
|= (unsigned long) bc
->nasid
<< 32;
341 printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", pci_name(d
));
344 * Configure device to allow bus mastering, i/o and memory mapping.
345 * Older qlogicisp driver expects to have the IO space enable
346 * bit set. Things stop working if we program the controllers as not
347 * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags.
350 pci_read_config_word(d
, PCI_COMMAND
, &command
);
351 command
|= PCI_COMMAND_MEMORY
;
352 command
|= PCI_COMMAND_IO
;
353 pci_write_config_word(d
, PCI_COMMAND
, command
);
354 d
->resource
[1].flags
|= 1;
356 pci_enable_swapping(d
);
359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP1020
,
362 static void __init
pci_fixup_isp2x00(struct pci_dev
*d
)
364 struct bridge_controller
*bc
= BRIDGE_CONTROLLER(d
->bus
);
365 bridge_t
*bridge
= bc
->base
;
368 int slot
= PCI_SLOT(d
->devfn
);
370 unsigned short command
;
372 printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", pci_name(d
));
374 /* set the resource struct for this device */
375 start
= (u32
) (u64
) bridge
; /* yes, we want to lose the upper 32 bits here */
376 start
|= BRIDGE_DEVIO(slot
);
378 d
->resource
[0].start
= start
;
379 d
->resource
[0].end
= d
->resource
[0].start
+ 0xff;
380 d
->resource
[0].flags
= IORESOURCE_IO
;
382 d
->resource
[1].start
= start
;
383 d
->resource
[1].end
= d
->resource
[0].start
+ 0xfff;
384 d
->resource
[1].flags
= IORESOURCE_MEM
;
387 * set the bridge device(x) reg for this device
389 devreg
= bridge
->b_device
[slot
].reg
;
390 /* point device(x) to it appropriate small window */
391 devreg
&= ~BRIDGE_DEV_OFF_MASK
;
392 devreg
|= (start
>> 20) & BRIDGE_DEV_OFF_MASK
;
393 bridge
->b_device
[slot
].reg
= devreg
;
395 pci_enable_swapping(d
);
397 /* set card's base addr reg */
398 //pci_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001);
399 //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000);
400 //pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000);
402 /* I got these from booting irix on system... */
403 pci_write_config_dword(d
, PCI_BASE_ADDRESS_0
, 0x200001);
404 //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000);
405 pci_write_config_dword(d
, PCI_ROM_ADDRESS
, 0x10200000);
407 pci_write_config_dword(d
, PCI_BASE_ADDRESS_1
, start
);
408 //pci_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000));
410 /* set cache line size */
411 pci_write_config_dword(d
, PCI_CACHE_LINE_SIZE
, 0xf080);
413 /* set pci bus timeout */
414 bridge
->b_bus_timeout
|= BRIDGE_BUS_PCI_RETRY_HLD(0x3);
415 bridge
->b_wid_tflush
;
416 printk("PCI: bridge bus timeout= 0x%x \n", bridge
->b_bus_timeout
);
418 /* set host error field */
419 bridge
->b_int_host_err
= 0x44;
420 bridge
->b_wid_tflush
;
422 bridge
->b_wid_tflush
; /* wait until Bridge PIO complete */
423 for (i
= 0; i
< 8; i
++)
424 printk("PCI: device(%d)= 0x%x\n", i
,
425 bridge
->b_device
[i
].reg
);
427 /* configure device to allow bus mastering, i/o and memory mapping */
429 pci_read_config_word(d
, PCI_COMMAND
, &command
);
430 command
|= PCI_COMMAND_MEMORY
;
431 command
|= PCI_COMMAND_IO
;
432 pci_write_config_word(d
, PCI_COMMAND
, command
);
433 /*d->resource[1].flags |= 1; */
436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP2100
,
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP2200
,