arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47
  48 #include <asm/addrspace.h>
  49 #include <asm/time.h>
  50 #include <asm/bcache.h>
  51 #include <asm/irq.h>
  52 #include <asm/reboot.h>
  53 #include <asm/gdb-stub.h>
  54 #include <asm/jmr3927/jmr3927.h>
  55 #include <asm/mipsregs.h>
  56 #include <asm/traps.h>
  57
  58 /* Tick Timer divider */
  59 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  60 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  61
  62 unsigned char led_state = 0xf;
  63
  64 struct {
  65     struct resource ram0;
  66     struct resource ram1;
  67     struct resource pcimem;
  68     struct resource iob;
  69     struct resource ioc;
  70     struct resource pciio;
  71     struct resource jmy1394;
  72     struct resource rom1;
  73     struct resource rom0;
  74     struct resource sio0;
  75     struct resource sio1;
  76 } jmr3927_resources = {
  77     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  78     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  79     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  80     { "IOB",           0x10000000, 0x13FFFFFF                  },
  81     { "IOC",           0x14000000, 0x14FFFFFF                  },
  82     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  83     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  84     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  85     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  86     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  87     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  88 };
  89
  90 /* don't enable - see errata */
  91 int jmr3927_ccfg_toeon = 0;
  92
  93 static inline void do_reset(void)
  94 {
  95 #ifdef CONFIG_TC35815
  96         extern void tc35815_killall(void);
  97         tc35815_killall();
  98 #endif
  99 #if 1   /* Resetting PCI bus */
 100         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 101         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 102         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 103         mdelay(1);
 104         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 105 #endif
 106         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 107 }
 108
 109 static void jmr3927_machine_restart(char *command)
 110 {
 111         cli();
 112         puts("Rebooting...");
 113         do_reset();
 114 }
 115
 116 static void jmr3927_machine_halt(void)
 117 {
 118         puts("JMR-TX3927 halted.\n");
 119         while (1);
 120 }
 121
 122 static void jmr3927_machine_power_off(void)
 123 {
 124         puts("JMR-TX3927 halted. Please turn off the power.\n");
 125         while (1);
 126 }
 127
 128 #define USE_RTC_DS1742
 129 #ifdef USE_RTC_DS1742
 130 extern void rtc_ds1742_init(unsigned long base);
 131 #endif
 132 static void __init jmr3927_time_init(void)
 133 {
 134 #ifdef USE_RTC_DS1742
 135         if (jmr3927_have_nvram()) {
 136                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 137         }
 138 #endif
 139 }
 140
 141 unsigned long jmr3927_do_gettimeoffset(void);
 142 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 143
 144 static void __init jmr3927_timer_setup(struct irqaction *irq)
 145 {
 146         do_gettimeoffset = jmr3927_do_gettimeoffset;
 147
 148         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 149         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 150         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 151         jmr3927_tmrptr->tcr =
 152                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 153
 154         setup_irq(JMR3927_IRQ_TICK, irq);
 155 }
 156
 157 #define USECS_PER_JIFFY (1000000/HZ)
 158
 159 unsigned long jmr3927_do_gettimeoffset(void)
 160 {
 161        unsigned long count;
 162        unsigned long res = 0;
 163
 164        /* MUST read TRR before TISR. */
 165        count = jmr3927_tmrptr->trr;
 166
 167        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 168                /* timer interrupt is pending.  use Max value. */
 169                res = USECS_PER_JIFFY - 1;
 170        } else {
 171                /* convert to usec */
 172                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 173                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 174
 175                /*
 176                 * Due to possible jiffies inconsistencies, we need to check
 177                 * the result so that we'll get a timer that is monotonic.
 178                 */
 179                if (res >= USECS_PER_JIFFY)
 180                        res = USECS_PER_JIFFY-1;
 181        }
 182
 183        return res;
 184 }
 185
 186
 187 #if defined(CONFIG_BLK_DEV_INITRD)
 188 extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
 189 #endif
 190
 191 //#undef DO_WRITE_THROUGH
 192 #define DO_WRITE_THROUGH
 193 #define DO_ENABLE_CACHE
 194
 195 extern char * __init prom_getcmdline(void);
 196 static void jmr3927_board_init(void);
 197 extern void jmr3927_irq_setup(void);
 198 extern struct resource pci_io_resource;
 199 extern struct resource pci_mem_resource;
 200
 201 static void __init jmr3927_setup(void)
 202 {
 203         extern int panic_timeout;
 204         char *argptr;
 205
 206         irq_setup = jmr3927_irq_setup;
 207         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 208
 209         board_time_init = jmr3927_time_init;
 210         board_timer_setup = jmr3927_timer_setup;
 211
 212         _machine_restart = jmr3927_machine_restart;
 213         _machine_halt = jmr3927_machine_halt;
 214         _machine_power_off = jmr3927_machine_power_off;
 215
 216         /*
 217          * IO/MEM resources.
 218          */
 219         ioport_resource.start = pci_io_resource.start;
 220         ioport_resource.end = pci_io_resource.end;
 221         iomem_resource.start = pci_mem_resource.start;
 222         iomem_resource.end = pci_mem_resource.end;
 223
 224         /* Reboot on panic */
 225         panic_timeout = 180;
 226
 227         {
 228                 unsigned int conf;
 229                 conf = read_c0_conf();
 230         }
 231
 232 #if 1
 233         /* cache setup */
 234         {
 235                 unsigned int conf;
 236 #ifdef DO_ENABLE_CACHE
 237                 int mips_ic_disable = 0, mips_dc_disable = 0;
 238 #else
 239                 int mips_ic_disable = 1, mips_dc_disable = 1;
 240 #endif
 241 #ifdef DO_WRITE_THROUGH
 242                 int mips_config_cwfon = 0;
 243                 int mips_config_wbon = 0;
 244 #else
 245                 int mips_config_cwfon = 1;
 246                 int mips_config_wbon = 1;
 247 #endif
 248
 249                 conf = read_c0_conf();
 250                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 251                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 252                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 253                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 254                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 255
 256                 write_c0_conf(conf);
 257                 write_c0_cache(0);
 258         }
 259 #endif
 260
 261         /* initialize board */
 262         jmr3927_board_init();
 263
 264         argptr = prom_getcmdline();
 265
 266         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 267                         jmr3927_ccfg_toeon = 1;
 268         }
 269         argptr = prom_getcmdline();
 270         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 271                 argptr = prom_getcmdline();
 272                 strcat(argptr, " ip=bootp");
 273         }
 274
 275 #ifdef CONFIG_TXX927_SERIAL_CONSOLE
 276         argptr = prom_getcmdline();
 277         if ((argptr = strstr(argptr, "console=")) == NULL) {
 278                 argptr = prom_getcmdline();
 279                 strcat(argptr, " console=ttyS1,115200");
 280         }
 281 #endif
 282 }
 283
 284 early_initcall(jmr3927_setup);
 285
 286
 287 static void tx3927_setup(void);
 288
 289 #ifdef CONFIG_PCI
 290 unsigned long mips_pci_io_base;
 291 unsigned long mips_pci_io_size;
 292 unsigned long mips_pci_mem_base;
 293 unsigned long mips_pci_mem_size;
 294 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 295 unsigned long mips_pci_io_pciaddr = 0;
 296 #endif
 297
 298 static void __init jmr3927_board_init(void)
 299 {
 300         char *argptr;
 301
 302 #ifdef CONFIG_PCI
 303         mips_pci_io_base = JMR3927_PCIIO;
 304         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 305         mips_pci_mem_base = JMR3927_PCIMEM;
 306         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 307 #endif
 308
 309         tx3927_setup();
 310
 311         if (jmr3927_have_isac()) {
 312
 313 #ifdef CONFIG_FB_E1355
 314                 argptr = prom_getcmdline();
 315                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 316                         argptr = prom_getcmdline();
 317                         strcat(argptr, " video=e1355fb:crt16h");
 318                 }
 319 #endif
 320
 321 #ifdef CONFIG_BLK_DEV_IDE
 322                 /* overrides PCI-IDE */
 323 #endif
 324         }
 325
 326         /* SIO0 DTR on */
 327         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 328
 329         jmr3927_led_set(0);
 330
 331
 332         if (jmr3927_have_isac())
 333                 jmr3927_io_led_set(0);
 334         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 335                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 336                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 337                jmr3927_dipsw1(), jmr3927_dipsw2(),
 338                jmr3927_dipsw3(), jmr3927_dipsw4());
 339         if (jmr3927_have_isac())
 340                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 341                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 342                        jmr3927_io_dipsw());
 343 }
 344
 345 static void __init tx3927_setup(void)
 346 {
 347         int i;
 348
 349         /* SDRAMC are configured by PROM */
 350
 351         /* ROMC */
 352         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 353         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 354         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 355         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 356
 357         /* CCFG */
 358         /* enable Timeout BusError */
 359         if (jmr3927_ccfg_toeon)
 360                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 361
 362         /* clear BusErrorOnWrite flag */
 363         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 364         /* Disable PCI snoop */
 365         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 366
 367 #ifdef DO_WRITE_THROUGH
 368         /* Enable PCI SNOOP - with write through only */
 369         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 370 #endif
 371
 372         /* Pin selection */
 373         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 374         tx3927_ccfgptr->pcfg |=
 375                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 376                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 377
 378         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 379                tx3927_ccfgptr->crir,
 380                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 381
 382         /* IRC */
 383         /* disable interrupt control */
 384         tx3927_ircptr->cer = 0;
 385         /* mask all IRC interrupts */
 386         tx3927_ircptr->imr = 0;
 387         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 388                 tx3927_ircptr->ilr[i] = 0;
 389         }
 390         /* setup IRC interrupt mode (Low Active) */
 391         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 392                 tx3927_ircptr->cr[i] = 0;
 393         }
 394
 395         /* TMR */
 396         /* disable all timers */
 397         for (i = 0; i < TX3927_NR_TMR; i++) {
 398                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 399                 tx3927_tmrptr(i)->tisr = 0;
 400                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 401                 tx3927_tmrptr(i)->itmr = 0;
 402                 tx3927_tmrptr(i)->ccdr = 0;
 403                 tx3927_tmrptr(i)->pgmr = 0;
 404         }
 405
 406         /* DMA */
 407         tx3927_dmaptr->mcr = 0;
 408         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 409                 /* reset channel */
 410                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 411                 tx3927_dmaptr->ch[i].ccr = 0;
 412         }
 413         /* enable DMA */
 414 #ifdef __BIG_ENDIAN
 415         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 416 #else
 417         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 418 #endif
 419
 420 #ifdef CONFIG_PCI
 421         /* PCIC */
 422         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 423                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 424                tx3927_pcicptr->rid);
 425         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 426                 printk("External\n");
 427                 /* XXX */
 428         } else {
 429                 printk("Internal\n");
 430
 431                 /* Reset PCI Bus */
 432                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 433                 udelay(100);
 434                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 435                                     JMR3927_IOC_RESET_ADDR);
 436                 udelay(100);
 437                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 438
 439
 440                 /* Disable External PCI Config. Access */
 441                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 442 #ifdef __BIG_ENDIAN
 443                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 444                         TX3927_PCIC_LBC_TIBSE |
 445                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 446 #endif
 447                 /* LB->PCI mappings */
 448                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 449                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 450                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 451                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 452                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 453                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 454                 /* PCI->LB mappings */
 455                 tx3927_pcicptr->iobas = 0xffffffff;
 456                 tx3927_pcicptr->ioba = 0;
 457                 tx3927_pcicptr->tlbioma = 0;
 458                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 459                 tx3927_pcicptr->mba = 0;
 460                 tx3927_pcicptr->tlbmma = 0;
 461 #ifndef JMR3927_INIT_INDIRECT_PCI
 462                 /* Enable Direct mapping Address Space Decoder */
 463                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 464 #endif
 465
 466                 /* Clear All Local Bus Status */
 467                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 468                 /* Enable All Local Bus Interrupts */
 469                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 470                 /* Clear All PCI Status Error */
 471                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 472                 /* Enable All PCI Status Error Interrupts */
 473                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 474
 475                 /* PCIC Int => IRC IRQ10 */
 476                 tx3927_pcicptr->il = TX3927_IR_PCI;
 477 #if 1
 478                 /* Target Control (per errata) */
 479                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 480 #endif
 481
 482                 /* Enable Bus Arbiter */
 483 #if 0
 484                 tx3927_pcicptr->req_trace = 0x73737373;
 485 #endif
 486                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 487
 488                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 489                         PCI_COMMAND_MEMORY |
 490 #if 1
 491                         PCI_COMMAND_IO |
 492 #endif
 493                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 494         }
 495 #endif /* CONFIG_PCI */
 496
 497         /* PIO */
 498         /* PIO[15:12] connected to LEDs */
 499         tx3927_pioptr->dir = 0x0000f000;
 500         tx3927_pioptr->maskcpu = 0;
 501         tx3927_pioptr->maskext = 0;
 502         {
 503                 unsigned int conf;
 504
 505         conf = read_c0_conf();
 506                if (!(conf & TX39_CONF_ICE))
 507                        printk("TX3927 I-Cache disabled.\n");
 508                if (!(conf & TX39_CONF_DCE))
 509                        printk("TX3927 D-Cache disabled.\n");
 510                else if (!(conf & TX39_CONF_WBON))
 511                        printk("TX3927 D-Cache WriteThrough.\n");
 512                else if (!(conf & TX39_CONF_CWFON))
 513                        printk("TX3927 D-Cache WriteBack.\n");
 514                else
 515                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 516         }
 517 }