1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5206e ColdFire based eLITE boards.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
7 * Copyright (C) 1999 Rob Scott (rscott@mtrob.fdns.net)
9 * 1999/02/24 Modified for the 5307 processor David W. Miller
12 /*****************************************************************************/
14 #include "linux/autoconf.h"
15 #include "asm/coldfire.h"
16 #include "asm/mcfsim.h"
18 /*****************************************************************************/
21 * M5206eLITE ColdFire eval board, chip select and memory setup.
25 #define MEM_BASE 0x30000000 /* Base memory for M5206eLITE */
26 #define MEM_RESERVED 0x00020000 /* Don't use memory reserved by dBUG */
27 #define MEM_SIZE 0x00100000 /* 1 MB of SRAM on M5206eLITE */
29 #define MEM_BASE 0x00000000 /* Base memory for M5206eLITE */
30 #define MEM_RESERVED 0x00010000 /* Skip first MEM_LUMP for colilo */
31 #define MEM_SIZE 0x02000000 /* Max DRAM 32Mb */
33 #define MEM_MIN MEM_BASE+MEM_RESERVED
34 /* Define end of probeable memory space */
35 #define MEM_MAX MEM_BASE+MEM_SIZE
36 #define MEM_BUILTIN 0x20000000 /* Put built in SRAM at dBUG loc */
37 #define MEM_TMPSTACK MEM_BUILTIN+0x800 /* Use built in SRAM for tmp stack */
38 #define MEM_LUMP 0x00010000 /* 64 Kb chunks */
39 #define VBR_BASE MEM_BUILTIN /* Use built in SRAM for vectors */
41 #define CS0_ADDR 0x0000ffe0 /* CS0 connected to Flash ROM */
42 #define CS0_MASK 0x000f0000 /* is 1Mbyte */
43 #define CS0_CTRL 0x00001da3 /* read-write (for flash) */
44 #define CS1_ADDR 0x00000000 /* CS1 not connected */
45 #define CS1_MASK 0x00000000
46 #define CS1_CTRL 0x00000000
47 #define CS2_ADDR 0x00003000 /* CS2 connected to SRAM */
48 #define CS2_MASK 0x000f0000 /* is 1Mbyte */
49 #define CS2_CTRL 0x00001903 /* read-write */
50 #define CS3_ADDR 0x00004000 /* CS3 connected to LED, par port */
51 #define CS3_MASK 0x000f0000 /* is 1Mbyte */
52 #define CS3_CTRL 0x00000183 /* read-write */
53 #define CS4_ADDR 0x00000000 /* CS4 not connected */
54 #define CS4_MASK 0x00000000
55 #define CS4_CTRL 0x00000000
56 #define CS5_ADDR 0x00000000 /* CS5 not connected */
57 #define CS5_MASK 0x00000000
58 #define CS5_CTRL 0x00000000
59 #define CS6_ADDR 0x00000000 /* CS6 not connected */
60 #define CS6_MASK 0x00000000
61 #define CS6_CTRL 0x00000000
62 #define CS7_ADDR 0x00000000 /* CS7 not connected */
63 #define CS7_MASK 0x00000000
64 #define CS7_CTRL 0x00000000
65 #define DMC_CTRL 0x00000000 /* default memory control */
67 #define DCRR 0x00000034 /* Refresh period */
69 <15>: DAEM, 1 = Drive Multiplexed Address During External Master DRAM xfer
70 <14>: EDO, 1 = EDO, 0 = Normal
71 <12>: RCD, 1 = 2 clk RAS-to-CAS, 0 = 1.0 clk RAS-to-CAS
72 <10:09>: RSH, 10 = 3.5 clk RAS low, 01 = 2.5 clk, 00 = 1.5 clk
73 <06:05>: RP, 10 = 3.5 clk RAS Precharge, 01 = 2.5 clk, 00 = 1.5 clk
74 <03>: CAS, 1 = 2.5 clk CAS assertion, 0 = 1.5 clk
75 <01>: CP, 1 = 1.5 CAS clk precharge, 0 = .5 clk
76 <00>: CSR, 1 = 2.0 clk CAS before RAS setup, 0 = 1.0 clk
78 #define DCTR 0x0000144B /* Slow DRAM */
79 #define DCAR0 0x00000000 /* DRAM0 address, 0 base addr */
80 #define DCMR0 0x003e0000 /* DRAM0 mask, 4Mb DRAM */
81 #define DCCR0 0x00000007 /* DRAM0 control, R/W, burst pg mde */
82 #define DCAR1 0x00000000 /* DRAM1 address, 0 base addr */
83 #define DCMR1 0x00000000 /* DRAM1 mask, no DRAM */
84 #define DCCR1 0x00000000 /* DRAM1 control, off */
86 /*****************************************************************************/
94 /*****************************************************************************/
99 * Set up the usable of RAM stuff. Size of RAM is determined then
100 * an initial stack set up at the end.
111 /*****************************************************************************/
116 * This is the codes first entry point. This is where it all
122 move.w #0x2700, %sr /* No interrupts */
124 move.l #MCF_MBAR+1, %a0 /* Set I/O base addr */
125 movec %a0, %MBAR /* Note: bit 0 is Validate */
126 move.l #MEM_BUILTIN+1,%a0 /* Set SRAM base addr */
127 movec %a0, %RAMBAR0 /* Note: bit 0 is Validate */
129 move.l #MCF_MBAR, %a0 /* Get I/O base addr */
131 /* ----------------------- CS1 ----------------------- */
132 move.w #CS1_ADDR, %d0 /* CS1 address */
133 move.w %d0, MCFSIM_CSAR1(%a0) /* CS1 address */
134 move.l #CS1_MASK, %d0 /* CS1 mask */
135 move.l %d0, MCFSIM_CSMR1(%a0) /* CS1 mask */
136 move.w #CS1_CTRL, %d0 /* CS1 control */
137 move.w %d0, MCFSIM_CSCR1(%a0) /* CS1 control */
139 /* ----------------------- CS2 ----------------------- */
140 move.w #CS2_ADDR, %d0 /* CS2 address */
141 move.w %d0, MCFSIM_CSAR2(%a0) /* CS2 address */
142 move.l #CS2_MASK, %d0 /* CS2 mask */
143 move.l %d0, MCFSIM_CSMR2(%a0) /* CS2 mask */
144 move.w #CS2_CTRL, %d0 /* CS2 control */
145 move.w %d0, MCFSIM_CSCR2(%a0) /* CS2 control */
147 /* ----------------------- CS3 ----------------------- */
148 move.w #CS3_ADDR, %d0 /* CS3 address */
149 move.w %d0, MCFSIM_CSAR3(%a0) /* CS3 address */
150 move.l #CS3_MASK, %d0 /* CS3 mask */
151 move.l %d0, MCFSIM_CSMR3(%a0) /* CS3 mask */
152 move.w #CS3_CTRL, %d0 /* CS3 control */
153 move.w %d0, MCFSIM_CSCR3(%a0) /* CS3 control */
155 /* ----------------------- CS4 ----------------------- */
156 move.w #CS4_ADDR, %d0 /* CS4 address */
157 move.w %d0, MCFSIM_CSAR4(%a0) /* CS4 address */
158 move.l #CS4_MASK, %d0 /* CS4 mask */
159 move.l %d0, MCFSIM_CSMR4(%a0) /* CS4 mask */
160 move.w #CS4_CTRL, %d0 /* CS4 control */
161 move.w %d0, MCFSIM_CSCR4(%a0) /* CS4 control */
163 /* ----------------------- CS5 ----------------------- */
164 move.w #CS5_ADDR, %d0 /* CS5 address */
165 move.w %d0, MCFSIM_CSAR5(%a0) /* CS5 address */
166 move.l #CS5_MASK, %d0 /* CS5 mask */
167 move.l %d0, MCFSIM_CSMR5(%a0) /* CS5 mask */
168 move.w #CS5_CTRL, %d0 /* CS5 control */
169 move.w %d0, MCFSIM_CSCR5(%a0) /* CS5 control */
171 /* ----------------------- CS6 ----------------------- */
172 move.w #CS6_ADDR, %d0 /* CS6 address */
173 move.w %d0, MCFSIM_CSAR6(%a0) /* CS6 address */
174 move.l #CS6_MASK, %d0 /* CS6 mask */
175 move.l %d0, MCFSIM_CSMR6(%a0) /* CS6 mask */
176 move.w #CS6_CTRL, %d0 /* CS6 control */
177 move.w %d0, MCFSIM_CSCR6(%a0) /* CS6 control */
179 /* ----------------------- CS7 ----------------------- */
180 move.w #CS7_ADDR, %d0 /* CS7 address */
181 move.w %d0, MCFSIM_CSAR7(%a0) /* CS7 address */
182 move.l #CS7_MASK, %d0 /* CS7 mask */
183 move.l %d0, MCFSIM_CSMR7(%a0) /* CS7 mask */
184 move.w #CS7_CTRL, %d0 /* CS7 control */
185 move.w %d0, MCFSIM_CSCR7(%a0) /* CS7 control */
187 /* --------------------- Default --------------------- */
188 move.w #DMC_CTRL, %d0 /* Default control */
189 move.w %d0, MCFSIM_DMCR(%a0) /* Default control */
191 /* ----------------------- DRAM ------------------------ */
192 move.w #DCRR, %d0 /* Refresh period */
193 move.w %d0, MCFSIM_DCRR(%a0) /* Refresh period */
194 move.w #DCTR, %d0 /* Timing address */
195 move.w %d0, MCFSIM_DCTR(%a0) /* Timing address */
196 move.w #DCAR0, %d0 /* DRAM0 base address */
197 move.w %d0, MCFSIM_DCAR0(%a0) /* DRAM0 base address */
198 move.l #DCMR0, %d0 /* DRAM0 mask */
199 move.l %d0, MCFSIM_DCMR0(%a0) /* DRAM0 mask */
200 move.b #DCCR0, %d0 /* DRAM0 control */
201 move.b %d0, MCFSIM_DCCR0(%a0) /* DRAM0 control */
202 move.w #DCAR1, %d0 /* DRAM1 base address */
203 move.w %d0, MCFSIM_DCAR1(%a0) /* DRAM1 base address */
204 move.l #DCMR1, %d0 /* DRAM1 mask */
205 move.l %d0, MCFSIM_DCMR1(%a0) /* DRAM1 mask */
206 move.b #DCCR1, %d0 /* DRAM1 control */
207 move.b %d0, MCFSIM_DCCR1(%a0) /* DRAM1 control */
210 * ChipSelect 0 - ROM cs
212 * ChipSelect 0 is the global chip select coming out of system reset.
213 * CS0 is asserted for every access until CSMR0 is written. Therefore,
214 * the entire ChipSelect must be properly set prior to asserting
217 move.w #CS0_ADDR, %d0 /* CS0 address */
218 move.w %d0, MCFSIM_CSAR0(%a0) /* CS0 address */
219 move.l #CS0_MASK, %d0 /* CS0 mask */
220 move.l %d0, MCFSIM_CSMR0(%a0) /* CS0 mask */
221 move.w #CS0_CTRL, %d0 /* CS0 control */
222 move.w %d0, MCFSIM_CSCR0(%a0) /* CS0 control */
226 * Setup VBR here, otherwise buserror remap will not work.
227 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
229 * bkr@cut.de 19990306
231 * Note: this is because dBUG points VBR to ROM, making vectors read
232 * only, so the bus trap can't be changed. (RS)
234 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
236 move.l %a7, _ramvec /* Set up vector addr */
237 move.l %a7, _rambase /* Set up base RAM addr */
241 * Determine size of RAM, then set up initial stack
242 * Done differently for different eval boards and cpus.
245 #if defined(CONFIG_SMALL)
247 * Set to SRAM size when configuring a minimal system
253 * On the Arnewsh 5206 board and the Motorola m5206eLITE board
254 * we can probe for the amount of DRAM present...
256 move.l #MEM_MIN, %a0 /* Start at bottom */
257 move.l #MEM_MAX, %a1 /* Set stop point */
258 lea.l MEM_TMPSTACK, %sp /* Set up tmp stack ptr */
260 move.l #VBR_BASE+8, %a2 /* Address of bus trap */
261 lea.l _ram_buserr, %a3 /* Get RAM trap address */
262 move.l %a3, (%a2) /* Set trap to local ptr */
265 move.l (%a0), %d0 /* Attempt read */
266 add.l #MEM_LUMP, %a0 /* Try next bank */
267 cmp.l %a1, %a0 /* Check more? */
271 * BUS error trap handler - used for RAM probing.
276 _found_ram: /* Vectored here on bus err */
279 move.l %a0, %d0 /* Mem end addr is in a0 */
280 move.l %d0, %sp /* Set up initial stack ptr */
281 move.l %d0, _ramend /* Set end ram addr */
285 * Enable CPU internal cache.
287 move.l #0x01000000, %d0 /* Invalidate cache cmd */
288 movec %d0, %CACR /* Invalidate cache */
289 move.l #0x80000100, %d0 /* Setup cache mask */
290 movec %d0, %CACR /* Enable cache */
293 #ifdef CONFIG_ROMFS_FS
295 * Move ROM filesystem above bss :-)
297 lea.l _sbss, %a0 /* Get start of bss */
298 lea.l _ebss, %a1 /* Set up destination */
299 move.l %a0, %a2 /* Copy of bss start */
301 move.l 8(%a0), %d0 /* Get size of ROMFS */
302 addq.l #8, %d0 /* Allow for rounding */
303 and.l #0xfffffffc, %d0 /* Whole words */
305 add.l %d0, %a0 /* Copy from end */
306 add.l %d0, %a1 /* Copy from end */
307 move.l %a1, _ramstart /* Set start of ram */
310 move.l -(%a0), %d0 /* Copy dword */
312 cmp.l %a0, %a2 /* Check if at end */
315 #else /* CONFIG_ROMFS_FS */
317 move.l %a1, _ramstart
318 #endif /* CONFIG_ROMFS_FS */
322 * Zero out the bss region.
324 lea.l _sbss, %a0 /* Get start of bss */
325 lea.l _ebss, %a1 /* Get end of bss */
326 clr.l %d0 /* Set value */
328 move.l %d0, (%a0)+ /* Clear each word */
329 cmp.l %a0, %a1 /* Check if at end */
333 * Load the current task pointer and stack.
335 lea init_thread_union, %a0
339 * Assember start up done, start code proper.
341 jsr start_kernel /* Start Linux kernel */
344 jmp _exit /* Should never get here */
346 /*****************************************************************************/