2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
35 #include <linux/sysdev.h>
39 #include <asm/timer.h>
41 #include <mach_apic.h>
45 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
48 * Is the SiS APIC rmw bug present ?
49 * -1 = don't know, 0 = no, 1 = yes
51 int sis_apic_bug
= -1;
54 * # of IRQ routing registers
56 int nr_ioapic_registers
[MAX_IO_APICS
];
59 * Rough estimation of how many shared IRQs there are, can
62 #define MAX_PLUS_SHARED_IRQS NR_IRQS
63 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
66 * This is performance-critical, we want to do it O(1)
68 * the indexing order of this array favors 1:1 mappings
69 * between pins and IRQs.
72 static struct irq_pin_list
{
74 } irq_2_pin
[PIN_MAP_SIZE
];
76 int vector_irq
[NR_VECTORS
] = { [0 ... NR_VECTORS
- 1] = -1};
78 #define vector_to_irq(vector) \
79 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
81 #define vector_to_irq(vector) (vector)
85 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
86 * shared ISA-space IRQs, so we have to support them. We are super
87 * fast in the common case, and fast for shared ISA-space IRQs.
89 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
91 static int first_free_entry
= NR_IRQS
;
92 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
95 entry
= irq_2_pin
+ entry
->next
;
97 if (entry
->pin
!= -1) {
98 entry
->next
= first_free_entry
;
99 entry
= irq_2_pin
+ entry
->next
;
100 if (++first_free_entry
>= PIN_MAP_SIZE
)
101 panic("io_apic.c: whoops");
108 * Reroute an IRQ to a different pin.
110 static void __init
replace_pin_at_irq(unsigned int irq
,
111 int oldapic
, int oldpin
,
112 int newapic
, int newpin
)
114 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
117 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
118 entry
->apic
= newapic
;
123 entry
= irq_2_pin
+ entry
->next
;
127 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
129 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
130 unsigned int pin
, reg
;
136 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
139 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
142 entry
= irq_2_pin
+ entry
->next
;
147 static void __mask_IO_APIC_irq (unsigned int irq
)
149 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
153 static void __unmask_IO_APIC_irq (unsigned int irq
)
155 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
158 /* mask = 1, trigger = 0 */
159 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
161 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
164 /* mask = 0, trigger = 1 */
165 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
167 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
170 static void mask_IO_APIC_irq (unsigned int irq
)
174 spin_lock_irqsave(&ioapic_lock
, flags
);
175 __mask_IO_APIC_irq(irq
);
176 spin_unlock_irqrestore(&ioapic_lock
, flags
);
179 static void unmask_IO_APIC_irq (unsigned int irq
)
183 spin_lock_irqsave(&ioapic_lock
, flags
);
184 __unmask_IO_APIC_irq(irq
);
185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
188 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
190 struct IO_APIC_route_entry entry
;
193 /* Check delivery_mode to be sure we're not clearing an SMI pin */
194 spin_lock_irqsave(&ioapic_lock
, flags
);
195 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
196 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
197 spin_unlock_irqrestore(&ioapic_lock
, flags
);
198 if (entry
.delivery_mode
== dest_SMI
)
202 * Disable it in the IO-APIC irq-routing table:
204 memset(&entry
, 0, sizeof(entry
));
206 spin_lock_irqsave(&ioapic_lock
, flags
);
207 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
208 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
209 spin_unlock_irqrestore(&ioapic_lock
, flags
);
212 static void clear_IO_APIC (void)
216 for (apic
= 0; apic
< nr_ioapics
; apic
++)
217 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
218 clear_IO_APIC_pin(apic
, pin
);
221 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
225 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
226 unsigned int apicid_value
;
228 apicid_value
= cpu_mask_to_apicid(cpumask
);
229 /* Prepare to do the io_apic_write */
230 apicid_value
= apicid_value
<< 24;
231 spin_lock_irqsave(&ioapic_lock
, flags
);
236 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
239 entry
= irq_2_pin
+ entry
->next
;
241 spin_unlock_irqrestore(&ioapic_lock
, flags
);
244 #if defined(CONFIG_IRQBALANCE)
245 # include <asm/processor.h> /* kernel_thread() */
246 # include <linux/kernel_stat.h> /* kstat */
247 # include <linux/slab.h> /* kmalloc() */
248 # include <linux/timer.h> /* time_after() */
250 # ifdef CONFIG_BALANCED_IRQ_DEBUG
251 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
252 # define Dprintk(x...) do { TDprintk(x); } while (0)
254 # define TDprintk(x...)
255 # define Dprintk(x...)
258 extern cpumask_t irq_affinity
[NR_IRQS
];
260 cpumask_t __cacheline_aligned pending_irq_balance_cpumask
[NR_IRQS
];
262 #define IRQBALANCE_CHECK_ARCH -999
263 static int irqbalance_disabled
= IRQBALANCE_CHECK_ARCH
;
264 static int physical_balance
= 0;
266 struct irq_cpu_info
{
267 unsigned long * last_irq
;
268 unsigned long * irq_delta
;
270 } irq_cpu_data
[NR_CPUS
];
272 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
273 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
274 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
276 #define IDLE_ENOUGH(cpu,now) \
277 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
279 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
281 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
283 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
284 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
285 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
286 #define BALANCED_IRQ_LESS_DELTA (HZ)
288 long balanced_irq_interval
= MAX_BALANCED_IRQ_INTERVAL
;
290 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
291 unsigned long now
, int direction
)
299 if (unlikely(cpu
== curr_cpu
))
302 if (direction
== 1) {
311 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
312 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
317 static inline void balance_irq(int cpu
, int irq
)
319 unsigned long now
= jiffies
;
320 cpumask_t allowed_mask
;
321 unsigned int new_cpu
;
323 if (irqbalance_disabled
)
326 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[irq
]);
327 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
328 if (cpu
!= new_cpu
) {
329 irq_desc_t
*desc
= irq_desc
+ irq
;
332 spin_lock_irqsave(&desc
->lock
, flags
);
333 pending_irq_balance_cpumask
[irq
] = cpumask_of_cpu(new_cpu
);
334 spin_unlock_irqrestore(&desc
->lock
, flags
);
338 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
341 Dprintk("Rotating IRQs among CPUs.\n");
342 for (i
= 0; i
< NR_CPUS
; i
++) {
343 for (j
= 0; cpu_online(i
) && (j
< NR_IRQS
); j
++) {
344 if (!irq_desc
[j
].action
)
346 /* Is it a significant load ? */
347 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
348 useful_load_threshold
)
353 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
354 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
358 static void do_irq_balance(void)
361 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
362 unsigned long move_this_load
= 0;
363 int max_loaded
= 0, min_loaded
= 0;
365 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
367 int tmp_loaded
, first_attempt
= 1;
368 unsigned long tmp_cpu_irq
;
369 unsigned long imbalance
= 0;
370 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
372 for (i
= 0; i
< NR_CPUS
; i
++) {
377 package_index
= CPU_TO_PACKAGEINDEX(i
);
378 for (j
= 0; j
< NR_IRQS
; j
++) {
379 unsigned long value_now
, delta
;
380 /* Is this an active IRQ? */
381 if (!irq_desc
[j
].action
)
383 if ( package_index
== i
)
384 IRQ_DELTA(package_index
,j
) = 0;
385 /* Determine the total count per processor per IRQ */
386 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
388 /* Determine the activity per processor per IRQ */
389 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
391 /* Update last_cpu_irq[][] for the next time */
392 LAST_CPU_IRQ(i
,j
) = value_now
;
394 /* Ignore IRQs whose rate is less than the clock */
395 if (delta
< useful_load_threshold
)
397 /* update the load for the processor or package total */
398 IRQ_DELTA(package_index
,j
) += delta
;
400 /* Keep track of the higher numbered sibling as well */
401 if (i
!= package_index
)
404 * We have sibling A and sibling B in the package
406 * cpu_irq[A] = load for cpu A + load for cpu B
407 * cpu_irq[B] = load for cpu B
409 CPU_IRQ(package_index
) += delta
;
412 /* Find the least loaded processor package */
413 for (i
= 0; i
< NR_CPUS
; i
++) {
416 if (i
!= CPU_TO_PACKAGEINDEX(i
))
418 if (min_cpu_irq
> CPU_IRQ(i
)) {
419 min_cpu_irq
= CPU_IRQ(i
);
423 max_cpu_irq
= ULONG_MAX
;
426 /* Look for heaviest loaded processor.
427 * We may come back to get the next heaviest loaded processor.
428 * Skip processors with trivial loads.
432 for (i
= 0; i
< NR_CPUS
; i
++) {
435 if (i
!= CPU_TO_PACKAGEINDEX(i
))
437 if (max_cpu_irq
<= CPU_IRQ(i
))
439 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
440 tmp_cpu_irq
= CPU_IRQ(i
);
445 if (tmp_loaded
== -1) {
446 /* In the case of small number of heavy interrupt sources,
447 * loading some of the cpus too much. We use Ingo's original
448 * approach to rotate them around.
450 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
451 rotate_irqs_among_cpus(useful_load_threshold
);
454 goto not_worth_the_effort
;
457 first_attempt
= 0; /* heaviest search */
458 max_cpu_irq
= tmp_cpu_irq
; /* load */
459 max_loaded
= tmp_loaded
; /* processor */
460 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
462 Dprintk("max_loaded cpu = %d\n", max_loaded
);
463 Dprintk("min_loaded cpu = %d\n", min_loaded
);
464 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
465 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
466 Dprintk("load imbalance = %lu\n", imbalance
);
468 /* if imbalance is less than approx 10% of max load, then
469 * observe diminishing returns action. - quit
471 if (imbalance
< (max_cpu_irq
>> 3)) {
472 Dprintk("Imbalance too trivial\n");
473 goto not_worth_the_effort
;
477 /* if we select an IRQ to move that can't go where we want, then
478 * see if there is another one to try.
482 for (j
= 0; j
< NR_IRQS
; j
++) {
483 /* Is this an active IRQ? */
484 if (!irq_desc
[j
].action
)
486 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
488 /* Try to find the IRQ that is closest to the imbalance
489 * without going over.
491 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
492 move_this_load
= IRQ_DELTA(max_loaded
,j
);
496 if (selected_irq
== -1) {
500 imbalance
= move_this_load
;
502 /* For physical_balance case, we accumlated both load
503 * values in the one of the siblings cpu_irq[],
504 * to use the same code for physical and logical processors
505 * as much as possible.
507 * NOTE: the cpu_irq[] array holds the sum of the load for
508 * sibling A and sibling B in the slot for the lowest numbered
509 * sibling (A), _AND_ the load for sibling B in the slot for
510 * the higher numbered sibling.
512 * We seek the least loaded sibling by making the comparison
515 load
= CPU_IRQ(min_loaded
) >> 1;
516 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
517 if (load
> CPU_IRQ(j
)) {
518 /* This won't change cpu_sibling_map[min_loaded] */
524 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[selected_irq
]);
525 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
526 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
528 if (!cpus_empty(tmp
)) {
529 irq_desc_t
*desc
= irq_desc
+ selected_irq
;
532 Dprintk("irq = %d moved to cpu = %d\n",
533 selected_irq
, min_loaded
);
534 /* mark for change destination */
535 spin_lock_irqsave(&desc
->lock
, flags
);
536 pending_irq_balance_cpumask
[selected_irq
] =
537 cpumask_of_cpu(min_loaded
);
538 spin_unlock_irqrestore(&desc
->lock
, flags
);
539 /* Since we made a change, come back sooner to
540 * check for more variation.
542 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
543 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
548 not_worth_the_effort
:
550 * if we did not find an IRQ to move, then adjust the time interval
553 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
554 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
555 Dprintk("IRQ worth rotating not found\n");
559 static int balanced_irq(void *unused
)
562 unsigned long prev_balance_time
= jiffies
;
563 long time_remaining
= balanced_irq_interval
;
567 /* push everything to CPU 0 to give us a starting point. */
568 for (i
= 0 ; i
< NR_IRQS
; i
++) {
569 pending_irq_balance_cpumask
[i
] = cpumask_of_cpu(0);
573 set_current_state(TASK_INTERRUPTIBLE
);
574 time_remaining
= schedule_timeout(time_remaining
);
575 if (time_after(jiffies
,
576 prev_balance_time
+balanced_irq_interval
)) {
578 prev_balance_time
= jiffies
;
579 time_remaining
= balanced_irq_interval
;
585 static int __init
balanced_irq_init(void)
588 struct cpuinfo_x86
*c
;
591 cpus_shift_right(tmp
, cpu_online_map
, 2);
593 /* When not overwritten by the command line ask subarchitecture. */
594 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
595 irqbalance_disabled
= NO_BALANCE_IRQ
;
596 if (irqbalance_disabled
)
599 /* disable irqbalance completely if there is only one processor online */
600 if (num_online_cpus() < 2) {
601 irqbalance_disabled
= 1;
605 * Enable physical balance only if more than 1 physical processor
608 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
609 physical_balance
= 1;
611 for (i
= 0; i
< NR_CPUS
; i
++) {
614 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
615 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
616 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
617 printk(KERN_ERR
"balanced_irq_init: out of memory");
620 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
621 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
624 printk(KERN_INFO
"Starting balanced_irq\n");
625 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
628 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
630 for (i
= 0; i
< NR_CPUS
; i
++) {
631 if(irq_cpu_data
[i
].irq_delta
)
632 kfree(irq_cpu_data
[i
].irq_delta
);
633 if(irq_cpu_data
[i
].last_irq
)
634 kfree(irq_cpu_data
[i
].last_irq
);
639 static int __init
irqbalance_disable(char *str
)
641 irqbalance_disabled
= 1;
645 __setup("noirqbalance", irqbalance_disable
);
647 static inline void move_irq(int irq
)
649 /* note - we hold the desc->lock */
650 if (unlikely(!cpus_empty(pending_irq_balance_cpumask
[irq
]))) {
651 set_ioapic_affinity_irq(irq
, pending_irq_balance_cpumask
[irq
]);
652 cpus_clear(pending_irq_balance_cpumask
[irq
]);
656 __initcall(balanced_irq_init
);
658 #else /* !CONFIG_IRQBALANCE */
659 static inline void move_irq(int irq
) { }
660 #endif /* CONFIG_IRQBALANCE */
663 void fastcall
send_IPI_self(int vector
)
670 apic_wait_icr_idle();
671 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
673 * Send the IPI. The write to APIC_ICR fires this off.
675 apic_write_around(APIC_ICR
, cfg
);
677 #endif /* !CONFIG_SMP */
681 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
682 * specific CPU-side IRQs.
686 int pirq_entries
[MAX_PIRQS
];
688 int skip_ioapic_setup
;
690 static int __init
ioapic_setup(char *str
)
692 skip_ioapic_setup
= 1;
696 __setup("noapic", ioapic_setup
);
698 static int __init
ioapic_pirq_setup(char *str
)
701 int ints
[MAX_PIRQS
+1];
703 get_options(str
, ARRAY_SIZE(ints
), ints
);
705 for (i
= 0; i
< MAX_PIRQS
; i
++)
706 pirq_entries
[i
] = -1;
709 apic_printk(APIC_VERBOSE
, KERN_INFO
710 "PIRQ redirection, working around broken MP-BIOS.\n");
712 if (ints
[0] < MAX_PIRQS
)
715 for (i
= 0; i
< max
; i
++) {
716 apic_printk(APIC_VERBOSE
, KERN_DEBUG
717 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
719 * PIRQs are mapped upside down, usually.
721 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
726 __setup("pirq=", ioapic_pirq_setup
);
729 * Find the IRQ entry number of a certain pin.
731 static int __init
find_irq_entry(int apic
, int pin
, int type
)
735 for (i
= 0; i
< mp_irq_entries
; i
++)
736 if (mp_irqs
[i
].mpc_irqtype
== type
&&
737 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
738 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
739 mp_irqs
[i
].mpc_dstirq
== pin
)
746 * Find the pin to which IRQ[irq] (ISA) is connected
748 static int find_isa_irq_pin(int irq
, int type
)
752 for (i
= 0; i
< mp_irq_entries
; i
++) {
753 int lbus
= mp_irqs
[i
].mpc_srcbus
;
755 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
756 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
757 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
758 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
760 (mp_irqs
[i
].mpc_irqtype
== type
) &&
761 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
763 return mp_irqs
[i
].mpc_dstirq
;
769 * Find a specific PCI IRQ entry.
770 * Not an __init, possibly needed by modules
772 static int pin_2_irq(int idx
, int apic
, int pin
);
774 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
776 int apic
, i
, best_guess
= -1;
778 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
779 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
780 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
781 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
784 for (i
= 0; i
< mp_irq_entries
; i
++) {
785 int lbus
= mp_irqs
[i
].mpc_srcbus
;
787 for (apic
= 0; apic
< nr_ioapics
; apic
++)
788 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
789 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
792 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
793 !mp_irqs
[i
].mpc_irqtype
&&
795 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
796 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
798 if (!(apic
|| IO_APIC_IRQ(irq
)))
801 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
804 * Use the first all-but-pin matching entry as a
805 * best-guess fuzzy result for broken mptables.
815 * This function currently is only a helper for the i386 smp boot process where
816 * we need to reprogram the ioredtbls to cater for the cpus which have come online
817 * so mask in all cases should simply be TARGET_CPUS
819 void __init
setup_ioapic_dest(void)
821 int pin
, ioapic
, irq
, irq_entry
;
823 if (skip_ioapic_setup
== 1)
826 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
827 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
828 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
831 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
832 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
839 * EISA Edge/Level control register, ELCR
841 static int __init
EISA_ELCR(unsigned int irq
)
844 unsigned int port
= 0x4d0 + (irq
>> 3);
845 return (inb(port
) >> (irq
& 7)) & 1;
847 apic_printk(APIC_VERBOSE
, KERN_INFO
848 "Broken MPtable reports ISA irq %d\n", irq
);
852 /* EISA interrupts are always polarity zero and can be edge or level
853 * trigger depending on the ELCR value. If an interrupt is listed as
854 * EISA conforming in the MP table, that means its trigger type must
855 * be read in from the ELCR */
857 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
858 #define default_EISA_polarity(idx) (0)
860 /* ISA interrupts are always polarity zero edge triggered,
861 * when listed as conforming in the MP table. */
863 #define default_ISA_trigger(idx) (0)
864 #define default_ISA_polarity(idx) (0)
866 /* PCI interrupts are always polarity one level triggered,
867 * when listed as conforming in the MP table. */
869 #define default_PCI_trigger(idx) (1)
870 #define default_PCI_polarity(idx) (1)
872 /* MCA interrupts are always polarity zero level triggered,
873 * when listed as conforming in the MP table. */
875 #define default_MCA_trigger(idx) (1)
876 #define default_MCA_polarity(idx) (0)
878 /* NEC98 interrupts are always polarity zero edge triggered,
879 * when listed as conforming in the MP table. */
881 #define default_NEC98_trigger(idx) (0)
882 #define default_NEC98_polarity(idx) (0)
884 static int __init
MPBIOS_polarity(int idx
)
886 int bus
= mp_irqs
[idx
].mpc_srcbus
;
890 * Determine IRQ line polarity (high active or low active):
892 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
894 case 0: /* conforms, ie. bus-type dependent polarity */
896 switch (mp_bus_id_to_type
[bus
])
898 case MP_BUS_ISA
: /* ISA pin */
900 polarity
= default_ISA_polarity(idx
);
903 case MP_BUS_EISA
: /* EISA pin */
905 polarity
= default_EISA_polarity(idx
);
908 case MP_BUS_PCI
: /* PCI pin */
910 polarity
= default_PCI_polarity(idx
);
913 case MP_BUS_MCA
: /* MCA pin */
915 polarity
= default_MCA_polarity(idx
);
918 case MP_BUS_NEC98
: /* NEC 98 pin */
920 polarity
= default_NEC98_polarity(idx
);
925 printk(KERN_WARNING
"broken BIOS!!\n");
932 case 1: /* high active */
937 case 2: /* reserved */
939 printk(KERN_WARNING
"broken BIOS!!\n");
943 case 3: /* low active */
948 default: /* invalid */
950 printk(KERN_WARNING
"broken BIOS!!\n");
958 static int __init
MPBIOS_trigger(int idx
)
960 int bus
= mp_irqs
[idx
].mpc_srcbus
;
964 * Determine IRQ trigger mode (edge or level sensitive):
966 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
968 case 0: /* conforms, ie. bus-type dependent */
970 switch (mp_bus_id_to_type
[bus
])
972 case MP_BUS_ISA
: /* ISA pin */
974 trigger
= default_ISA_trigger(idx
);
977 case MP_BUS_EISA
: /* EISA pin */
979 trigger
= default_EISA_trigger(idx
);
982 case MP_BUS_PCI
: /* PCI pin */
984 trigger
= default_PCI_trigger(idx
);
987 case MP_BUS_MCA
: /* MCA pin */
989 trigger
= default_MCA_trigger(idx
);
992 case MP_BUS_NEC98
: /* NEC 98 pin */
994 trigger
= default_NEC98_trigger(idx
);
999 printk(KERN_WARNING
"broken BIOS!!\n");
1011 case 2: /* reserved */
1013 printk(KERN_WARNING
"broken BIOS!!\n");
1022 default: /* invalid */
1024 printk(KERN_WARNING
"broken BIOS!!\n");
1032 static inline int irq_polarity(int idx
)
1034 return MPBIOS_polarity(idx
);
1037 static inline int irq_trigger(int idx
)
1039 return MPBIOS_trigger(idx
);
1042 static int pin_2_irq(int idx
, int apic
, int pin
)
1045 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1048 * Debugging check, we are in big trouble if this message pops up!
1050 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1051 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1053 switch (mp_bus_id_to_type
[bus
])
1055 case MP_BUS_ISA
: /* ISA pin */
1060 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1063 case MP_BUS_PCI
: /* PCI pin */
1066 * PCI IRQs are mapped in order
1070 irq
+= nr_ioapic_registers
[i
++];
1072 if ((!apic
) && (irq
< 16))
1078 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 if ((pin
>= 16) && (pin
<= 23)) {
1088 if (pirq_entries
[pin
-16] != -1) {
1089 if (!pirq_entries
[pin
-16]) {
1090 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin
-16);
1093 irq
= pirq_entries
[pin
-16];
1094 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1103 static inline int IO_APIC_irq_trigger(int irq
)
1107 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1108 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1109 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1110 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1111 return irq_trigger(idx
);
1115 * nonexistent IRQs are edge default
1120 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1121 u8 irq_vector
[NR_IRQ_VECTORS
] = { FIRST_DEVICE_VECTOR
, 0 };
1123 int assign_irq_vector(int irq
)
1125 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1127 BUG_ON(irq
>= NR_IRQ_VECTORS
);
1128 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0)
1129 return IO_APIC_VECTOR(irq
);
1131 current_vector
+= 8;
1132 if (current_vector
== SYSCALL_VECTOR
)
1135 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1139 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1142 vector_irq
[current_vector
] = irq
;
1143 if (irq
!= AUTO_ASSIGN
)
1144 IO_APIC_VECTOR(irq
) = current_vector
;
1146 return current_vector
;
1149 static struct hw_interrupt_type ioapic_level_type
;
1150 static struct hw_interrupt_type ioapic_edge_type
;
1152 #define IOAPIC_AUTO -1
1153 #define IOAPIC_EDGE 0
1154 #define IOAPIC_LEVEL 1
1156 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1158 if (use_pci_vector() && !platform_legacy_irq(irq
)) {
1159 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1160 trigger
== IOAPIC_LEVEL
)
1161 irq_desc
[vector
].handler
= &ioapic_level_type
;
1163 irq_desc
[vector
].handler
= &ioapic_edge_type
;
1164 set_intr_gate(vector
, interrupt
[vector
]);
1166 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1167 trigger
== IOAPIC_LEVEL
)
1168 irq_desc
[irq
].handler
= &ioapic_level_type
;
1170 irq_desc
[irq
].handler
= &ioapic_edge_type
;
1171 set_intr_gate(vector
, interrupt
[irq
]);
1175 void __init
setup_IO_APIC_irqs(void)
1177 struct IO_APIC_route_entry entry
;
1178 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1179 unsigned long flags
;
1181 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1183 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1184 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1187 * add it to the IO-APIC irq-routing table:
1189 memset(&entry
,0,sizeof(entry
));
1191 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1192 entry
.dest_mode
= INT_DEST_MODE
;
1193 entry
.mask
= 0; /* enable IRQ */
1194 entry
.dest
.logical
.logical_dest
=
1195 cpu_mask_to_apicid(TARGET_CPUS
);
1197 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1200 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1201 " IO-APIC (apicid-pin) %d-%d",
1202 mp_ioapics
[apic
].mpc_apicid
,
1206 apic_printk(APIC_VERBOSE
, ", %d-%d",
1207 mp_ioapics
[apic
].mpc_apicid
, pin
);
1211 entry
.trigger
= irq_trigger(idx
);
1212 entry
.polarity
= irq_polarity(idx
);
1214 if (irq_trigger(idx
)) {
1219 irq
= pin_2_irq(idx
, apic
, pin
);
1221 * skip adding the timer int on secondary nodes, which causes
1222 * a small but painful rift in the time-space continuum
1224 if (multi_timer_check(apic
, irq
))
1227 add_pin_to_irq(irq
, apic
, pin
);
1229 if (!apic
&& !IO_APIC_IRQ(irq
))
1232 if (IO_APIC_IRQ(irq
)) {
1233 vector
= assign_irq_vector(irq
);
1234 entry
.vector
= vector
;
1235 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1237 if (!apic
&& (irq
< 16))
1238 disable_8259A_irq(irq
);
1240 spin_lock_irqsave(&ioapic_lock
, flags
);
1241 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1242 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1243 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1248 apic_printk(APIC_VERBOSE
, " not connected.\n");
1252 * Set up the 8259A-master output pin:
1254 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
1256 struct IO_APIC_route_entry entry
;
1257 unsigned long flags
;
1259 memset(&entry
,0,sizeof(entry
));
1261 disable_8259A_irq(0);
1264 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1267 * We use logical delivery to get the timer IRQ
1270 entry
.dest_mode
= INT_DEST_MODE
;
1271 entry
.mask
= 0; /* unmask IRQ now */
1272 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1273 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1276 entry
.vector
= vector
;
1279 * The timer IRQ doesn't have to know that behind the
1280 * scene we have a 8259A-master in AEOI mode ...
1282 irq_desc
[0].handler
= &ioapic_edge_type
;
1285 * Add it to the IO-APIC irq-routing table:
1287 spin_lock_irqsave(&ioapic_lock
, flags
);
1288 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
1289 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
1290 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1292 enable_8259A_irq(0);
1295 static inline void UNEXPECTED_IO_APIC(void)
1299 void __init
print_IO_APIC(void)
1302 union IO_APIC_reg_00 reg_00
;
1303 union IO_APIC_reg_01 reg_01
;
1304 union IO_APIC_reg_02 reg_02
;
1305 union IO_APIC_reg_03 reg_03
;
1306 unsigned long flags
;
1308 if (apic_verbosity
== APIC_QUIET
)
1311 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1312 for (i
= 0; i
< nr_ioapics
; i
++)
1313 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1314 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1317 * We are a bit conservative about what we expect. We have to
1318 * know about every hardware change ASAP.
1320 printk(KERN_INFO
"testing the IO APIC.......................\n");
1322 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1324 spin_lock_irqsave(&ioapic_lock
, flags
);
1325 reg_00
.raw
= io_apic_read(apic
, 0);
1326 reg_01
.raw
= io_apic_read(apic
, 1);
1327 if (reg_01
.bits
.version
>= 0x10)
1328 reg_02
.raw
= io_apic_read(apic
, 2);
1329 if (reg_01
.bits
.version
>= 0x20)
1330 reg_03
.raw
= io_apic_read(apic
, 3);
1331 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1333 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1334 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1335 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1336 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1337 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1338 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1339 UNEXPECTED_IO_APIC();
1340 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1341 UNEXPECTED_IO_APIC();
1343 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1344 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1345 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1346 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1347 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1348 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1349 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1350 (reg_01
.bits
.entries
!= 0x2E) &&
1351 (reg_01
.bits
.entries
!= 0x3F)
1353 UNEXPECTED_IO_APIC();
1355 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1356 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1357 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1358 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1359 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1360 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1361 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1363 UNEXPECTED_IO_APIC();
1364 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1365 UNEXPECTED_IO_APIC();
1368 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1369 * but the value of reg_02 is read as the previous read register
1370 * value, so ignore it if reg_02 == reg_01.
1372 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1373 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1374 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1375 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1376 UNEXPECTED_IO_APIC();
1380 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1381 * or reg_03, but the value of reg_0[23] is read as the previous read
1382 * register value, so ignore it if reg_03 == reg_0[12].
1384 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1385 reg_03
.raw
!= reg_01
.raw
) {
1386 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1387 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1388 if (reg_03
.bits
.__reserved_1
)
1389 UNEXPECTED_IO_APIC();
1392 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1394 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1395 " Stat Dest Deli Vect: \n");
1397 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1398 struct IO_APIC_route_entry entry
;
1400 spin_lock_irqsave(&ioapic_lock
, flags
);
1401 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1402 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1403 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1405 printk(KERN_DEBUG
" %02x %03X %02X ",
1407 entry
.dest
.logical
.logical_dest
,
1408 entry
.dest
.physical
.physical_dest
1411 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1416 entry
.delivery_status
,
1418 entry
.delivery_mode
,
1423 if (use_pci_vector())
1424 printk(KERN_INFO
"Using vector-based indexing\n");
1425 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1426 for (i
= 0; i
< NR_IRQS
; i
++) {
1427 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1430 if (use_pci_vector() && !platform_legacy_irq(i
))
1431 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1433 printk(KERN_DEBUG
"IRQ%d ", i
);
1435 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1438 entry
= irq_2_pin
+ entry
->next
;
1443 printk(KERN_INFO
".................................... done.\n");
1448 static void print_APIC_bitfield (int base
)
1453 if (apic_verbosity
== APIC_QUIET
)
1456 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1457 for (i
= 0; i
< 8; i
++) {
1458 v
= apic_read(base
+ i
*0x10);
1459 for (j
= 0; j
< 32; j
++) {
1469 void /*__init*/ print_local_APIC(void * dummy
)
1471 unsigned int v
, ver
, maxlvt
;
1473 if (apic_verbosity
== APIC_QUIET
)
1476 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1477 smp_processor_id(), hard_smp_processor_id());
1478 v
= apic_read(APIC_ID
);
1479 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1480 v
= apic_read(APIC_LVR
);
1481 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1482 ver
= GET_APIC_VERSION(v
);
1483 maxlvt
= get_maxlvt();
1485 v
= apic_read(APIC_TASKPRI
);
1486 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1488 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1489 v
= apic_read(APIC_ARBPRI
);
1490 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1491 v
& APIC_ARBPRI_MASK
);
1492 v
= apic_read(APIC_PROCPRI
);
1493 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1496 v
= apic_read(APIC_EOI
);
1497 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1498 v
= apic_read(APIC_RRR
);
1499 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1500 v
= apic_read(APIC_LDR
);
1501 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1502 v
= apic_read(APIC_DFR
);
1503 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1504 v
= apic_read(APIC_SPIV
);
1505 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1507 printk(KERN_DEBUG
"... APIC ISR field:\n");
1508 print_APIC_bitfield(APIC_ISR
);
1509 printk(KERN_DEBUG
"... APIC TMR field:\n");
1510 print_APIC_bitfield(APIC_TMR
);
1511 printk(KERN_DEBUG
"... APIC IRR field:\n");
1512 print_APIC_bitfield(APIC_IRR
);
1514 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1515 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1516 apic_write(APIC_ESR
, 0);
1517 v
= apic_read(APIC_ESR
);
1518 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1521 v
= apic_read(APIC_ICR
);
1522 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1523 v
= apic_read(APIC_ICR2
);
1524 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1526 v
= apic_read(APIC_LVTT
);
1527 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1529 if (maxlvt
> 3) { /* PC is LVT#4. */
1530 v
= apic_read(APIC_LVTPC
);
1531 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1533 v
= apic_read(APIC_LVT0
);
1534 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1535 v
= apic_read(APIC_LVT1
);
1536 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1538 if (maxlvt
> 2) { /* ERR is LVT#3. */
1539 v
= apic_read(APIC_LVTERR
);
1540 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1543 v
= apic_read(APIC_TMICT
);
1544 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1545 v
= apic_read(APIC_TMCCT
);
1546 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1547 v
= apic_read(APIC_TDCR
);
1548 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1552 void print_all_local_APICs (void)
1554 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1557 void /*__init*/ print_PIC(void)
1559 extern spinlock_t i8259A_lock
;
1561 unsigned long flags
;
1563 if (apic_verbosity
== APIC_QUIET
)
1566 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1568 spin_lock_irqsave(&i8259A_lock
, flags
);
1570 v
= inb(0xa1) << 8 | inb(0x21);
1571 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1573 v
= inb(0xa0) << 8 | inb(0x20);
1574 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1578 v
= inb(0xa0) << 8 | inb(0x20);
1582 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1584 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1586 v
= inb(0x4d1) << 8 | inb(0x4d0);
1587 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1590 static void __init
enable_IO_APIC(void)
1592 union IO_APIC_reg_01 reg_01
;
1594 unsigned long flags
;
1596 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1597 irq_2_pin
[i
].pin
= -1;
1598 irq_2_pin
[i
].next
= 0;
1601 for (i
= 0; i
< MAX_PIRQS
; i
++)
1602 pirq_entries
[i
] = -1;
1605 * The number of IO-APIC IRQ registers (== #pins):
1607 for (i
= 0; i
< nr_ioapics
; i
++) {
1608 spin_lock_irqsave(&ioapic_lock
, flags
);
1609 reg_01
.raw
= io_apic_read(i
, 1);
1610 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1611 nr_ioapic_registers
[i
] = reg_01
.bits
.entries
+1;
1615 * Do not trust the IO-APIC being empty at bootup
1621 * Not an __init, needed by the reboot code
1623 void disable_IO_APIC(void)
1626 * Clear the IO-APIC before rebooting:
1630 disconnect_bsp_APIC();
1634 * function to set the IO-APIC physical IDs based on the
1635 * values stored in the MPC table.
1637 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1640 #ifndef CONFIG_X86_NUMAQ
1641 static void __init
setup_ioapic_ids_from_mpc(void)
1643 union IO_APIC_reg_00 reg_00
;
1644 physid_mask_t phys_id_present_map
;
1647 unsigned char old_id
;
1648 unsigned long flags
;
1651 * This is broken; anything with a real cpu count has to
1652 * circumvent this idiocy regardless.
1654 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1657 * Set the IOAPIC ID to the value stored in the MPC table.
1659 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1661 /* Read the register 0 value */
1662 spin_lock_irqsave(&ioapic_lock
, flags
);
1663 reg_00
.raw
= io_apic_read(apic
, 0);
1664 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1666 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1668 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1669 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1670 apic
, mp_ioapics
[apic
].mpc_apicid
);
1671 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1673 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1676 /* Don't check I/O APIC IDs for some xAPIC systems. They have
1677 * no meaning without the serial APIC bus. */
1678 if (NO_IOAPIC_CHECK
)
1681 * Sanity check, is the ID really free? Every APIC in a
1682 * system must have a unique ID or we get lots of nice
1683 * 'stuck on smp_invalidate_needed IPI wait' messages.
1685 if (check_apicid_used(phys_id_present_map
,
1686 mp_ioapics
[apic
].mpc_apicid
)) {
1687 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1688 apic
, mp_ioapics
[apic
].mpc_apicid
);
1689 for (i
= 0; i
< get_physical_broadcast(); i
++)
1690 if (!physid_isset(i
, phys_id_present_map
))
1692 if (i
>= get_physical_broadcast())
1693 panic("Max APIC ID exceeded!\n");
1694 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1696 physid_set(i
, phys_id_present_map
);
1697 mp_ioapics
[apic
].mpc_apicid
= i
;
1700 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1701 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1702 "phys_id_present_map\n",
1703 mp_ioapics
[apic
].mpc_apicid
);
1704 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1709 * We need to adjust the IRQ routing table
1710 * if the ID changed.
1712 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1713 for (i
= 0; i
< mp_irq_entries
; i
++)
1714 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1715 mp_irqs
[i
].mpc_dstapic
1716 = mp_ioapics
[apic
].mpc_apicid
;
1719 * Read the right value from the MPC table and
1720 * write it into the ID register.
1722 apic_printk(APIC_VERBOSE
, KERN_INFO
1723 "...changing IO-APIC physical APIC ID to %d ...",
1724 mp_ioapics
[apic
].mpc_apicid
);
1726 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1727 spin_lock_irqsave(&ioapic_lock
, flags
);
1728 io_apic_write(apic
, 0, reg_00
.raw
);
1729 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1734 spin_lock_irqsave(&ioapic_lock
, flags
);
1735 reg_00
.raw
= io_apic_read(apic
, 0);
1736 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1737 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1738 printk("could not set ID!\n");
1740 apic_printk(APIC_VERBOSE
, " ok.\n");
1744 static void __init
setup_ioapic_ids_from_mpc(void) { }
1748 * There is a nasty bug in some older SMP boards, their mptable lies
1749 * about the timer IRQ. We do the following to work around the situation:
1751 * - timer IRQ defaults to IO-APIC IRQ
1752 * - if this function detects that timer IRQs are defunct, then we fall
1753 * back to ISA timer IRQs
1755 static int __init
timer_irq_works(void)
1757 unsigned long t1
= jiffies
;
1760 /* Let ten ticks pass... */
1761 mdelay((10 * 1000) / HZ
);
1764 * Expect a few ticks at least, to be sure some possible
1765 * glue logic does not lock up after one or two first
1766 * ticks in a non-ExtINT mode. Also the local APIC
1767 * might have cached one ExtINT interrupt. Finally, at
1768 * least one tick may be lost due to delays.
1770 if (jiffies
- t1
> 4)
1777 * In the SMP+IOAPIC case it might happen that there are an unspecified
1778 * number of pending IRQ events unhandled. These cases are very rare,
1779 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1780 * better to do it this way as thus we do not have to be aware of
1781 * 'pending' interrupts in the IRQ path, except at this point.
1784 * Edge triggered needs to resend any interrupt
1785 * that was delayed but this is now handled in the device
1790 * Starting up a edge-triggered IO-APIC interrupt is
1791 * nasty - we need to make sure that we get the edge.
1792 * If it is already asserted for some reason, we need
1793 * return 1 to indicate that is was pending.
1795 * This is not complete - we should be able to fake
1796 * an edge even if it isn't on the 8259A...
1798 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1800 int was_pending
= 0;
1801 unsigned long flags
;
1803 spin_lock_irqsave(&ioapic_lock
, flags
);
1805 disable_8259A_irq(irq
);
1806 if (i8259A_irq_pending(irq
))
1809 __unmask_IO_APIC_irq(irq
);
1810 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1816 * Once we have recorded IRQ_PENDING already, we can mask the
1817 * interrupt for real. This prevents IRQ storms from unhandled
1820 static void ack_edge_ioapic_irq(unsigned int irq
)
1823 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1824 == (IRQ_PENDING
| IRQ_DISABLED
))
1825 mask_IO_APIC_irq(irq
);
1830 * Level triggered interrupts can just be masked,
1831 * and shutting down and starting up the interrupt
1832 * is the same as enabling and disabling them -- except
1833 * with a startup need to return a "was pending" value.
1835 * Level triggered interrupts are special because we
1836 * do not touch any IO-APIC register while handling
1837 * them. We ack the APIC in the end-IRQ handler, not
1838 * in the start-IRQ-handler. Protection against reentrance
1839 * from the same interrupt is still provided, both by the
1840 * generic IRQ layer and by the fact that an unacked local
1841 * APIC does not accept IRQs.
1843 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1845 unmask_IO_APIC_irq(irq
);
1847 return 0; /* don't check for pending */
1850 static void end_level_ioapic_irq (unsigned int irq
)
1857 * It appears there is an erratum which affects at least version 0x11
1858 * of I/O APIC (that's the 82093AA and cores integrated into various
1859 * chipsets). Under certain conditions a level-triggered interrupt is
1860 * erroneously delivered as edge-triggered one but the respective IRR
1861 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1862 * message but it will never arrive and further interrupts are blocked
1863 * from the source. The exact reason is so far unknown, but the
1864 * phenomenon was observed when two consecutive interrupt requests
1865 * from a given source get delivered to the same CPU and the source is
1866 * temporarily disabled in between.
1868 * A workaround is to simulate an EOI message manually. We achieve it
1869 * by setting the trigger mode to edge and then to level when the edge
1870 * trigger mode gets detected in the TMR of a local APIC for a
1871 * level-triggered interrupt. We mask the source for the time of the
1872 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1873 * The idea is from Manfred Spraul. --macro
1875 i
= IO_APIC_VECTOR(irq
);
1877 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1881 if (!(v
& (1 << (i
& 0x1f)))) {
1882 #ifdef APIC_MISMATCH_DEBUG
1883 atomic_inc(&irq_mis_count
);
1885 spin_lock(&ioapic_lock
);
1886 __mask_and_edge_IO_APIC_irq(irq
);
1887 __unmask_and_level_IO_APIC_irq(irq
);
1888 spin_unlock(&ioapic_lock
);
1892 #ifdef CONFIG_PCI_MSI
1893 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
1895 int irq
= vector_to_irq(vector
);
1897 return startup_edge_ioapic_irq(irq
);
1900 static void ack_edge_ioapic_vector(unsigned int vector
)
1902 int irq
= vector_to_irq(vector
);
1904 ack_edge_ioapic_irq(irq
);
1907 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
1909 int irq
= vector_to_irq(vector
);
1911 return startup_level_ioapic_irq (irq
);
1914 static void end_level_ioapic_vector (unsigned int vector
)
1916 int irq
= vector_to_irq(vector
);
1918 end_level_ioapic_irq(irq
);
1921 static void mask_IO_APIC_vector (unsigned int vector
)
1923 int irq
= vector_to_irq(vector
);
1925 mask_IO_APIC_irq(irq
);
1928 static void unmask_IO_APIC_vector (unsigned int vector
)
1930 int irq
= vector_to_irq(vector
);
1932 unmask_IO_APIC_irq(irq
);
1935 static void set_ioapic_affinity_vector (unsigned int vector
,
1938 int irq
= vector_to_irq(vector
);
1940 set_ioapic_affinity_irq(irq
, cpu_mask
);
1945 * Level and edge triggered IO-APIC interrupts need different handling,
1946 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1947 * handled with the level-triggered descriptor, but that one has slightly
1948 * more overhead. Level-triggered interrupts cannot be handled with the
1949 * edge-triggered handler, without risking IRQ storms and other ugly
1952 static struct hw_interrupt_type ioapic_edge_type
= {
1953 .typename
= "IO-APIC-edge",
1954 .startup
= startup_edge_ioapic
,
1955 .shutdown
= shutdown_edge_ioapic
,
1956 .enable
= enable_edge_ioapic
,
1957 .disable
= disable_edge_ioapic
,
1958 .ack
= ack_edge_ioapic
,
1959 .end
= end_edge_ioapic
,
1960 .set_affinity
= set_ioapic_affinity
,
1963 static struct hw_interrupt_type ioapic_level_type
= {
1964 .typename
= "IO-APIC-level",
1965 .startup
= startup_level_ioapic
,
1966 .shutdown
= shutdown_level_ioapic
,
1967 .enable
= enable_level_ioapic
,
1968 .disable
= disable_level_ioapic
,
1969 .ack
= mask_and_ack_level_ioapic
,
1970 .end
= end_level_ioapic
,
1971 .set_affinity
= set_ioapic_affinity
,
1974 static inline void init_IO_APIC_traps(void)
1979 * NOTE! The local APIC isn't very good at handling
1980 * multiple interrupts at the same interrupt level.
1981 * As the interrupt level is determined by taking the
1982 * vector number and shifting that right by 4, we
1983 * want to spread these out a bit so that they don't
1984 * all fall in the same interrupt level.
1986 * Also, we've got to be careful not to trash gate
1987 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1989 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1991 if (use_pci_vector()) {
1992 if (!platform_legacy_irq(tmp
))
1993 if ((tmp
= vector_to_irq(tmp
)) == -1)
1996 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
1998 * Hmm.. We don't have an entry for this,
1999 * so default to an old-fashioned 8259
2000 * interrupt if we can..
2003 make_8259A_irq(irq
);
2005 /* Strange. Oh, well.. */
2006 irq_desc
[irq
].handler
= &no_irq_type
;
2011 static void enable_lapic_irq (unsigned int irq
)
2015 v
= apic_read(APIC_LVT0
);
2016 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2019 static void disable_lapic_irq (unsigned int irq
)
2023 v
= apic_read(APIC_LVT0
);
2024 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2027 static void ack_lapic_irq (unsigned int irq
)
2032 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
2034 static struct hw_interrupt_type lapic_irq_type
= {
2035 .typename
= "local-APIC-edge",
2036 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
2037 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
2038 .enable
= enable_lapic_irq
,
2039 .disable
= disable_lapic_irq
,
2040 .ack
= ack_lapic_irq
,
2041 .end
= end_lapic_irq
2044 static void setup_nmi (void)
2047 * Dirty trick to enable the NMI watchdog ...
2048 * We put the 8259A master into AEOI mode and
2049 * unmask on all local APICs LVT0 as NMI.
2051 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2052 * is from Maciej W. Rozycki - so we do not have to EOI from
2053 * the NMI handler or the timer interrupt.
2055 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2057 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2059 apic_printk(APIC_VERBOSE
, " done.\n");
2063 * This looks a bit hackish but it's about the only one way of sending
2064 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2065 * not support the ExtINT mode, unfortunately. We need to send these
2066 * cycles as some i82489DX-based boards have glue logic that keeps the
2067 * 8259A interrupt line asserted until INTA. --macro
2069 static inline void unlock_ExtINT_logic(void)
2072 struct IO_APIC_route_entry entry0
, entry1
;
2073 unsigned char save_control
, save_freq_select
;
2074 unsigned long flags
;
2076 pin
= find_isa_irq_pin(8, mp_INT
);
2080 spin_lock_irqsave(&ioapic_lock
, flags
);
2081 *(((int *)&entry0
) + 1) = io_apic_read(0, 0x11 + 2 * pin
);
2082 *(((int *)&entry0
) + 0) = io_apic_read(0, 0x10 + 2 * pin
);
2083 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2084 clear_IO_APIC_pin(0, pin
);
2086 memset(&entry1
, 0, sizeof(entry1
));
2088 entry1
.dest_mode
= 0; /* physical delivery */
2089 entry1
.mask
= 0; /* unmask IRQ now */
2090 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2091 entry1
.delivery_mode
= dest_ExtINT
;
2092 entry1
.polarity
= entry0
.polarity
;
2096 spin_lock_irqsave(&ioapic_lock
, flags
);
2097 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
2098 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
2099 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2101 save_control
= CMOS_READ(RTC_CONTROL
);
2102 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2103 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2105 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2110 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2114 CMOS_WRITE(save_control
, RTC_CONTROL
);
2115 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2116 clear_IO_APIC_pin(0, pin
);
2118 spin_lock_irqsave(&ioapic_lock
, flags
);
2119 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
2120 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
2121 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2125 * This code may look a bit paranoid, but it's supposed to cooperate with
2126 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2127 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2128 * fanatically on his truly buggy board.
2130 static inline void check_timer(void)
2136 * get/set the timer IRQ vector:
2138 disable_8259A_irq(0);
2139 vector
= assign_irq_vector(0);
2140 set_intr_gate(vector
, interrupt
[0]);
2143 * Subtle, code in do_timer_interrupt() expects an AEOI
2144 * mode for the 8259A whenever interrupts are routed
2145 * through I/O APICs. Also IRQ0 has to be enabled in
2146 * the 8259A which implies the virtual wire has to be
2147 * disabled in the local APIC.
2149 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2152 enable_8259A_irq(0);
2154 pin1
= find_isa_irq_pin(0, mp_INT
);
2155 pin2
= find_isa_irq_pin(0, mp_ExtINT
);
2157 printk(KERN_INFO
"..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
2161 * Ok, does IRQ0 through the IOAPIC work?
2163 unmask_IO_APIC_irq(0);
2164 if (timer_irq_works()) {
2165 if (nmi_watchdog
== NMI_IO_APIC
) {
2166 disable_8259A_irq(0);
2168 enable_8259A_irq(0);
2169 check_nmi_watchdog();
2173 clear_IO_APIC_pin(0, pin1
);
2174 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2177 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2179 printk("\n..... (found pin %d) ...", pin2
);
2181 * legacy devices should be connected to IO APIC #0
2183 setup_ExtINT_IRQ0_pin(pin2
, vector
);
2184 if (timer_irq_works()) {
2187 replace_pin_at_irq(0, 0, pin1
, 0, pin2
);
2189 add_pin_to_irq(0, 0, pin2
);
2190 if (nmi_watchdog
== NMI_IO_APIC
) {
2192 check_nmi_watchdog();
2197 * Cleanup, just in case ...
2199 clear_IO_APIC_pin(0, pin2
);
2201 printk(" failed.\n");
2203 if (nmi_watchdog
== NMI_IO_APIC
) {
2204 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2208 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2210 disable_8259A_irq(0);
2211 irq_desc
[0].handler
= &lapic_irq_type
;
2212 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2213 enable_8259A_irq(0);
2215 if (timer_irq_works()) {
2216 printk(" works.\n");
2219 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2220 printk(" failed.\n");
2222 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2227 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2229 unlock_ExtINT_logic();
2231 if (timer_irq_works()) {
2232 printk(" works.\n");
2235 printk(" failed :(.\n");
2236 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2237 "report. Then try booting with the 'noapic' option");
2242 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2243 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2244 * Linux doesn't really care, as it's not actually used
2245 * for any interrupt handling anyway.
2247 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2249 void __init
setup_IO_APIC(void)
2254 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2256 io_apic_irqs
= ~PIC_IRQS
;
2258 printk("ENABLING IO-APIC IRQs\n");
2261 * Set up IO-APIC IRQ routing.
2264 setup_ioapic_ids_from_mpc();
2266 setup_IO_APIC_irqs();
2267 init_IO_APIC_traps();
2274 * Called after all the initialization is done. If we didnt find any
2275 * APIC bugs then we can allow the modify fast path
2278 static int __init
io_apic_bug_finalize(void)
2280 if(sis_apic_bug
== -1)
2285 late_initcall(io_apic_bug_finalize
);
2287 struct sysfs_ioapic_data
{
2288 struct sys_device dev
;
2289 struct IO_APIC_route_entry entry
[0];
2291 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2293 static int ioapic_suspend(struct sys_device
*dev
, u32 state
)
2295 struct IO_APIC_route_entry
*entry
;
2296 struct sysfs_ioapic_data
*data
;
2297 unsigned long flags
;
2300 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2301 entry
= data
->entry
;
2302 spin_lock_irqsave(&ioapic_lock
, flags
);
2303 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2304 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
2305 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
2307 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2312 static int ioapic_resume(struct sys_device
*dev
)
2314 struct IO_APIC_route_entry
*entry
;
2315 struct sysfs_ioapic_data
*data
;
2316 unsigned long flags
;
2317 union IO_APIC_reg_00 reg_00
;
2320 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2321 entry
= data
->entry
;
2323 spin_lock_irqsave(&ioapic_lock
, flags
);
2324 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2325 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2326 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2327 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2329 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2330 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2331 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2333 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2338 static struct sysdev_class ioapic_sysdev_class
= {
2339 set_kset_name("ioapic"),
2340 .suspend
= ioapic_suspend
,
2341 .resume
= ioapic_resume
,
2344 static int __init
ioapic_init_sysfs(void)
2346 struct sys_device
* dev
;
2347 int i
, size
, error
= 0;
2349 error
= sysdev_class_register(&ioapic_sysdev_class
);
2353 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2354 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2355 * sizeof(struct IO_APIC_route_entry
);
2356 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2357 if (!mp_ioapic_data
[i
]) {
2358 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2361 memset(mp_ioapic_data
[i
], 0, size
);
2362 dev
= &mp_ioapic_data
[i
]->dev
;
2364 dev
->cls
= &ioapic_sysdev_class
;
2365 error
= sysdev_register(dev
);
2367 kfree(mp_ioapic_data
[i
]);
2368 mp_ioapic_data
[i
] = NULL
;
2369 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2377 device_initcall(ioapic_init_sysfs
);
2379 /* --------------------------------------------------------------------------
2380 ACPI-based IOAPIC Configuration
2381 -------------------------------------------------------------------------- */
2383 #ifdef CONFIG_ACPI_BOOT
2385 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2387 union IO_APIC_reg_00 reg_00
;
2388 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2390 unsigned long flags
;
2394 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2395 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2396 * supports up to 16 on one shared APIC bus.
2398 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2399 * advantage of new APIC bus architecture.
2402 if (physids_empty(apic_id_map
))
2403 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2405 spin_lock_irqsave(&ioapic_lock
, flags
);
2406 reg_00
.raw
= io_apic_read(ioapic
, 0);
2407 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2409 if (apic_id
>= get_physical_broadcast()) {
2410 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2411 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2412 apic_id
= reg_00
.bits
.ID
;
2416 * Every APIC in a system must have a unique ID or we get lots of nice
2417 * 'stuck on smp_invalidate_needed IPI wait' messages.
2419 if (check_apicid_used(apic_id_map
, apic_id
)) {
2421 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2422 if (!check_apicid_used(apic_id_map
, i
))
2426 if (i
== get_physical_broadcast())
2427 panic("Max apic_id exceeded!\n");
2429 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2430 "trying %d\n", ioapic
, apic_id
, i
);
2435 tmp
= apicid_to_cpu_present(apic_id
);
2436 physids_or(apic_id_map
, apic_id_map
, tmp
);
2438 if (reg_00
.bits
.ID
!= apic_id
) {
2439 reg_00
.bits
.ID
= apic_id
;
2441 spin_lock_irqsave(&ioapic_lock
, flags
);
2442 io_apic_write(ioapic
, 0, reg_00
.raw
);
2443 reg_00
.raw
= io_apic_read(ioapic
, 0);
2444 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2447 if (reg_00
.bits
.ID
!= apic_id
)
2448 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic
);
2451 apic_printk(APIC_VERBOSE
, KERN_INFO
2452 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2458 int __init
io_apic_get_version (int ioapic
)
2460 union IO_APIC_reg_01 reg_01
;
2461 unsigned long flags
;
2463 spin_lock_irqsave(&ioapic_lock
, flags
);
2464 reg_01
.raw
= io_apic_read(ioapic
, 1);
2465 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2467 return reg_01
.bits
.version
;
2471 int __init
io_apic_get_redir_entries (int ioapic
)
2473 union IO_APIC_reg_01 reg_01
;
2474 unsigned long flags
;
2476 spin_lock_irqsave(&ioapic_lock
, flags
);
2477 reg_01
.raw
= io_apic_read(ioapic
, 1);
2478 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2480 return reg_01
.bits
.entries
;
2484 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2486 struct IO_APIC_route_entry entry
;
2487 unsigned long flags
;
2489 if (!IO_APIC_IRQ(irq
)) {
2490 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2496 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2497 * Note that we mask (disable) IRQs now -- these get enabled when the
2498 * corresponding device driver registers for this IRQ.
2501 memset(&entry
,0,sizeof(entry
));
2503 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2504 entry
.dest_mode
= INT_DEST_MODE
;
2505 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2506 entry
.trigger
= edge_level
;
2507 entry
.polarity
= active_high_low
;
2511 * IRQs < 16 are already in the irq_2_pin[] map
2514 add_pin_to_irq(irq
, ioapic
, pin
);
2516 entry
.vector
= assign_irq_vector(irq
);
2518 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2519 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2520 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2521 edge_level
, active_high_low
);
2523 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2525 if (!ioapic
&& (irq
< 16))
2526 disable_8259A_irq(irq
);
2528 spin_lock_irqsave(&ioapic_lock
, flags
);
2529 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2530 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2531 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2536 #endif /*CONFIG_ACPI_BOOT*/