2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
35 #include <asm/arch_hooks.h>
38 #include <mach_apic.h>
48 static void apic_pm_activate(void);
50 void __init
apic_intr_init(void)
55 /* self generated IPI for local APIC timer */
56 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
58 /* IPI vectors for APIC spurious and error interrupts */
59 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
60 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
62 /* thermal monitor LVT interrupt */
63 #ifdef CONFIG_X86_MCE_P4THERMAL
64 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
68 /* Using APIC to generate smp_local_timer_interrupt? */
69 int using_apic_timer
= 0;
71 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
72 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
73 static DEFINE_PER_CPU(int, prof_counter
) = 1;
75 static int enabled_via_apicbase
;
77 void enable_NMI_through_LVT0 (void * dummy
)
81 ver
= apic_read(APIC_LVR
);
82 ver
= GET_APIC_VERSION(ver
);
83 v
= APIC_DM_NMI
; /* unmask and set to NMI */
84 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
85 v
|= APIC_LVT_LEVEL_TRIGGER
;
86 apic_write_around(APIC_LVT0
, v
);
89 int get_physical_broadcast(void)
91 unsigned int lvr
, version
;
92 lvr
= apic_read(APIC_LVR
);
93 version
= GET_APIC_VERSION(lvr
);
94 if (!APIC_INTEGRATED(version
) || version
>= 0x14)
102 unsigned int v
, ver
, maxlvt
;
104 v
= apic_read(APIC_LVR
);
105 ver
= GET_APIC_VERSION(v
);
106 /* 82489DXs do not report # of LVT entries. */
107 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
111 void clear_local_APIC(void)
116 maxlvt
= get_maxlvt();
119 * Masking an LVT entry on a P6 can trigger a local APIC error
120 * if the vector is zero. Mask LVTERR first to prevent this.
123 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
124 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
127 * Careful: we have to set masks only first to deassert
128 * any level-triggered sources.
130 v
= apic_read(APIC_LVTT
);
131 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
132 v
= apic_read(APIC_LVT0
);
133 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
134 v
= apic_read(APIC_LVT1
);
135 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
137 v
= apic_read(APIC_LVTPC
);
138 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
141 /* lets not touch this if we didn't frob it */
142 #ifdef CONFIG_X86_MCE_P4THERMAL
144 v
= apic_read(APIC_LVTTHMR
);
145 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
149 * Clean APIC state for other OSs:
151 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
152 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
153 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
155 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
157 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
159 #ifdef CONFIG_X86_MCE_P4THERMAL
161 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
163 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
164 if (APIC_INTEGRATED(v
)) { /* !82489DX */
165 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
166 apic_write(APIC_ESR
, 0);
171 void __init
connect_bsp_APIC(void)
175 * Do not trust the local APIC being empty at bootup.
179 * PIC mode, enable APIC mode in the IMCR, i.e.
180 * connect BSP's local APIC to INT and NMI lines.
182 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
183 "enabling APIC mode.\n");
190 void disconnect_bsp_APIC(void)
194 * Put the board back into PIC mode (has an effect
195 * only on certain older boards). Note that APIC
196 * interrupts, including IPIs, won't work beyond
197 * this point! The only exception are INIT IPIs.
199 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
200 "entering PIC mode.\n");
206 void disable_local_APIC(void)
213 * Disable APIC (implies clearing of registers
216 value
= apic_read(APIC_SPIV
);
217 value
&= ~APIC_SPIV_APIC_ENABLED
;
218 apic_write_around(APIC_SPIV
, value
);
220 if (enabled_via_apicbase
) {
222 rdmsr(MSR_IA32_APICBASE
, l
, h
);
223 l
&= ~MSR_IA32_APICBASE_ENABLE
;
224 wrmsr(MSR_IA32_APICBASE
, l
, h
);
229 * This is to verify that we're looking at a real local APIC.
230 * Check these against your board if the CPUs aren't getting
231 * started for no apparent reason.
233 int __init
verify_local_APIC(void)
235 unsigned int reg0
, reg1
;
238 * The version register is read-only in a real APIC.
240 reg0
= apic_read(APIC_LVR
);
241 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
242 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
243 reg1
= apic_read(APIC_LVR
);
244 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
247 * The two version reads above should print the same
248 * numbers. If the second one is different, then we
249 * poke at a non-APIC.
255 * Check if the version looks reasonably.
257 reg1
= GET_APIC_VERSION(reg0
);
258 if (reg1
== 0x00 || reg1
== 0xff)
261 if (reg1
< 0x02 || reg1
== 0xff)
265 * The ID register is read/write in a real APIC.
267 reg0
= apic_read(APIC_ID
);
268 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
271 * The next two are just to see if we have sane values.
272 * They're only really relevant if we're in Virtual Wire
273 * compatibility mode, but most boxes are anymore.
275 reg0
= apic_read(APIC_LVT0
);
276 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
277 reg1
= apic_read(APIC_LVT1
);
278 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
283 void __init
sync_Arb_IDs(void)
288 apic_wait_icr_idle();
290 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
291 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
295 extern void __error_in_apic_c (void);
298 * An initial setup of the virtual wire mode.
300 void __init
init_bsp_APIC(void)
302 unsigned long value
, ver
;
305 * Don't do the setup now if we have a SMP BIOS as the
306 * through-I/O-APIC virtual wire mode might be active.
308 if (smp_found_config
|| !cpu_has_apic
)
311 value
= apic_read(APIC_LVR
);
312 ver
= GET_APIC_VERSION(value
);
315 * Do not trust the local APIC being empty at bootup.
322 value
= apic_read(APIC_SPIV
);
323 value
&= ~APIC_VECTOR_MASK
;
324 value
|= APIC_SPIV_APIC_ENABLED
;
326 /* This bit is reserved on P4/Xeon and should be cleared */
327 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
328 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
330 value
|= APIC_SPIV_FOCUS_DISABLED
;
331 value
|= SPURIOUS_APIC_VECTOR
;
332 apic_write_around(APIC_SPIV
, value
);
335 * Set up the virtual wire mode.
337 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
339 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
340 value
|= APIC_LVT_LEVEL_TRIGGER
;
341 apic_write_around(APIC_LVT1
, value
);
344 void __init
setup_local_APIC (void)
346 unsigned long oldvalue
, value
, ver
, maxlvt
;
348 /* Pound the ESR really hard over the head with a big hammer - mbligh */
350 apic_write(APIC_ESR
, 0);
351 apic_write(APIC_ESR
, 0);
352 apic_write(APIC_ESR
, 0);
353 apic_write(APIC_ESR
, 0);
356 value
= apic_read(APIC_LVR
);
357 ver
= GET_APIC_VERSION(value
);
359 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
363 * Double-check whether this APIC is really registered.
365 if (!apic_id_registered())
369 * Intel recommends to set DFR, LDR and TPR before enabling
370 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
371 * document number 292116). So here it goes...
376 * Set Task Priority to 'accept all'. We never change this
379 value
= apic_read(APIC_TASKPRI
);
380 value
&= ~APIC_TPRI_MASK
;
381 apic_write_around(APIC_TASKPRI
, value
);
384 * Now that we are all set up, enable the APIC
386 value
= apic_read(APIC_SPIV
);
387 value
&= ~APIC_VECTOR_MASK
;
391 value
|= APIC_SPIV_APIC_ENABLED
;
394 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
395 * certain networking cards. If high frequency interrupts are
396 * happening on a particular IOAPIC pin, plus the IOAPIC routing
397 * entry is masked/unmasked at a high rate as well then sooner or
398 * later IOAPIC line gets 'stuck', no more interrupts are received
399 * from the device. If focus CPU is disabled then the hang goes
402 * [ This bug can be reproduced easily with a level-triggered
403 * PCI Ne2000 networking cards and PII/PIII processors, dual
407 * Actually disabling the focus CPU check just makes the hang less
408 * frequent as it makes the interrupt distributon model be more
409 * like LRU than MRU (the short-term load is more even across CPUs).
410 * See also the comment in end_level_ioapic_irq(). --macro
413 /* Enable focus processor (bit==0) */
414 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
416 /* Disable focus processor (bit==1) */
417 value
|= APIC_SPIV_FOCUS_DISABLED
;
420 * Set spurious IRQ vector
422 value
|= SPURIOUS_APIC_VECTOR
;
423 apic_write_around(APIC_SPIV
, value
);
428 * set up through-local-APIC on the BP's LINT0. This is not
429 * strictly necessery in pure symmetric-IO mode, but sometimes
430 * we delegate interrupts to the 8259A.
433 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
435 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
436 if (!smp_processor_id() && (pic_mode
|| !value
)) {
437 value
= APIC_DM_EXTINT
;
438 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
441 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
442 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
445 apic_write_around(APIC_LVT0
, value
);
448 * only the BP should see the LINT1 NMI signal, obviously.
450 if (!smp_processor_id())
453 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
454 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
455 value
|= APIC_LVT_LEVEL_TRIGGER
;
456 apic_write_around(APIC_LVT1
, value
);
458 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
459 maxlvt
= get_maxlvt();
460 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
461 apic_write(APIC_ESR
, 0);
462 oldvalue
= apic_read(APIC_ESR
);
464 value
= ERROR_APIC_VECTOR
; // enables sending errors
465 apic_write_around(APIC_LVTERR
, value
);
467 * spec says clear errors after enabling vector.
470 apic_write(APIC_ESR
, 0);
471 value
= apic_read(APIC_ESR
);
472 if (value
!= oldvalue
)
473 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
474 "vector: 0x%08lx after: 0x%08lx\n",
479 * Something untraceble is creating bad interrupts on
480 * secondary quads ... for the moment, just leave the
481 * ESR disabled - we can't do anything useful with the
482 * errors anyway - mbligh
484 printk("Leaving ESR disabled.\n");
486 printk("No ESR for 82489DX.\n");
489 if (nmi_watchdog
== NMI_LOCAL_APIC
)
490 setup_apic_nmi_watchdog();
497 /* 'active' is true if the local APIC was enabled by us and
498 not the BIOS; this signifies that we are also responsible
499 for disabling it before entering apm/acpi suspend */
501 /* r/w apic fields */
502 unsigned int apic_id
;
503 unsigned int apic_taskpri
;
504 unsigned int apic_ldr
;
505 unsigned int apic_dfr
;
506 unsigned int apic_spiv
;
507 unsigned int apic_lvtt
;
508 unsigned int apic_lvtpc
;
509 unsigned int apic_lvt0
;
510 unsigned int apic_lvt1
;
511 unsigned int apic_lvterr
;
512 unsigned int apic_tmict
;
513 unsigned int apic_tdcr
;
514 unsigned int apic_thmr
;
517 static int lapic_suspend(struct sys_device
*dev
, u32 state
)
521 if (!apic_pm_state
.active
)
524 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
525 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
526 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
527 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
528 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
529 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
530 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
531 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
532 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
533 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
534 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
535 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
536 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
538 local_irq_save(flags
);
539 disable_local_APIC();
540 local_irq_restore(flags
);
544 static int lapic_resume(struct sys_device
*dev
)
549 if (!apic_pm_state
.active
)
552 local_irq_save(flags
);
555 * Make sure the APICBASE points to the right address
557 * FIXME! This will be wrong if we ever support suspend on
558 * SMP! We'll need to do this as part of the CPU restore!
560 rdmsr(MSR_IA32_APICBASE
, l
, h
);
561 l
&= ~MSR_IA32_APICBASE_BASE
;
562 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
563 wrmsr(MSR_IA32_APICBASE
, l
, h
);
565 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
566 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
567 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
568 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
569 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
570 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
571 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
572 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
573 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
574 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
575 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
576 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
577 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
578 apic_write(APIC_ESR
, 0);
580 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
581 apic_write(APIC_ESR
, 0);
583 local_irq_restore(flags
);
588 static struct sysdev_class lapic_sysclass
= {
589 set_kset_name("lapic"),
590 .resume
= lapic_resume
,
591 .suspend
= lapic_suspend
,
594 static struct sys_device device_lapic
= {
596 .cls
= &lapic_sysclass
,
599 static void __init
apic_pm_activate(void)
601 apic_pm_state
.active
= 1;
604 static int __init
init_lapic_sysfs(void)
610 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
612 error
= sysdev_class_register(&lapic_sysclass
);
614 error
= sysdev_register(&device_lapic
);
617 device_initcall(init_lapic_sysfs
);
619 #else /* CONFIG_PM */
621 static void apic_pm_activate(void) { }
623 #endif /* CONFIG_PM */
626 * Detect and enable local APICs on non-SMP boards.
627 * Original code written by Keir Fraser.
631 * Knob to control our willingness to enable the local APIC.
633 int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
635 static int __init
lapic_disable(char *str
)
637 enable_local_apic
= -1;
638 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
641 __setup("nolapic", lapic_disable
);
643 static int __init
lapic_enable(char *str
)
645 enable_local_apic
= 1;
648 __setup("lapic", lapic_enable
);
650 static int __init
apic_set_verbosity(char *str
)
652 if (strcmp("debug", str
) == 0)
653 apic_verbosity
= APIC_DEBUG
;
654 else if (strcmp("verbose", str
) == 0)
655 apic_verbosity
= APIC_VERBOSE
;
657 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
658 " use apic=verbose or apic=debug", str
);
663 __setup("apic=", apic_set_verbosity
);
665 static int __init
detect_init_APIC (void)
668 extern void get_cpu_vendor(struct cpuinfo_x86
*);
670 /* Disabled by DMI scan or kernel option? */
671 if (enable_local_apic
< 0)
674 /* Workaround for us being called before identify_cpu(). */
675 get_cpu_vendor(&boot_cpu_data
);
677 switch (boot_cpu_data
.x86_vendor
) {
679 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
680 (boot_cpu_data
.x86
== 15))
683 case X86_VENDOR_INTEL
:
684 if (boot_cpu_data
.x86
== 6 ||
685 (boot_cpu_data
.x86
== 15 && (cpu_has_apic
|| enable_local_apic
> 0)) ||
686 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
695 * Over-ride BIOS and try to enable LAPIC
696 * only if "lapic" specified
698 if (enable_local_apic
!= 1)
701 * Some BIOSes disable the local APIC in the
702 * APIC_BASE MSR. This can only be done in
703 * software for Intel P6 and AMD K7 (Model > 1).
705 rdmsr(MSR_IA32_APICBASE
, l
, h
);
706 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
707 apic_printk(APIC_VERBOSE
, "Local APIC disabled "
708 "by BIOS -- reenabling.\n");
709 l
&= ~MSR_IA32_APICBASE_BASE
;
710 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
711 wrmsr(MSR_IA32_APICBASE
, l
, h
);
712 enabled_via_apicbase
= 1;
716 * The APIC feature bit should now be enabled
719 features
= cpuid_edx(1);
720 if (!(features
& (1 << X86_FEATURE_APIC
))) {
721 printk("Could not enable APIC!\n");
724 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
725 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
727 /* The BIOS may have set up the APIC at some other address */
728 rdmsr(MSR_IA32_APICBASE
, l
, h
);
729 if (l
& MSR_IA32_APICBASE_ENABLE
)
730 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
732 if (nmi_watchdog
!= NMI_NONE
)
733 nmi_watchdog
= NMI_LOCAL_APIC
;
735 apic_printk(APIC_VERBOSE
, "Found and enabled local APIC!\n");
742 printk("No local APIC present or hardware disabled\n");
746 void __init
init_apic_mappings(void)
748 unsigned long apic_phys
;
751 * If no local APIC can be found then set up a fake all
752 * zeroes page to simulate the local APIC and another
753 * one for the IO-APIC.
755 if (!smp_found_config
&& detect_init_APIC()) {
756 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
757 apic_phys
= __pa(apic_phys
);
759 apic_phys
= mp_lapic_addr
;
761 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
762 apic_printk(APIC_DEBUG
, "mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
766 * Fetch the APIC ID of the BSP in case we have a
767 * default configuration (or the MP table is broken).
769 if (boot_cpu_physical_apicid
== -1U)
770 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
772 #ifdef CONFIG_X86_IO_APIC
774 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
777 for (i
= 0; i
< nr_ioapics
; i
++) {
778 if (smp_found_config
) {
779 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
781 printk(KERN_ERR
"WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO/APIC support!\n");
783 smp_found_config
= 0;
784 skip_ioapic_setup
= 1;
785 goto fake_ioapic_page
;
789 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
790 ioapic_phys
= __pa(ioapic_phys
);
792 set_fixmap_nocache(idx
, ioapic_phys
);
793 apic_printk(APIC_DEBUG
, "mapped IOAPIC to "
795 __fix_to_virt(idx
), ioapic_phys
);
803 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
804 * per second. We assume that the caller has already set up the local
807 * The APIC timer is not exactly sync with the external timer chip, it
808 * closely follows bus clocks.
812 * The timer chip is already set up at HZ interrupts per second here,
813 * but we do not accept timer interrupts yet. We only allow the BP
816 static unsigned int __init
get_8254_timer_count(void)
818 extern spinlock_t i8253_lock
;
823 spin_lock_irqsave(&i8253_lock
, flags
);
825 outb_p(0x00, PIT_MODE
);
826 count
= inb_p(PIT_CH0
);
827 count
|= inb_p(PIT_CH0
) << 8;
829 spin_unlock_irqrestore(&i8253_lock
, flags
);
834 /* next tick in 8254 can be caught by catching timer wraparound */
835 static void __init
wait_8254_wraparound(void)
837 unsigned int curr_count
, prev_count
=~0;
840 curr_count
= get_8254_timer_count();
843 prev_count
= curr_count
;
844 curr_count
= get_8254_timer_count();
845 delta
= curr_count
-prev_count
;
848 * This limit for delta seems arbitrary, but it isn't, it's
849 * slightly above the level of error a buggy Mercury/Neptune
850 * chipset timer can cause.
853 } while (delta
< 300);
857 * Default initialization for 8254 timers. If we use other timers like HPET,
858 * we override this later
860 void (*wait_timer_tick
)(void) = wait_8254_wraparound
;
863 * This function sets up the local APIC timer, with a timeout of
864 * 'clocks' APIC bus clock. During calibration we actually call
865 * this function twice on the boot CPU, once with a bogus timeout
866 * value, second time for real. The other (noncalibrating) CPUs
867 * call this function only once, with the real, calibrated value.
869 * We do reads before writes even if unnecessary, to get around the
870 * P5 APIC double write bug.
873 #define APIC_DIVISOR 16
875 void __setup_APIC_LVTT(unsigned int clocks
)
877 unsigned int lvtt_value
, tmp_value
, ver
;
879 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
880 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
881 if (!APIC_INTEGRATED(ver
))
882 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
883 apic_write_around(APIC_LVTT
, lvtt_value
);
888 tmp_value
= apic_read(APIC_TDCR
);
889 apic_write_around(APIC_TDCR
, (tmp_value
890 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
893 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
896 static void setup_APIC_timer(unsigned int clocks
)
900 local_irq_save(flags
);
903 * Wait for IRQ0's slice:
907 __setup_APIC_LVTT(clocks
);
909 local_irq_restore(flags
);
913 * In this function we calibrate APIC bus clocks to the external
914 * timer. Unfortunately we cannot use jiffies and the timer irq
915 * to calibrate, since some later bootup code depends on getting
916 * the first irq? Ugh.
918 * We want to do the calibration only once since we
919 * want to have local timer irqs syncron. CPUs connected
920 * by the same APIC bus have the very same bus frequency.
921 * And we want to have irqs off anyways, no accidental
925 int __init
calibrate_APIC_clock(void)
927 unsigned long long t1
= 0, t2
= 0;
931 const int LOOPS
= HZ
/10;
933 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
936 * Put whatever arbitrary (but long enough) timeout
937 * value into the APIC clock, we just want to get the
938 * counter running for calibration.
940 __setup_APIC_LVTT(1000000000);
943 * The timer chip counts down to zero. Let's wait
944 * for a wraparound to start exact measurement:
945 * (the current tick might have been already half done)
951 * We wrapped around just now. Let's start:
955 tt1
= apic_read(APIC_TMCCT
);
958 * Let's wait LOOPS wraprounds:
960 for (i
= 0; i
< LOOPS
; i
++)
963 tt2
= apic_read(APIC_TMCCT
);
968 * The APIC bus clock counter is 32 bits only, it
969 * might have overflown, but note that we use signed
970 * longs, thus no extra care needed.
972 * underflown to be exact, as the timer counts down ;)
975 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
978 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
980 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
981 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
983 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
986 result
%(1000000/HZ
));
991 static unsigned int calibration_result
;
993 void __init
setup_boot_APIC_clock(void)
995 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
996 using_apic_timer
= 1;
1000 calibration_result
= calibrate_APIC_clock();
1002 * Now set up the timer for real.
1004 setup_APIC_timer(calibration_result
);
1009 void __init
setup_secondary_APIC_clock(void)
1011 local_irq_disable(); /* FIXME: Do we need this? --RR */
1012 setup_APIC_timer(calibration_result
);
1016 void __init
disable_APIC_timer(void)
1018 if (using_apic_timer
) {
1021 v
= apic_read(APIC_LVTT
);
1022 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1026 void enable_APIC_timer(void)
1028 if (using_apic_timer
) {
1031 v
= apic_read(APIC_LVTT
);
1032 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1037 * the frequency of the profiling timer can be changed
1038 * by writing a multiplier value into /proc/profile.
1040 int setup_profiling_timer(unsigned int multiplier
)
1045 * Sanity check. [at least 500 APIC cycles should be
1046 * between APIC interrupts as a rule of thumb, to avoid
1049 if ( (!multiplier
) || (calibration_result
/multiplier
< 500))
1053 * Set the new multiplier for each CPU. CPUs don't start using the
1054 * new values until the next timer interrupt in which they do process
1055 * accounting. At that time they also adjust their APIC timers
1058 for (i
= 0; i
< NR_CPUS
; ++i
)
1059 per_cpu(prof_multiplier
, i
) = multiplier
;
1067 * Local timer interrupt handler. It does both profiling and
1068 * process statistics/rescheduling.
1070 * We do profiling in every local tick, statistics/rescheduling
1071 * happen only every 'profiling multiplier' ticks. The default
1072 * multiplier is 1 and it can be changed by writing the new multiplier
1073 * value into /proc/profile.
1076 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
1078 int cpu
= smp_processor_id();
1080 profile_tick(CPU_PROFILING
, regs
);
1081 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1083 * The multiplier may have changed since the last time we got
1084 * to this point as a result of the user writing to
1085 * /proc/profile. In this case we need to adjust the APIC
1086 * timer accordingly.
1088 * Interrupts are already masked off at this point.
1090 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1091 if (per_cpu(prof_counter
, cpu
) !=
1092 per_cpu(prof_old_multiplier
, cpu
)) {
1095 per_cpu(prof_counter
, cpu
));
1096 per_cpu(prof_old_multiplier
, cpu
) =
1097 per_cpu(prof_counter
, cpu
);
1101 update_process_times(user_mode(regs
));
1106 * We take the 'long' return path, and there every subsystem
1107 * grabs the apropriate locks (kernel lock/ irq lock).
1109 * we might want to decouple profiling from the 'long path',
1110 * and do the profiling totally in assembly.
1112 * Currently this isn't too much of an issue (performance wise),
1113 * we can take more than 100K local irqs per second on a 100 MHz P5.
1118 * Local APIC timer interrupt. This is the most natural way for doing
1119 * local interrupts, but local timer interrupts can be emulated by
1120 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1122 * [ if a single-CPU system runs an SMP kernel then we call the local
1123 * interrupt as well. Thus we cannot inline the local irq ... ]
1126 void smp_apic_timer_interrupt(struct pt_regs regs
)
1128 int cpu
= smp_processor_id();
1131 * the NMI deadlock-detector uses this.
1133 irq_stat
[cpu
].apic_timer_irqs
++;
1136 * NOTE! We'd better ACK the irq immediately,
1137 * because timer handling can be slow.
1141 * update_process_times() expects us to have done irq_enter().
1142 * Besides, if we don't timer interrupts ignore the global
1143 * interrupt lock, which is the WrongThing (tm) to do.
1146 smp_local_timer_interrupt(®s
);
1151 * This interrupt should _never_ happen with our APIC/SMP architecture
1153 asmlinkage
void smp_spurious_interrupt(void)
1159 * Check if this really is a spurious interrupt and ACK it
1160 * if it is a vectored one. Just in case...
1161 * Spurious interrupts should not be ACKed.
1163 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1164 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1167 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1168 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1169 smp_processor_id());
1174 * This interrupt should never happen with our APIC/SMP architecture
1177 asmlinkage
void smp_error_interrupt(void)
1179 unsigned long v
, v1
;
1182 /* First tickle the hardware, only then report what went on. -- REW */
1183 v
= apic_read(APIC_ESR
);
1184 apic_write(APIC_ESR
, 0);
1185 v1
= apic_read(APIC_ESR
);
1187 atomic_inc(&irq_err_count
);
1189 /* Here is what the APIC error bits mean:
1192 2: Send accept error
1193 3: Receive accept error
1195 5: Send illegal vector
1196 6: Received illegal vector
1197 7: Illegal register address
1199 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1200 smp_processor_id(), v
, v1
);
1205 * This initializes the IO-APIC and APIC hardware if this is
1208 int __init
APIC_init_uniprocessor (void)
1210 if (enable_local_apic
< 0)
1211 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1213 if (!smp_found_config
&& !cpu_has_apic
)
1217 * Complain if the BIOS pretends there is one.
1219 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1220 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1221 boot_cpu_physical_apicid
);
1225 verify_local_APIC();
1229 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1233 if (nmi_watchdog
== NMI_LOCAL_APIC
)
1234 check_nmi_watchdog();
1235 #ifdef CONFIG_X86_IO_APIC
1236 if (smp_found_config
)
1237 if (!skip_ioapic_setup
&& nr_ioapics
)
1240 setup_boot_APIC_clock();