1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
21 * %g7: physical address base of the linux page
22 * tables for the current address space
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
38 tsb_miss_page_table_walk:
39 /* This clobbers %g1 and %g6, preserve them... */
48 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
51 TSB_LOCK_TAG(%g1, %g2, %g4)
53 /* Load and check PTE. */
54 ldxa [%g5] ASI_PHYS_USE_EC, %g5
55 brgez,a,pn %g5, tsb_do_fault
58 /* If it is larger than the base page size, don't
59 * bother putting it into the TSB.
62 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g4
63 sethi %hi(_PAGE_SZBITS >> 32), %g7
66 bne,a,pn %xcc, tsb_tlb_reload
69 TSB_WRITE(%g1, %g5, %g6)
71 /* Finally, load TLB and return from trap. */
73 cmp %g3, FAULT_CODE_DTLB
74 bne,pn %xcc, tsb_itlb_load
78 stxa %g5, [%g0] ASI_DTLB_DATA_IN
82 stxa %g5, [%g0] ASI_ITLB_DATA_IN
85 /* No valid entry in the page tables, do full fault
91 cmp %g3, FAULT_CODE_DTLB
93 bne,pn %xcc, tsb_do_itlb_fault
94 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
99 mov TLB_TAG_ACCESS, %g4
100 ldxa [%g4] ASI_DMMU, %g5
101 be,pt %xcc, sparc64_realfault_common
102 mov FAULT_CODE_DTLB, %g4
103 ba,pt %xcc, winfix_trampoline
108 ba,pt %xcc, sparc64_realfault_common
109 mov FAULT_CODE_ITLB, %g4
111 .globl sparc64_realfault_common
112 sparc64_realfault_common:
113 /* fault code in %g4, fault address in %g5, etrap will
114 * preserve these two values in %l4 and %l5 respectively
116 ba,pt %xcc, etrap ! Save trap state
118 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
119 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
120 call do_sparc64_fault ! Call fault handler
121 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
122 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
123 nop ! Delay slot (fill me)
125 .globl winfix_trampoline
127 rdpr %tpc, %g3 ! Prepare winfixup TNPC
128 or %g3, 0x7c, %g3 ! Compute branch offset
129 wrpr %g3, %tnpc ! Write it into TNPC
132 /* Insert an entry into the TSB.
134 * %o0: TSB entry pointer (virt or phys address)
142 wrpr %o5, PSTATE_IE, %pstate
143 TSB_LOCK_TAG(%o0, %g2, %g3)
144 TSB_WRITE(%o0, %o2, %o1)
149 /* Flush the given TSB entry if it has the matching
152 * %o0: TSB entry pointer (virt or phys address)
158 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
159 1: TSB_LOAD_TAG(%o0, %g1)
167 TSB_CAS_TAG(%o0, %g1, %o3)
174 /* Reload MMU related context switch state at
177 * %o0: page table physical address
178 * %o1: TSB register value
179 * %o2: TSB virtual address
180 * %o3: TSB mapping locked PTE
182 * We have to run this whole thing with interrupts
183 * disabled so that the current cpu doesn't change
187 .globl __tsb_context_switch
188 __tsb_context_switch:
190 wrpr %o5, PSTATE_IE, %pstate
192 ldub [%g6 + TI_CPU], %g1
193 sethi %hi(trap_block), %g2
194 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
195 or %g2, %lo(trap_block), %g2
197 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
200 stxa %o1, [%g1] ASI_DMMU
203 stxa %o1, [%g1] ASI_IMMU
209 sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4
210 mov TLB_TAG_ACCESS, %g1
211 lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
212 stxa %o2, [%g1] ASI_DMMU
215 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS