Xilinx: ARM: update interrupts in device trees
commit685be2e849c206f1d42f5fb89cc761065a557a30
authorJohn Linn <john.linn@xilinx.com>
Thu, 23 Aug 2012 22:02:22 +0000 (23 15:02 -0700)
committerJohn Linn <john.linn@xilinx.com>
Thu, 23 Aug 2012 22:02:22 +0000 (23 15:02 -0700)
tree37e8e4330e163ba67cea2998278931a20f2ed270
parent15623db92ebef4e643b138f533961b553a7653d1
Xilinx: ARM: update interrupts in device trees

The interrupt properties were using the wrong trigger type
and this corrects them. Most should be active high level.
The SCU devices are leading edge triggered and also have a
mask for the CPUs that can accept the interrupts.

Signed-off-by: John Linn <john.linn@xilinx.com>
arch/arm/boot/dts/zynq-zc702.dts
arch/arm/boot/dts/zynq-zc706.dts
arch/arm/boot/dts/zynq-zc770-xm010.dts
arch/arm/boot/dts/zynq-zc770-xm011.dts
arch/arm/boot/dts/zynq-zc770-xm012.dts
arch/arm/boot/dts/zynq-zc770-xm013.dts