From a99eea300dedf979e4328a9d92a533597f185ba5 Mon Sep 17 00:00:00 2001 From: jethead71 Date: Tue, 5 Feb 2008 04:43:19 +0000 Subject: [PATCH] Gigabeat S mixer: Make some progress. Get the tick and core sleep working using the AVIC. Redo the startup code to remap from IRAM and not include the lcd driver frambuffer in the remapping (until it can be moved). Clean up LCD driver. For other misc. changes, see the diffs. Now it progresses to ATA init and fails with -11 but without crashing or hanging. Replace all bootloaders. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16216 a1c6a512-1295-4272-9138-f99709370657 --- bootloader/gigabeat-s.c | 3 +- firmware/SOURCES | 13 +- firmware/app.lds | 9 +- firmware/boot.lds | 70 +- firmware/export/imx31l.h | 990 +++++++++++---------- firmware/kernel.c | 42 - firmware/target/arm/imx31/crt0.S | 422 ++++----- firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | 403 ++++----- firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | 180 ++-- .../target/arm/imx31/gigabeat-s/kernel-imx31.c | 55 +- .../target/arm/imx31/gigabeat-s/lcd-as-imx31.S | 222 ----- firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c | 224 ++--- firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c | 4 + firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c | 8 - .../target/arm/imx31/gigabeat-s/system-imx31.c | 18 +- .../target/arm/imx31/gigabeat-s/system-target.h | 20 +- firmware/thread.c | 15 + 17 files changed, 1190 insertions(+), 1508 deletions(-) rewrite firmware/export/imx31l.h (71%) rewrite firmware/target/arm/imx31/gigabeat-s/avic-imx31.c (84%) rewrite firmware/target/arm/imx31/gigabeat-s/avic-imx31.h (64%) delete mode 100644 firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S diff --git a/bootloader/gigabeat-s.c b/bootloader/gigabeat-s.c index 1c07598fa..a4e6391c7 100644 --- a/bootloader/gigabeat-s.c +++ b/bootloader/gigabeat-s.c @@ -57,7 +57,7 @@ void main(void) { lcd_clear_display(); printf("Hello world!"); - printf("Gigabeat S Rockbox Bootloader v.00000001"); + printf("Gigabeat S Rockbox Bootloader v.00000002"); kernel_init(); printf("kernel init done"); int rc; @@ -118,6 +118,7 @@ void main(void) if (rc == EOK) { kernel_entry = (void*) loadbuffer; + invalidate_icache(); rc = kernel_entry(); } diff --git a/firmware/SOURCES b/firmware/SOURCES index 933057614..266c3d1f3 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -609,24 +609,25 @@ target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c #ifdef GIGABEAT_S #ifndef SIMULATOR +target/arm/lcd-as-memframe.S target/arm/mmu-arm.c target/arm/imx31/gigabeat-s/adc-imx31.c target/arm/imx31/gigabeat-s/ata-imx31.c +target/arm/imx31/gigabeat-s/avic-imx31.c target/arm/imx31/gigabeat-s/backlight-imx31.c target/arm/imx31/gigabeat-s/button-imx31.c +target/arm/imx31/gigabeat-s/dma_start.c +target/arm/imx31/gigabeat-s/kernel-imx31.c target/arm/imx31/gigabeat-s/i2c-imx31.c target/arm/imx31/gigabeat-s/i2s-imx31.c -target/arm/imx31/gigabeat-s/lcd-as-imx31.S target/arm/imx31/gigabeat-s/lcd-imx31.c +target/arm/imx31/gigabeat-s/mmu-imx31.c target/arm/imx31/gigabeat-s/power-imx31.c target/arm/imx31/gigabeat-s/powermgmt-imx31.c +target/arm/imx31/gigabeat-s/spi-imx31.c +target/arm/imx31/gigabeat-s/system-imx31.c target/arm/imx31/gigabeat-s/usb-imx31.c target/arm/imx31/gigabeat-s/wmcodec-imx31.c -target/arm/imx31/gigabeat-s/dma_start.c -target/arm/imx31/gigabeat-s/system-imx31.c -target/arm/imx31/gigabeat-s/mmu-imx31.c -target/arm/imx31/gigabeat-s/avic-imx31.c -target/arm/imx31/gigabeat-s/spi-imx31.c #ifndef BOOTLOADER target/arm/imx31/gigabeat-s/pcm-imx31.c #endif diff --git a/firmware/app.lds b/firmware/app.lds index c5c4e6e30..a02d0a3b5 100644 --- a/firmware/app.lds +++ b/firmware/app.lds @@ -39,6 +39,9 @@ INPUT(target/sh/crt0.o) #if CONFIG_CPU==S3C2440 #include "s3c2440.h" #define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE +#elif CONFIG_CPU==IMX31L +#include "imx31l.h" +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE - TTB_SIZE #elif CONFIG_CPU==DM320 #include "dm320.h" #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE @@ -76,6 +79,8 @@ INPUT(target/sh/crt0.o) #elif CONFIG_CPU==IMX31L #define DRAMORIG (0x0 + STUBOFFSET) #define IRAMORIG 0x1FFFC000 +#define IRAMORIG DRAMORIG +#define IRAM DRAM #define IRAMSIZE 0x4000 #elif defined(CPU_TCC780X) #define DRAMORIG 0x20000000 + STUBOFFSET @@ -105,7 +110,7 @@ MEMORY ITCM : ORIGIN = ITCMORIG, LENGTH = ITCMSIZE DTCM : ORIGIN = DTCMORIG, LENGTH = DTCMSIZE SRAM : ORIGIN = SRAMORIG, LENGTH = SRAMSIZE -#elif CONFIG_CPU != S3C2440 +#elif CONFIG_CPU != S3C2440 && CONFIG_CPU != IMX31L IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE #endif #if CONFIG_CPU==PNX0101 @@ -296,7 +301,7 @@ SECTIONS _end = .; } > DRAM -#elif CONFIG_CPU==S3C2440 +#elif CONFIG_CPU==S3C2440 || CONFIG_CPU == IMX31L .text : { loadaddress = .; diff --git a/firmware/boot.lds b/firmware/boot.lds index 8d7d55a60..c0f19bc43 100644 --- a/firmware/boot.lds +++ b/firmware/boot.lds @@ -302,37 +302,47 @@ SECTIONS } #elif (CONFIG_CPU==IMX31L) { - . = 0x8a000000; - .vectors : - { - KEEP(*(.vectors*)); - *(.vectors*); - } - .text : { - *(.init.text) - *(.text*) - } - .data : { - *(.icode) - *(.irodata) - *(.idata) - *(.data*) - _dataend = . ; +#if 0 + .vectors 0x0 : + { + _vectorsstart = .; + *(.vectors); + _vectorsend = .; + } AT> DRAM +#endif + . = 0x82000000; + + .text : + { + *(.init.text) + *(.text*) } - .stack : - { - *(.stack) - _stackbegin = .; - stackbegin = .; - . += 0x2000; - _stackend = .; - stackend = .; - } - .bss : { - _edata = .; - *(.bss*); - *(.ibss); - _end = .; + + .data : + { + *(.icode) + *(.irodata) + *(.idata) + *(.data*) + _dataend = . ; + } + + .stack : + { + *(.stack) + _stackbegin = .; + stackbegin = .; + . += 0x2000; + _stackend = .; + stackend = .; + } + + .bss : + { + _edata = .; + *(.bss*); + *(.ibss); + _end = .; } } #else diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h dissimilarity index 71% index 2bcb3492f..4cc51e9bc 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h @@ -1,476 +1,514 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2006 by James Espinoza - * - * All files in this archive are subject to the GNU General Public License. - * See the file COPYING in the source tree root for full license agreement. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ - -#define L2CC_BASE_ADDR 0x30000000 - -/*Frame Buffer and TTB defines from gigabeat f/x build*/ -#define LCDSADDR1 (*(volatile int *)0x80100000) /* STN/TFT: frame buffer start address 1 */ -#define FRAME1 ((short *)0x80100000) //Foreground FB -#define FRAME2 ((short *)0x84100000) //Background FB - Set to Graphic Window, hence the reason why text is only visible - //when background memory is written. -#define LCD_BUFFER_SIZE ((320*240*2)) -#define TTB_SIZE (0x4000) -#define TTB_BASE ((unsigned int *)(0x88000000 + (64*1024*1024)-TTB_SIZE)) -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x43F00000 -#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR -#define MAX_BASE_ADDR 0x43F04000 -#define EVTMON_BASE_ADDR 0x43F08000 -#define CLKCTL_BASE_ADDR 0x43F0C000 -#define ETB_SLOT4_BASE_ADDR 0x43F10000 -#define ETB_SLOT5_BASE_ADDR 0x43F14000 -#define ECT_CTIO_BASE_ADDR 0x43F18000 -#define I2C_BASE_ADDR 0x43F80000 -#define I2C3_BASE_ADDR 0x43F84000 -#define OTG_BASE_ADDR 0x43F88000 -#define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE_ADDR 0x43F90000 -#define UART2_BASE_ADDR 0x43F94000 -#define I2C2_BASE_ADDR 0x43F98000 -#define OWIRE_BASE_ADDR 0x43F9C000 -#define SSI1_BASE_ADDR 0x43FA0000 -#define CSPI1_BASE_ADDR 0x43FA4000 -#define KPP_BASE_ADDR 0x43FA8000 -#define IOMUXC_BASE_ADDR 0x43FAC000 -#define UART4_BASE_ADDR 0x43FB0000 -#define UART5_BASE_ADDR 0x43FB4000 -#define ECT_IP1_BASE_ADDR 0x43FB8000 -#define ECT_IP2_BASE_ADDR 0x43FBC000 - -/* - * SPBA - */ -#define SPBA_BASE_ADDR 0x50000000 -#define MMC_SDHC1_BASE_ADDR 0x50004000 -#define MMC_SDHC2_BASE_ADDR 0x50008000 -#define UART3_BASE_ADDR 0x5000C000 -#define CSPI2_BASE_ADDR 0x50010000 -#define SSI2_BASE_ADDR 0x50014000 -#define SIM_BASE_ADDR 0x50018000 -#define IIM_BASE_ADDR 0x5001C000 -#define ATA_DMA_BASE_ADDR 0x50020000 -#define SPBA_CTRL_BASE_ADDR 0x5003C000 - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x53F00000 -#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR -#define CCM_BASE_ADDR 0x53F80000 -#define FIRI_BASE_ADDR 0x53F8C000 -#define GPT1_BASE_ADDR 0x53F90000 -#define EPIT1_BASE_ADDR 0x53F94000 -#define EPIT2_BASE_ADDR 0x53F98000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define SCC_BASE 0x53FAC000 -#define SCM_BASE 0x53FAE000 -#define SMN_BASE 0x53FAF000 -#define RNGA_BASE_ADDR 0x53FB0000 -#define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define AUDMUX_BASE 0x53FC4000 -#define MPEG4_ENC_BASE 0x53FC8000 -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define SDMA_BASE_ADDR 0x53FD4000 -#define RTC_BASE_ADDR 0x53FD8000 -#define WDOG_BASE_ADDR 0x53FDC000 -#define PWM_BASE_ADDR 0x53FE0000 -#define RTIC_BASE_ADDR 0x53FEC000 - -#define WDOG1_BASE_ADDR WDOG_BASE_ADDR -#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR - -/* ATA */ -#define TIME_OFF (*(volatile unsigned char*)0x43F8C000) -#define TIME_ON (*(volatile unsigned char*)0x43F8C001) -#define TIME_1 (*(volatile unsigned char*)0x43F8C002) -#define TIME_2W (*(volatile unsigned char*)0x43F8C003) -#define TIME_2R (*(volatile unsigned char*)0x43F8C004) -#define TIME_AX (*(volatile unsigned char*)0x43F8C005) -#define TIME_PIO_RDX (*(volatile unsigned char*)0x43F8C00F) -#define TIME_4 (*(volatile unsigned char*)0x43F8C007) -#define TIME_9 (*(volatile unsigned char*)0x43F8C008) - -/* Timers */ -#define EPITCR1 (*(volatile long*)EPIT1_BASE_ADDR) -#define EPITSR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x04)) -#define EPITLR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x08)) -#define EPITCMPR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x0C)) -#define EPITCNT1 (*(volatile long*)(EPIT1_BASE_ADDR+0x10)) -#define EPITCR2 (*(volatile long*)EPIT2_BASE_ADDR) -#define EPITSR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x04)) -#define EPITLR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x08)) -#define EPITCMPR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x0C)) -#define EPITCNT2 (*(volatile long*)(EPIT2_BASE_ADDR+0x10)) - -/* GPIO */ -#define GPIO1_DR (*(volatile long*)GPIO1_BASE_ADDR) -#define GPIO1_GDIR (*(volatile long*)(GPIO1_BASE_ADDR+0x04)) -#define GPIO1_PSR (*(volatile long*)(GPIO1_BASE_ADDR+0x08)) -#define GPIO1_ICR1 (*(volatile long*)(GPIO1_BASE_ADDR+0x0C)) -#define GPIO1_ICR2 (*(volatile long*)(GPIO1_BASE_ADDR+0x10)) -#define GPIO1_IMR (*(volatile long*)(GPIO1_BASE_ADDR+0x14)) -#define GPIO1_ISR (*(volatile long*)(GPIO1_BASE_ADDR+0x18)) - -#define GPIO2_DR (*(volatile long*)GPIO2_BASE_ADDR) -#define GPIO2_GDIR (*(volatile long*)(GPIO2_BASE_ADDR+0x04)) -#define GPIO2_PSR (*(volatile long*)(GPIO2_BASE_ADDR+0x08)) -#define GPIO2_ICR1 (*(volatile long*)(GPIO2_BASE_ADDR+0x0C)) -#define GPIO2_ICR2 (*(volatile long*)(GPIO2_BASE_ADDR+0x10)) -#define GPIO2_IMR (*(volatile long*)(GPIO2_BASE_ADDR+0x14)) -#define GPIO2_ISR (*(volatile long*)(GPIO2_BASE_ADDR+0x18)) - -#define GPIO3_DR (*(volatile long*)GPIO3_BASE_ADDR) -#define GPIO3_GDIR (*(volatile long*)(GPIO3_BASE_ADDR+0x04)) -#define GPIO3_PSR (*(volatile long*)(GPIO3_BASE_ADDR+0x08)) -#define GPIO3_ICR1 (*(volatile long*)(GPIO3_BASE_ADDR+0x0C)) -#define GPIO3_ICR2 (*(volatile long*)(GPIO3_BASE_ADDR+0x10)) -#define GPIO3_IMR (*(volatile long*)(GPIO3_BASE_ADDR+0x14)) -#define GPIO3_ISR (*(volatile long*)(GPIO3_BASE_ADDR+0x18)) - -/* SPI */ -#define CSPI_RXDATA1 (*(volatile long*)CSPI1_BASE_ADDR) -#define CSPI_TXDATA1 (*(volatile long*)(CSPI1_BASE_ADDR+0x04)) -#define CSPI_CONREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x08)) -#define CSPI_INTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x0C)) -#define CSPI_DMAREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x10)) -#define CSPI_STATREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x14)) -#define CSPI_PERIODREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x18)) -#define CSPI_TESTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x1C0)) - -#define CSPI_RXDATA2 (*(volatile long*)CSPI2_BASE_ADDR) -#define CSPI_TXDATA2 (*(volatile long*)(CSPI2_BASE_ADDR+0x04)) -#define CSPI_CONREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x08)) -#define CSPI_INTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x0C)) -#define CSPI_DMAREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x10)) -#define CSPI_STATREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x14)) -#define CSPI_PERIODREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x18)) -#define CSPI_TESTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x1C0)) - -/* RTC */ -#define RTC_HOURMIN (*(volatile long*)RTC_BASE_ADDR) -#define RTC_SECONDS (*(volatile long*)(RTC_BASE_ADDR+0x04)) -#define RTC_ALRM_HM (*(volatile long*)(RTC_BASE_ADDR+0x08)) -#define RTC_ALRM_SEC (*(volatile long*)(RTC_BASE_ADDR+0x0C)) -#define RTC_CTL (*(volatile long*)(RTC_BASE_ADDR+0x10)) -#define RTC_ISR (*(volatile long*)(RTC_BASE_ADDR+0x14)) -#define RTC_IENR (*(volatile long*)(RTC_BASE_ADDR+0x18)) -#define RTC_STPWCH (*(volatile long*)(RTC_BASE_ADDR+0x1C)) -#define RTC_DAYR (*(volatile long*)(RTC_BASE_ADDR+0x20)) -#define RTC_DAYALARM (*(volatile long*)(RTC_BASE_ADDR+0x24)) - -/* Keypad */ -#define KPP_KPCR (*(volatile short*)KPP_BASE_ADDR) -#define KPP_KPSR (*(volatile short*)(KPP_BASE_ADDR+0x2)) -#define KPP_KDDR (*(volatile short*)(KPP_BASE_ADDR+0x4)) -#define KPP_KPDR (*(volatile short*)(KPP_BASE_ADDR+0x6)) - -/* ROMPATCH and AVIC */ -#define ROMPATCH_BASE_ADDR 0x60000000 -#define AVIC_BASE_ADDR 0x68000000 - -#define INTCNTL (*(volatile long*)AVIC_BASE_ADDR) -#define NIMASK (*(volatile long*)(AVIC_BASE_ADDR+0x004)) -#define INTENNUM (*(volatile long*)(AVIC_BASE_ADDR+0x008)) -#define INTDISNUM (*(volatile long*)(AVIC_BASE_ADDR+0x00C)) -#define INTENABLEH (*(volatile long*)(AVIC_BASE_ADDR+0x010)) -#define INTENABLEL (*(volatile long*)(AVIC_BASE_ADDR+0x014)) -#define INTTYPEH (*(volatile long*)(AVIC_BASE_ADDR+0x018)) -#define INTTYPEL (*(volatile long*)(AVIC_BASE_ADDR+0x01C)) -#define NIPRIORITY7 (*(volatile long*)(AVIC_BASE_ADDR+0x020)) -#define NIPRIORITY6 (*(volatile long*)(AVIC_BASE_ADDR+0x024)) -#define NIPRIORITY5 (*(volatile long*)(AVIC_BASE_ADDR+0x028)) -#define NIPRIORITY4 (*(volatile long*)(AVIC_BASE_ADDR+0x02C)) -#define NIPRIORITY3 (*(volatile long*)(AVIC_BASE_ADDR+0x030)) -#define NIPRIORITY2 (*(volatile long*)(AVIC_BASE_ADDR+0x034)) -#define NIPRIORITY1 (*(volatile long*)(AVIC_BASE_ADDR+0x038)) -#define NIPRIORITY0 (*(volatile long*)(AVIC_BASE_ADDR+0x03C)) -#define NIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x040)) -#define FIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x044)) -#define INTSRCH (*(volatile long*)(AVIC_BASE_ADDR+0x048)) -#define INTSRCL (*(volatile long*)(AVIC_BASE_ADDR+0x04C)) -#define INTFRCH (*(volatile long*)(AVIC_BASE_ADDR+0x050)) -#define INTFRCL (*(volatile long*)(AVIC_BASE_ADDR+0x054)) -#define NIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x058)) -#define NIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x05C)) -#define FIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x060)) -#define FIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x064)) - -/* The vectors go all the way up to 63. 4 bytes for each */ -#define VECTOR_BASE_ADDR AVIC_BASE_ADDR+0x100 -#define VECTOR0 (*(volatile long*)VECTOR_BASE_ADDR) - -#define NIDIS (1 << 22) -#define FIDIS (1 << 21) - -/* Since AVIC vector registers are NOT used, we reserve some for various - * purposes. Copied from Linux source code. */ -#define AVIC_VEC_0 0x100 /* For WFI workaround used by Linux kernel */ -#define AVIC_VEC_1 0x104 /* For system revision used by Linux kernel */ -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_2_0 0x20 -#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1) -#define SYSTEM_REV_ID_MAG 0xF00C - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define EXT_MEM_CTRL_BASE 0xB8000000 -#define NFC_BASE EXT_MEM_CTRL_BASE -#define ESDCTL_BASE 0xB8001000 -#define WEIM_BASE_ADDR 0xB8002000 -#define WEIM_CTRL_CS0 WEIM_BASE_ADDR -#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) -#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) -#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) -#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) -#define M3IF_BASE 0xB8003000 -#define PCMCIA_CTL_BASE 0xB8004000 - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 -#define CS4_BASE_ADDR 0xB4000000 -#define CS4_BASE_PSRAM 0xB5000000 -#define CS5_BASE_ADDR 0xB6000000 -#define PCMCIA_MEM_BASE_ADDR 0xC0000000 - -#define INTERNAL_ROM_VA 0xF0000000 - -// SDRAM -#define RAM_BANK0_BASE SDRAM_BASE_ADDR - -/* - * IRQ Controller Register Definitions. - */ -#define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04)) -#define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18)) -#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C)) - -/* L210 */ -#define L2CC_BASE_ADDR 0x30000000 -#define L2_CACHE_LINE_SIZE 32 -#define L2_CACHE_CTL_REG 0x100 -#define L2_CACHE_AUX_CTL_REG 0x104 -#define L2_CACHE_SYNC_REG 0x730 -#define L2_CACHE_INV_LINE_REG 0x770 -#define L2_CACHE_INV_WAY_REG 0x77C -#define L2_CACHE_CLEAN_LINE_REG 0x7B0 -#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 - -/* CCM */ -#define CLKCTL_CCMR (*(volatile long*)(CCM_BASE_ADDR+0x00)) -#define CLKCTL_PDR0 (*(volatile long*)(CCM_BASE_ADDR+0x04)) -#define CLKCTL_PDR1 (*(volatile long*)(CCM_BASE_ADDR+0x08)) -#define CLKCTL_PDR2 (*(volatile long*)(CCM_BASE_ADDR+0x64)) -#define CLKCTL_RCSR (*(volatile long*)(CCM_BASE_ADDR+0x0C)) -#define CLKCTL_MPCTL (*(volatile long*)(CCM_BASE_ADDR+0x10)) -#define CLKCTL_UPCTL (*(volatile long*)(CCM_BASE_ADDR+0x14)) -#define CLKCTL_SPCTL (*(volatile long*)(CCM_BASE_ADDR+0x18)) -#define CLKCTL_COSR (*(volatile long*)(CCM_BASE_ADDR+0x1C)) -#define CLKCTL_PMCR0 (*(volatile long*)(CCM_BASE_ADDR+0x5C)) -#define PLL_REF_CLK 26000000 - -/* WEIM - CS0 */ -#define CSCRU 0x00 -#define CSCRL 0x04 -#define CSCRA 0x08 - -/* ESDCTL */ -#define ESDCTL_ESDCTL0 0x00 -#define ESDCTL_ESDCFG0 0x04 -#define ESDCTL_ESDCTL1 0x08 -#define ESDCTL_ESDCFG1 0x0C -#define ESDCTL_ESDMISC 0x10 - -/* More UART 1 Register defines */ -#define URXD1 (*(volatile int*)UART1_BASE_ADDR) -#define UTXD1 (*(volatile int*)(UART1_BASE_ADDR+0x40)) -#define UCR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x80)) -#define UCR2_1 (*(volatile int* )(UART1_BASE_ADDR+0x84)) -#define UCR3_1 (*(volatile int* )(UART1_BASE_ADDR+0x88)) -#define UCR4_1 (*(volatile int* )(UART1_BASE_ADDR+0x8C)) -#define UFCR1 (*(volatile int *)(UART1_BASE_ADDR+ 0x90)) -#define USR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x94)) -#define USR2_1 (*(volatile int *)(UART1_BASE_ADDR+0x98)) -#define UTS1 (*(volatile int *)(UART1_BASE_ADDR+0xB4)) - -/* - * UART Control Register 0 Bit Fields. - */ -#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt -#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate -#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable -#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt -#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable -#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable -#define EUartUCR1_IREN (1 << 7) // Infrared interface enable -#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable -#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable -#define EUartUCR1_SNDBRK (1 << 4) // Send break -#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable -#define EUartUCR1_DOZE (1 << 1) // Doze -#define EUartUCR1_UARTEN (1 << 0) // UART enabled -#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable -#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin -#define EUartUCR2_CTSC (1 << 13) // CTS pin control -#define EUartUCR2_CTS (1 << 12) // Clear to send -#define EUartUCR2_ESCEN (1 << 11) // Escape enable -#define EUartUCR2_PREN (1 << 8) // Parity enable -#define EUartUCR2_PROE (1 << 7) // Parity odd/even -#define EUartUCR2_STPB (1 << 6) // Stop -#define EUartUCR2_WS (1 << 5) // Word size -#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable -#define EUartUCR2_ATEN (1 << 3) // Aging timer enable -#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled -#define EUartUCR2_RXEN (1 << 1) // Receiver enabled -#define EUartUCR2_SRST_ (1 << 0) // SW reset -#define EUartUCR3_PARERREN (1 << 12) // Parity enable -#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable -#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved -#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable -#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable -#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable -#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected -#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission -#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable -#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) -#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception -#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable -#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable -#define EUartUCR4_IRSC (1 << 5) // IR special case -#define EUartUCR4_LPBYP (1 << 4) // Low power bypass -#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable -#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable -#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable -#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable -#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift -#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) -#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) -#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) -#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) -#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) -#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) -#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) -#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift -#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag -#define EUartUSR1_RTSS (1 << 14) // RTS pin status -#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag -#define EUartUSR1_RTSD (1 << 12) // RTS delta -#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag -#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag -#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag -#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status -#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag -#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag -#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag -#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete -#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty -#define EUartUSR2_IDLE (1 << 12) // Idle condition -#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped -#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag -#define EUartUSR2_WAKE (1 << 7) // Wake -#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag -#define EUartUSR2_TXDC (1 << 3) // Transmitter complete -#define EUartUSR2_BRCD (1 << 2) // Break condition -#define EUartUSR2_ORE (1 << 1) // Overrun error -#define EUartUSR2_RDR (1 << 0) // Recv data ready -#define EUartUTS_FRCPERR (1 << 13) // Force parity error -#define EUartUTS_LOOP (1 << 12) // Loop tx and rx -#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty -#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty -#define EUartUTS_TXFULL (1 << 4) // TxFIFO full -#define EUartUTS_RXFULL (1 << 3) // RxFIFO full -#define EUartUTS_SOFTRST (1 << 0) // Software reset - -#define DelayTimerPresVal 3 - -#define L2CC_ENABLED - -/* Assuming 26MHz input clock */ -/* PD MFD MFI MFN */ -#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0)) -#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0)) -#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0)) - -/* UPCTL PD MFD MFI MFN */ -#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0)) -#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) - -/* PDR0 */ -#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */ -#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */ -#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */ -#define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ -#define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ -#define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ - -#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */ - -#define PBC_BSTAT2 0x2 -#define PBC_BCTRL1 0x4 -#define PBC_BCTRL1_CLR 0x6 -#define PBC_BCTRL2 0x8 -#define PBC_BCTRL2_CLR 0xA -#define PBC_BCTRL3 0xC -#define PBC_BCTRL3_CLR 0xE -#define PBC_BCTRL4 0x10 -#define PBC_BCTRL4_CLR 0x12 -#define PBC_BSTAT1 0x14 -#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300) -#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000) - -#define REDBOOT_IMAGE_SIZE 0x40000 - -#define SDRAM_WORKAROUND_FULL_PAGE - -#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/ -#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/ -#define ARMHIPG_399_66_66 -#define ARMHIPG_399_133_66 - -/* MX31 EVB SDRAM is from 0x80000000, 64M */ -#define SDRAM_BASE_ADDR CSD0_BASE_ADDR -#define SDRAM_SIZE 0x04000000 - -#define UART_WIDTH_32 /* internal UART is 32bit access only */ -#define EXT_UART_x16 - -#define UART_WIDTH_32 /* internal UART is 32bit access only */ - -#define FLASH_BURST_MODE_ENABLE 1 -#define SDRAM_COMPARE_CONST1 0x55555555 -#define SDRAM_COMPARE_CONST2 0xAAAAAAAA -#define UART_FIFO_CTRL 0x881 -#define TIMEOUT 1000 -#define writel(v,a) (*(volatile int *) (a) = (v)) -#define readl(a) (*(volatile int *)(a)) -#define writew(v,a) (*(volatile short *) (a) = (v)) -#define readw(a) (*(volatile short *)(a)) +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006 by James Espinoza + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ + +#define REG8_PTR_T volatile unsigned char * +#define REG16_PTR_T volatile unsigned short * +#define REG32_PTR_T volatile unsigned long * + +#define TTB_BASE_ADDR (0x80000000 + (64*1024*1024)-TTB_SIZE) +#define IRAM_BASE_ADDR 0x1fffc000 +#define L2CC_BASE_ADDR 0x30000000 + +/*Frame Buffer and TTB defines from gigabeat f/x build*/ +#define FRAME ((short *)0x80100000) /* Framebuffer */ +#define LCD_BUFFER_SIZE ((320*240*2)) +#define TTB_SIZE (0x4000) +#define TTB_BASE ((unsigned int *)TTB_BASE_ADDR) +#define FRAME1 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32) +#define FRAME2 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32) +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define ETB_SLOT4_BASE_ADDR 0x43F10000 +#define ETB_SLOT5_BASE_ADDR 0x43F14000 +#define ECT_CTIO_BASE_ADDR 0x43F18000 +#define I2C_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define OTG_BASE_ADDR 0x43F88000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE_ADDR 0x43F90000 +#define UART2_BASE_ADDR 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define OWIRE_BASE_ADDR 0x43F9C000 +#define SSI1_BASE_ADDR 0x43FA0000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define KPP_BASE_ADDR 0x43FA8000 +#define IOMUXC_BASE_ADDR 0x43FAC000 +#define UART4_BASE_ADDR 0x43FB0000 +#define UART5_BASE_ADDR 0x43FB4000 +#define ECT_IP1_BASE_ADDR 0x43FB8000 +#define ECT_IP2_BASE_ADDR 0x43FBC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define MMC_SDHC1_BASE_ADDR 0x50004000 +#define MMC_SDHC2_BASE_ADDR 0x50008000 +#define UART3_BASE_ADDR 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define SSI2_BASE_ADDR 0x50014000 +#define SIM_BASE_ADDR 0x50018000 +#define IIM_BASE_ADDR 0x5001C000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define FIRI_BASE_ADDR 0x53F8C000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define SCC_BASE 0x53FAC000 +#define SCM_BASE 0x53FAE000 +#define SMN_BASE 0x53FAF000 +#define RNGA_BASE_ADDR 0x53FB0000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define AUDMUX_BASE 0x53FC4000 +#define MPEG4_ENC_BASE 0x53FC8000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 + +#define WDOG1_BASE_ADDR WDOG_BASE_ADDR +#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR + +/* IPU */ +#define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00)) +#define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04)) +#define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08)) +#define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C)) +#define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10)) +#define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14)) +#define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18)) +#define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C)) +#define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20)) +#define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24)) +#define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28)) +#define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C)) +#define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30)) +#define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34)) +#define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38)) +#define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C)) +#define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40)) +#define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44)) +#define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48)) +#define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C)) +#define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50)) +#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54)) +#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58)) +#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60)) + + +/* ATA */ +#define TIME_OFF (*(REG8_PTR_T)0x43F8C000) +#define TIME_ON (*(REG8_PTR_T)0x43F8C001) +#define TIME_1 (*(REG8_PTR_T)0x43F8C002) +#define TIME_2W (*(REG8_PTR_T)0x43F8C003) +#define TIME_2R (*(REG8_PTR_T)0x43F8C004) +#define TIME_AX (*(REG8_PTR_T)0x43F8C005) +#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F) +#define TIME_4 (*(REG8_PTR_T)0x43F8C007) +#define TIME_9 (*(REG8_PTR_T)0x43F8C008) + +/* Timers */ +#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) +#define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04)) +#define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08)) +#define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C)) +#define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10)) +#define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00)) +#define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04)) +#define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08)) +#define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C)) +#define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10)) + +/* GPIO */ +#define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00)) +#define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04)) +#define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08)) +#define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C)) +#define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10)) +#define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14)) +#define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18)) + +#define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00)) +#define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04)) +#define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08)) +#define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C)) +#define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10)) +#define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14)) +#define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18)) + +#define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00)) +#define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04)) +#define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08)) +#define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C)) +#define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10)) +#define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14)) +#define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) + +/* SPI */ +#define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00)) +#define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04)) +#define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08)) +#define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C)) +#define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10)) +#define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14)) +#define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18)) +#define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0)) + +#define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00)) +#define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04)) +#define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08)) +#define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C)) +#define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10)) +#define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14)) +#define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18)) +#define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0)) + +/* RTC */ +#define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) +#define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) +#define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08)) +#define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C)) +#define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10)) +#define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14)) +#define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18)) +#define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C)) +#define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20)) +#define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24)) + +/* Keypad */ +#define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0)) +#define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2)) +#define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4)) +#define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6)) + +/* ROMPATCH and AVIC */ +#define ROMPATCH_BASE_ADDR 0x60000000 + +/* Since AVIC vector registers are NOT used, we reserve some for various + * purposes. Copied from Linux source code. */ +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 +#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1) +#define SYSTEM_REV_ID_MAG 0xF00C + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define NFC_BASE EXT_MEM_CTRL_BASE +#define ESDCTL_BASE 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00) +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40) +#define M3IF_BASE 0xB8003000 +#define PCMCIA_CTL_BASE 0xB8004000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS4_BASE_PSRAM 0xB5000000 +#define CS5_BASE_ADDR 0xB6000000 +#define PCMCIA_MEM_BASE_ADDR 0xC0000000 + +#define INTERNAL_ROM_VA 0xF0000000 + +/* + * SDRAM + */ +#define RAM_BANK0_BASE SDRAM_BASE_ADDR + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_BASE_ADDR 0x68000000 +#define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00)) +#define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04)) +#define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08)) +#define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C)) +#define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10)) +#define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14)) +#define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18)) +#define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C)) +#define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20)) +#define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24)) +#define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28)) +#define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C)) +#define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30)) +#define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34)) +#define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38)) +#define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C)) +#define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40)) +#define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44)) +#define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48)) +#define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C)) +#define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50)) +#define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54)) +#define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58)) +#define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C)) +#define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60)) +#define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64)) +#define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100) +#define VECTOR(n) (*(REG32_PTR_T)(VECTOR_BASE_ADDR+((n)*4))) + +/* The vectors go all the way up to 63. 4 bytes for each */ +#define INTCNTL_ABFLAG (1 << 25) +#define INTCNTL_ABFEN (1 << 24) +#define INTCNTL_NIDIS (1 << 22) +#define INTCNTL_FIDIS (1 << 21) +#define INTCNTL_NIAD (1 << 20) +#define INTCNTL_FIAD (1 << 19) +#define INTCNTL_NM (1 << 18) + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 + +#define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG)) + +/* CCM */ +#define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) +#define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) +#define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) +#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) +#define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) +#define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) +#define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) +#define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18)) +#define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C)) +#define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20)) +#define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) +#define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) +#define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) +#define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) +#define PLL_REF_CLK 26000000 + +/* WEIM - CS0 */ +#define CSCRU 0x00 +#define CSCRL 0x04 +#define CSCRA 0x08 + +/* ESDCTL */ +#define ESDCTL_ESDCTL0 0x00 +#define ESDCTL_ESDCFG0 0x04 +#define ESDCTL_ESDCTL1 0x08 +#define ESDCTL_ESDCFG1 0x0C +#define ESDCTL_ESDMISC 0x10 + +/* More UART 1 Register defines */ +#define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00)) +#define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40)) +#define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80)) +#define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84)) +#define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88)) +#define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C)) +#define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90)) +#define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94)) +#define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98)) +#define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4)) + +/* + * UART Control Register 0 Bit Fields. + */ +#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt +#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate +#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable +#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt +#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable +#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable +#define EUartUCR1_IREN (1 << 7) // Infrared interface enable +#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable +#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable +#define EUartUCR1_SNDBRK (1 << 4) // Send break +#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable +#define EUartUCR1_DOZE (1 << 1) // Doze +#define EUartUCR1_UARTEN (1 << 0) // UART enabled +#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable +#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin +#define EUartUCR2_CTSC (1 << 13) // CTS pin control +#define EUartUCR2_CTS (1 << 12) // Clear to send +#define EUartUCR2_ESCEN (1 << 11) // Escape enable +#define EUartUCR2_PREN (1 << 8) // Parity enable +#define EUartUCR2_PROE (1 << 7) // Parity odd/even +#define EUartUCR2_STPB (1 << 6) // Stop +#define EUartUCR2_WS (1 << 5) // Word size +#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable +#define EUartUCR2_ATEN (1 << 3) // Aging timer enable +#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled +#define EUartUCR2_RXEN (1 << 1) // Receiver enabled +#define EUartUCR2_SRST_ (1 << 0) // SW reset +#define EUartUCR3_PARERREN (1 << 12) // Parity enable +#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable +#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved +#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable +#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable +#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable +#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected +#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission +#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable +#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) +#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception +#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable +#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable +#define EUartUCR4_IRSC (1 << 5) // IR special case +#define EUartUCR4_LPBYP (1 << 4) // Low power bypass +#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable +#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable +#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable +#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable +#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift +#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) +#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) +#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) +#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) +#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) +#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) +#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) +#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift +#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag +#define EUartUSR1_RTSS (1 << 14) // RTS pin status +#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag +#define EUartUSR1_RTSD (1 << 12) // RTS delta +#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag +#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag +#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag +#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status +#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag +#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag +#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag +#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete +#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty +#define EUartUSR2_IDLE (1 << 12) // Idle condition +#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped +#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag +#define EUartUSR2_WAKE (1 << 7) // Wake +#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag +#define EUartUSR2_TXDC (1 << 3) // Transmitter complete +#define EUartUSR2_BRCD (1 << 2) // Break condition +#define EUartUSR2_ORE (1 << 1) // Overrun error +#define EUartUSR2_RDR (1 << 0) // Recv data ready +#define EUartUTS_FRCPERR (1 << 13) // Force parity error +#define EUartUTS_LOOP (1 << 12) // Loop tx and rx +#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty +#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty +#define EUartUTS_TXFULL (1 << 4) // TxFIFO full +#define EUartUTS_RXFULL (1 << 3) // RxFIFO full +#define EUartUTS_SOFTRST (1 << 0) // Software reset + +#define DelayTimerPresVal 3 + +#define L2CC_ENABLED + +/* Assuming 26MHz input clock */ +/* PD MFD MFI MFN */ +#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0)) +#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0)) +#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0)) + +/* UPCTL PD MFD MFI MFN */ +#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0)) +#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) + +/* PDR0 */ +#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */ +#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */ +#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */ +#define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ +#define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ +#define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ + +#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */ + +#define PBC_BSTAT2 0x2 +#define PBC_BCTRL1 0x4 +#define PBC_BCTRL1_CLR 0x6 +#define PBC_BCTRL2 0x8 +#define PBC_BCTRL2_CLR 0xA +#define PBC_BCTRL3 0xC +#define PBC_BCTRL3_CLR 0xE +#define PBC_BCTRL4 0x10 +#define PBC_BCTRL4_CLR 0x12 +#define PBC_BSTAT1 0x14 +#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300) +#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000) + +#define REDBOOT_IMAGE_SIZE 0x40000 + +#define SDRAM_WORKAROUND_FULL_PAGE + +#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/ +#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/ +#define ARMHIPG_399_66_66 +#define ARMHIPG_399_133_66 + +/* MX31 EVB SDRAM is from 0x80000000, 64M */ +#define SDRAM_BASE_ADDR CSD0_BASE_ADDR +#define SDRAM_SIZE 0x04000000 + +#define UART_WIDTH_32 /* internal UART is 32bit access only */ +#define EXT_UART_x16 + +#define UART_WIDTH_32 /* internal UART is 32bit access only */ + +#define FLASH_BURST_MODE_ENABLE 1 +#define SDRAM_COMPARE_CONST1 0x55555555 +#define SDRAM_COMPARE_CONST2 0xAAAAAAAA +#define UART_FIFO_CTRL 0x881 +#define TIMEOUT 1000 +#define writel(v,a) (*(REG32_PTR_T)(a) = (v)) +#define readl(a) (*(REG32_PTR_T)(a)) +#define writew(v,a) (*(REG16_PTR_T)(a) = (v)) +#define readw(a) (*(REG16_PTR_T)(a)) diff --git a/firmware/kernel.c b/firmware/kernel.c index 35bdec7df..8eba5651a 100644 --- a/firmware/kernel.c +++ b/firmware/kernel.c @@ -819,48 +819,6 @@ void tick_start(unsigned int interval_in_ms) TIMER0.ctrl |= 0x80; /* Enable the counter */ } -#elif CONFIG_CPU == IMX31L -void tick_start(unsigned int interval_in_ms) -{ - EPITCR1 &= ~0x1; /* Disable the counter */ - - EPITCR1 &= ~0xE; /* Disable interrupt, count down from 0xFFFFFFFF */ - EPITCR1 &= ~0xFFF0; /* Clear prescaler */ -#ifdef BOOTLOADER - EPITCR1 |= (2700 << 2); /* Prescaler = 2700 */ -#endif - EPITCR1 &= ~(0x3 << 24); - EPITCR1 |= (0x2 << 24); /* Set clock source to external clock (27mhz) */ - EPITSR1 = 1; /* Clear the interrupt request */ -#ifndef BOOTLOADER - EPITLR1 = 27000000 * interval_in_ms / 1000; - EPITCMPR1 = 27000000 * interval_in_ms / 1000; -#else - (void)interval_in_ms; -#endif - - //avic_enable_int(EPIT1, IRQ, EPIT_HANDLER); - - EPITCR1 |= 0x1; /* Enable the counter */ -} - -#ifndef BOOTLOADER -void EPIT_HANDLER(void) __attribute__((interrupt("IRQ"))); -void EPIT_HANDLER(void) { - int i; - - /* Run through the list of tick tasks */ - for(i = 0;i < MAX_NUM_TICK_TASKS;i++) - { - if(tick_funcs[i]) - tick_funcs[i](); - } - - current_tick++; - - EPITSR1 = 1; /* Clear the interrupt request */ -} -#endif #endif int tick_add_task(void (*f)(void)) diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index 2be2510bb..9d5088853 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S @@ -24,7 +24,7 @@ .global start start: b newstart - .space 4*16 + .space 4*12 /* Space for low vectors */ /* Arm bootloader and startup code based on startup.s from the iPodLinux loader @@ -35,86 +35,53 @@ start: */ newstart: - msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ + msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ -#if !defined(BOOTLOADER) -#if !defined(DEBUG) - /* Copy exception handler code to address 0 */ - ldr r2, =_vectorsstart - ldr r3, =_vectorsend - ldr r4, =_vectorscopy -1: - cmp r3, r2 - ldrhi r5, [r4], #4 - strhi r5, [r2], #4 - bhi 1b -#else - ldr r1, =vectors - ldr r0, =irq_handler - str r0, [r1, #24] - ldr r0, =fiq_handler - str r0, [r1, #28] -#endif - - /* Zero out IBSS */ - ldr r2, =_iedata - ldr r3, =_iend - mov r4, #0 -1: - cmp r3, r2 - strhi r4, [r2], #4 - bhi 1b - - /* Copy the IRAM */ - ldr r2, =_iramcopy - ldr r3, =_iramstart - ldr r4, =_iramend -1: - cmp r4, r3 - ldrhi r5, [r2], #4 - strhi r5, [r3], #4 - bhi 1b -#endif /* !BOOTLOADER */ - - /* Initialise bss section to zero */ - ldr r2, =_edata - ldr r3, =_end - mov r4, #0 -1: - cmp r3, r2 - strhi r4, [r2], #4 - bhi 1b +#ifdef BOOTLOADER + ldr r2, =remap_start + ldr r3, =remap_end + ldr r5, =TTB_BASE_ADDR /* TTB pointer */ + ldr r6, =IRAM_BASE_ADDR + mov r1, r6 + +1: + cmp r3, r2 + ldrhi r4, [r2], #4 + strhi r4, [r1], #4 + bhi 1b + + mov pc, r6 - /* Set up some stack and munge it with 0xdeadbeef */ - ldr sp, =stackend - mov r3, sp - ldr r2, =stackbegin - ldr r4, =0xdeadbeef -1: - cmp r3, r2 - strhi r4, [r2], #4 - bhi 1b +remap_start: + mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */ + tst r3, #(1 << 2) + tsteq r3, #(1 << 12) + mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ + mov r0, #0 + mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ -#ifdef BOOTLOADER -/* Code for ARM bootloader targets other than iPod go here */ - - mov r0, #0 - mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ - mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + mcr p15, 0, r0, c13, c0, 0 + mcr p15, 0, r0, c13, c0, 1 /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 + mov r0, #0x40000000 /* start from AIPS 2GB region */ + add r0, r0, #0x15 + mcr p15, 0, r0, c15, c2, 4 /*** L2 Cache setup/invalidation/disable ***/ /* Disable L2 cache first */ - ldr r0, =L2CC_BASE_ADDR - ldr r2, [r0, #L2_CACHE_CTL_REG] - bic r2, r2, #0x1 - str r2, [r0, #L2_CACHE_CTL_REG] - - + mov r0, #L2CC_BASE_ADDR + mov r1, #0 + str r1, [r0, #L2_CACHE_CTL_REG] + + /* Disble L1 caches and memory manager */ + bic r3, r3, #(1 << 1) + bic r3, r3, #(1 << 2) + bic r3, r3, #(1 << 12) + mcr p15, 0, r3, c1, c0, 0 + /* * Configure L2 Cache: * - 128k size(16k way) @@ -122,42 +89,21 @@ newstart: * - 0 ws TAG/VALID/DIRTY * - 4 ws DATA R/W */ - ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] - and r1, r1, #0xFE000000 - ldr r2, =0x00030024 - orr r1, r1, r2 - str r1, [r0, #L2_CACHE_AUX_CTL_REG] + mov r1, #0x00130000 + orr r1, r1, #0x24 + str r1, [r0, #L2_CACHE_AUX_CTL_REG] /* Invalidate L2 */ - ldr r1, =0x000000FF - str r1, [r0, #L2_CACHE_INV_WAY_REG] + mov r1, #0x000000FF + str r1, [r0, #L2_CACHE_INV_WAY_REG] L2_loop: /* Poll Invalidate By Way register */ - ldr r2, [r0, #L2_CACHE_INV_WAY_REG] - cmp r2, #0 - bne L2_loop + ldr r2, [r0, #L2_CACHE_INV_WAY_REG] + cmp r2, #0 + bne L2_loop + /*** End of L2 operations ***/ - /* Set up stack for IRQ mode */ - mov r0,#0xd2 - msr cpsr, r0 - ldr sp, =irq_stack - /* Set up stack for FIQ mode */ - mov r0,#0xd1 - msr cpsr, r0 - ldr sp, =fiq_stack - /* Let abort and undefined modes use IRQ stack */ - mov r0,#0xd7 - msr cpsr, r0 - ldr sp, =irq_stack - mov r0,#0xdb - msr cpsr, r0 - ldr sp, =irq_stack - /* Switch to supervisor mode */ - mov r0,#0xd3 - msr cpsr, r0 - ldr sp, =stackend - /*remap memory as well as exception vectors*/ /*for now this will be done in bootloader, especially if usb will be needed within the bootloader to load the @@ -165,172 +111,155 @@ L2_loop: (whether they be swi or irq)*/ /* TTB Initialisation */ - ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) - mov r1, #0 - ldr r2, =(0x80000000+64*1024*1024) + mov r3, r5 + add r2, r3, #TTB_SIZE + mov r1, #0 ttbloop: - str r1, [r3], #4 - cmp r3, r2 - bne ttbloop + str r1, [r3], #4 + cmp r3, r2 + bne ttbloop /* Set TTB base address */ - ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) - mcr 15, 0 ,r3, cr2, cr0, 0 + mov r3, r5 + mcr p15, 0, r3, c2, c0, 0 /* Set all domains to manager status */ - mvn r3, #0 - mcr 15, 0, r3, cr3, cr0, 0 + mvn r3, #0 + mcr p15, 0, r3, c3, c0, 0 /* Set page tables */ /* Map each memory loc to itself, no cache */ - mov r1, #0 /* Physical address */ - ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ - ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+0x4000) /* End position */ + mov r1, #0 /* Physical address */ + mov r3, r5 + add r4, r3, #TTB_SIZE /* End position */ maploop1: - mov r2, r1 - orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ - //orr r2, r2, #(0<<5) /* domain 0th */ - orr r2, r2, #(1<<4) /* should be "1" */ - orr r2, r2, #(1<<1) /* Section signature */ - str r2, [r3], #4 - add r1, r1, #(1<<20) - cmp r3, r4 - bne maploop1 + mov r2, r1 + orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ + //orr r2, r2, #(0<<5) /* domain 0th */ + orr r2, r2, #(1<<4) /* should be "1" */ + orr r2, r2, #(1<<1) /* Section signature */ + str r2, [r3], #4 + add r1, r1, #(1<<20) + cmp r3, r4 + bne maploop1 /* Map 0x80000000 -> 0x0, cached */ - mov r1, #0x80000000 /* Physical address */ - ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ - ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+256) /* End position */ + mov r1, #0x80000000 /* Physical address */ + mov r3, r5 /* TTB pointer */ + add r4, r3, #64*4 /* End position */ maploop2: - mov r2, r1 - orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ - //orr r2, r2, #(0<<5) /* domain 0th */ - orr r2, r2, #(1<<4) /* should be "1" */ - orr r2, r2, #(1<<3) /* cache flags */ - orr r2, r2, #(1<<2) /* more cache stuff */ - orr r2, r2, #(1<<1) /* Section signature */ - str r2, [r3], #4 - add r1, r1, #(1<<20) - cmp r3, r4 - bne maploop2 + mov r2, r1 + orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ + //orr r2, r2, #(0<<5) /* domain 0th */ + orr r2, r2, #(1<<4) /* should be "1" */ + orr r2, r2, #(1<<3) /* cache flags */ + orr r2, r2, #(1<<2) /* more cache stuff */ + orr r2, r2, #(1<<1) /* Section signature */ + str r2, [r3], #4 + add r1, r1, #(1<<20) + bic r6, r1, #0xf0000000 + cmp r6, #0x00100000 /* Skip framebuffer */ + addeq r1, r1, #(1<<20) + cmp r3, r4 + bne maploop2 /* Enable MMU */ - mrc 15, 0, r3, cr1, cr0, 0 - tst r3, #0x4 - bleq clean_dcache - tst r3, #0x1000 - bleq clean_dcache - mov r0, #0 - - mcr 15, 0, r0, cr8, cr7, 0 /* Invalidate TLB */ - mcr 15, 0, r0, cr7, cr7, 0 /* Invalidate icache and dcache */ - mrc 15, 0, r0, cr1, cr0, 0 - orr r0, r0, #1 /* enable mmu bit */ - orr r0, r0, #(1<<2) /* enable dcache */ - orr r0, r0, #(1<<12) /* enable icache */ - mcr 15, 0, r0, cr1, cr0, 0 + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ + mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */ +#if 1 + mrc p15, 0, r0, c1, c0, 1 + bic r0, r0, #0x70 + bic r0, r0, #0x07 + mcr p15, 0, r0, c1, c0, 1 +#endif + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1 << 0) /* enable mmu bit */ + orr r0, r0, #(1 << 2) /* enable dcache */ + bic r0, r0, #(1 << 11) /* no program flow prediction */ + orr r0, r0, #(1 << 12) /* enable icache */ + bic r0, r0, #(1 << 13) /* low vectors */ + orr r0, r0, #(1 << 14) /* Round-robin */ + bic r0, r0, #(1 << 21) /* No low latency interrupt */ + mcr p15, 0, r0, c1, c0, 0 nop nop nop nop + ldr pc, L_post_remap +L_post_remap: + .word remap_end +remap_end: - mov r0,#0 - ldr r1,=_vectorstart - mov r2,#0 - -lp: ldr r3,[r1] - add r1,r1,#4 - str r3,[r0] - add r0,r0,#4 - add r2,r2,#1 - cmp r2,#16 - bne lp - bl main - -.section .vectors,"aw" -_vectorstart: - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - ldr pc, [pc, #24] - - /* Exception vectors */ - .global vectors -vectors: - .word start - .word undef_instr_handler - .word software_int_handler - .word prefetch_abort_handler - .word data_abort_handler - .word reserved_handler - .word irqz - .word fiqz - - .text - .global irq - .global fiq - .global UIE - -undef_instr_handler: - mov r0, lr - mov r1, #0 - b UIE - -software_int_handler: -reserved_handler: - bl irq_handler - movs pc, lr - -prefetch_abort_handler: - sub r0, lr, #4 - mov r1, #1 - b UIE - -data_abort_handler: - sub r0, lr, #8 - mov r1, #2 - b UIE - -/*not working....if we get here, let someone -know....*/ -irqz: bl irq_handler -fiqz: bl fiq_handler - -UIE: - b UIE +#endif /* BOOTLOADER */ -/* 256 words of IRQ stack */ - .space 256*4 -irq_stack: +#ifndef BOOTLOADER + /* Copy exception handler code to address 0 */ + ldr r2, =_vectorsstart + ldr r3, =_vectorsend + ldr r4, =_vectorscopy +1: + cmp r3, r2 + ldrhi r5, [r4], #4 + strhi r5, [r2], #4 + bhi 1b -/* 256 words of FIQ stack */ - .space 256*4 -fiq_stack: + /* Zero out IBSS */ + ldr r2, =_iedata + ldr r3, =_iend + mov r4, #0 +1: + cmp r3, r2 + strhi r4, [r2], #4 + bhi 1b + /* Copy the IRAM */ + ldr r2, =_iramcopy + ldr r3, =_iramstart + ldr r4, =_iramend +1: + cmp r4, r3 + ldrhi r5, [r2], #4 + strhi r5, [r3], #4 + bhi 1b +#endif /* BOOTLOADER */ -#else /* BOOTLOADER */ + /* Initialise bss section to zero */ + ldr r2, =_edata + ldr r3, =_end + mov r4, #0 +1: + cmp r3, r2 + strhi r4, [r2], #4 + bhi 1b + + /* Set up some stack and munge it with 0xdeadbeef */ + ldr sp, =stackend + ldr r2, =stackbegin + ldr r3, =0xdeadbeef +1: + cmp sp, r2 + strhi r3, [r2], #4 + bhi 1b + + /* Set up stack for IRQ mode */ + msr cpsr_c, #0xd2 + ldr sp, =irq_stack - /* Set up stack for IRQ mode */ - msr cpsr_c, #0xd2 - ldr sp, =irq_stack /* Set up stack for FIQ mode */ - msr cpsr_c, #0xd1 - ldr sp, =fiq_stack + msr cpsr_c, #0xd1 + ldr sp, =fiq_stack /* Let abort and undefined modes use IRQ stack */ - msr cpsr_c, #0xd7 - ldr sp, =irq_stack - msr cpsr_c, #0xdb - ldr sp, =irq_stack - /* Switch to supervisor mode */ - msr cpsr_c, #0xd3 - ldr sp, =stackend - bl main - /* main() should never return */ + msr cpsr_c, #0xd7 + ldr sp, =irq_stack + msr cpsr_c, #0xdb + ldr sp, =irq_stack + + /* Switch back to supervisor mode */ + msr cpsr_c, #0xd3 + bl main /* Exception handlers. Will be copied to address 0 after memory remapping */ _vectorstart: @@ -358,8 +287,6 @@ vectors: .text - .global irq - .global fiq .global UIE /* All illegal exceptions call into UIE with exception address as first @@ -389,6 +316,11 @@ data_abort_handler: mov r1, #2 b UIE +#ifdef BOOTLOADER +UIE: + b UIE +#endif + /* 256 words of IRQ stack */ .space 256*4 irq_stack: @@ -396,5 +328,3 @@ irq_stack: /* 256 words of FIQ stack */ .space 256*4 fiq_stack: - -#endif /* BOOTLOADER */ diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c dissimilarity index 84% index 8236a3801..99a52e56d 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c @@ -1,223 +1,180 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2007 by James Espinoza - * - * All files in this archive are subject to the GNU General Public License. - * See the file COPYING in the source tree root for full license agreement. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ -#include -#include "system.h" -#include "imx31l.h" -#include "avic-imx31.h" -#include "debug.h" - -void avic_init(void) -{ - /*following the steps in the AVIC setup in imx31 man*/ - - /*Initialize interrupt structures*/ - int i,avicstart; - /*get start of avic_init section for address calculation*/ - __asm__ ("ldr %0,=_avicstart\n\t" - :"=r"(avicstart):); - - for(i=0; i < 64;i++) - { - imx31_int[i].name = (char *)&imx31_int_names[i]; - imx31_int[i].int_type=IRQ; - /*integer i MUST be multiplied by 8 b/c gnu as - generates 2 instructions for each vector instruction - in vector_init(). Hence the value of 8 byte intervals - between each vector start address*/ - imx31_int[i].addr=(avicstart+(i*8)); - imx31_int[i].priority=0; - imx31_int[i].pInt_Handler=Unhandled_Int; - } - - /*enable all Interrupts*/ - avic_enable_int(ALL,IRQ,0); - - /*Setup all interrupt type IRQ*/ - avic_set_int_type(ALL,IRQ); - - /*Set NM bit to enable VIC*/ - INTCNTL |= (1 << 18); - - /*Setup Registers Vector0-Vector63 for interrupt handler functions*/ - for(i=0; i < 64;i++) - writel(imx31_int[i].addr,(VECTOR_BASE_ADDR+(i*8))); - - /*disable FIQ for now until the interrupt handlers are more mature...*/ - disable_fiq(); - /*enable_fiq();*/ - - /*enable IRQ in imx31 INTCNTL reg*/ - INTCNTL &= ~(NIDIS); - /*disable FIQ in imx31 INTCNTL reg*/ - INTCNTL |= FIDIS; - - /*enable IRQ in ARM11 core, enable VE bit in CP15 Control reg to enable VIC*/ - __asm__ ("mrs r0,cpsr\t\n" - "bic r0,r0,#0x80\t\n" - "msr cpsr,r0\t\n" - "mrc p15,0,r0,c1,c0,0\n\t" - "orr r0,r0,#0x1000000\n\t" - "mcr p15,0,r0,c1,c0,0\n\t"::: - "r0"); -} - -void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, - void (*pInt_Handler) (void)) -{ - int i; - - if(ints == ALL) - { - avic_set_int_type(ALL,intstype); - for(i=0;i<64;i++) - INTENNUM= (long)i; - if(!(*pInt_Handler)) - pInt_Handler=Unhandled_Int; - return; - } - - imx31_int[ints].int_type=intstype; - imx31_int[ints].pInt_Handler=pInt_Handler; - avic_set_int_type(ints,intstype); - INTENNUM=(long)ints; -} - -void avic_disable_int(enum IMX31_INT_LIST ints) -{ - int i; - - if(ints == ALL) - { - for(i=0;i<64;i++) - INTDISNUM=(long)i; - imx31_int[ints].pInt_Handler=Unhandled_Int; - return; - } - - INTDISNUM=(long)ints; -} - -void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype) -{ - int i; - if(ints == ALL) - { - imx31_int[ints].int_type=intstype; - for(i=0;i<64;i++) - { - if(intstype > CCM_DVFS) - INTTYPEH=(long)(intstype-32); - else INTTYPEL=(long)intstype; - } - return; - } - - imx31_int[ints].int_type=intstype; - if(intstype > CCM_DVFS) - INTTYPEH=(long)(intstype-32); - else INTTYPEL=(long)intstype; -} - -void Unhandled_Int(void) -{ - enum IMX31_INT_LIST ints = 0; - DEBUGF("Unhandled Interrupt:\n"); - DEBUGF("Name : %s\n",imx31_int[ints].name); - DEBUGF("Interrupt Type : "); - if(imx31_int[ints].int_type==IRQ) - DEBUGF("IRQ\n"); - else DEBUGF("FIQ\n"); - DEBUGF("Handler Address : 0x%x\n",imx31_int[ints].addr); - DEBUGF("Priority : %d",imx31_int[ints].priority); -} - -void vector_init(void) -{ - - /*64 branch instructions, one for every vector in avic - A better idea would to calculate the shellcode for each of these - instructions...*/ - - - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED0].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C3].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MPEG4_ENCODER].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTIC].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[FIR].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ATA].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MBX].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI3].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART3].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IIM].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RNGA].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EVTMON].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[KPP].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTC].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWN].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPT].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWR_FAIL].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_DVFS].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[NANDFC].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SDMA].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_OTG].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED3].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU_ERR].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED4].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED5].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART4].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART5].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ETC_IRQ].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SCM].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SMN].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_CLK].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PCMCIA].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[WDOG].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO3].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED6].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_PWMG].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TEMP].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS1].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS2].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_WDOG].pInt_Handler)); - __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TV].pInt_Handler)); - -} +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by James Espinoza + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include +#include "system.h" +#include "imx31l.h" +#include "avic-imx31.h" +#include "panic.h" +#include "debug.h" + +static const char * avic_int_names[64] = +{ + "RESERVED0", "RESERVED1", "RESERVED2", "I2C3", + "I2C2", "MPEG4_ENCODER", "RTIC", "FIR", + "MMC/SDHC2", "MMC/SDHC1", "I2C1", "SSI2", + "SSI1", "CSPI2", "CSPI1", "ATA", + "MBX", "CSPI3", "UART3", "IIM", + "SIM1", "SIM2", "RNGA", "EVTMON", + "KPP", "RTC", "PWN", "EPIT2", + "EPIT1", "GPT", "PWR_FAIL", "CCM_DVFS", + "UART2", "NANDFC", "SDMA", "USB_HOST1", + "USB_HOST2", "USB_OTG", "RESERVED3", "MSHC1", + "MSHC2", "IPU_ERR", "IPU", "RESERVED4", + "RESERVED5", "UART1", "UART4", "UART5", + "ETC_IRQ", "SCC_SCM", "SCC_SMN", "GPIO2", + "GPIO1", "CCM_CLK", "PCMCIA", "WDOG", + "GPIO3", "RESERVED6", "EXT_PWMG", "EXT_TEMP", + "EXT_SENS1", "EXT_SENS2", "EXT_WDOG", "EXT_TV" +}; + +static void UIE_VECTOR(void) +{ + set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS); + long offset = FIVECSR; + long offsetn = (long)NIVECSR >> 16; + + if (offsetn == -1) + offset = offsetn; /* Could be FIQ */ + + panicf("Unhandled %s %ld: %s", + offsetn >= 0 ? "IRQ" : "FIQ", offset, + offset >= 0 ? avic_int_names[offset] : ""); +} + +/* We use the AVIC */ +void __attribute__((naked)) irq_handler(void) +{ + panicf("Unhandled IRQ"); +} + +/* Accoring to section 9.3.5 of the UM, the AVIC doesn't accelerate + * fast interrupts and they must be dispatched */ +void __attribute__((naked)) fiq_handler(void) +{ + asm volatile ( + "mov r10, #0x6c000000 \n" /* load AVIC base address */ + "ldr r9, [r10, #0x44] \n" /* read FIVECSR of AVIC */ + "add r10, r10, #100 \n" /* move pointer to base of VECTOR table */ + "ldr r8, [r10, r9, lsl #2] \n" /* read FIQ vector from VECTOR table */ + "bx r8 \n" /* jump to FIQ service routine */ + ); +} + +void avic_init(void) +{ + /* Disable all interrupts and set to unhandled */ + avic_disable_int(ALL); + + /* Init all interrupts to type IRQ */ + avic_set_int_type(ALL, IRQ); + + /* Set NM bit to enable VIC */ + INTCNTL |= INTCNTL_NM; + + /* Enable IRQ/FIQ in imx31 INTCNTL reg */ + INTCNTL &= ~(INTCNTL_ABFEN | INTCNTL_NIDIS | INTCNTL_FIDIS); + + /* Enable VE bit in CP15 Control reg to enable VIC */ + asm volatile ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "orr r0, r0, #(1 << 24) \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + : : : "r0"); + + /* Enable normal interrupts at all priorities */ + NIMASK = 16; +} + +void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, + void (*handler)(void)) +{ + int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, + IRQ_FIQ_STATUS); + + if (ints != ALL) /* No mass-enable allowed */ + { + avic_set_int_type(ints, intstype); + VECTOR(ints) = (long)handler; + INTENNUM = ints; + } + + set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); +} + +void avic_disable_int(enum IMX31_INT_LIST ints) +{ + long i; + + if (ints == ALL) + { + for (i = 0; i < 64; i++) + { + INTDISNUM = i; + VECTOR(i) = (long)UIE_VECTOR; + } + } + else + { + INTDISNUM = ints; + VECTOR(ints) = (long)UIE_VECTOR; + } +} + +static void set_int_type(int i, enum INT_TYPE intstype) +{ + volatile unsigned long *reg; + long val; + + if (i >= 32) + { + reg = &INTTYPEH; + val = 1L << (i - 32); + } + else + { + reg = &INTTYPEL; + val = 1L << i; + } + + if (intstype == IRQ) + val = *reg & ~val; + else + val = *reg | val; + + *reg = val; +} + +void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype) +{ + int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, + IRQ_FIQ_STATUS); + + if (ints == ALL) + { + int i; + for (i = 0; i < 64; i++) + set_int_type(i, intstype); + } + else + { + set_int_type(ints, intstype); + } + + set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); +} diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h dissimilarity index 64% index 53a37b353..29a3ec8dd 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h @@ -1,125 +1,55 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2007 by James Espinoza - * - * All files in this archive are subject to the GNU General Public License. - * See the file COPYING in the source tree root for full license agreement. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ -#ifndef AVIC_IMX31_H -#define AVIC_IMX31_H - - -enum INT_TYPE {IRQ=0,FIQ}; - -struct int_names { - char name[16]; -}; - -static const struct int_names imx31_int_names[64] = -{ {"RESERVED0"}, - {"RESERVED1"}, - {"RESERVED2"}, - {"I2C3"}, - {"I2C2"}, - {"MPEG4_ENCODER"}, - {"RTIC"}, - {"FIR"}, - {"MMC/SDHC2"}, - {"MMC/SDHC1"}, - {"I2C1"}, - {"SSI2"}, - {"SSI1"}, - {"CSPI2"}, - {"CSPI1"}, - {"ATA"}, - {"MBX"}, - {"CSPI3"}, - {"UART3"}, - {"IIM"}, - {"SIM1"}, - {"SIM2"}, - {"RNGA"}, - {"EVTMON"}, - {"KPP"}, - {"RTC"}, - {"PWN"}, - {"EPIT2"}, - {"EPIT1"}, - {"GPT"}, - {"PWR_FAIL"}, - {"CCM_DVFS"}, - {"UART2"}, - {"NANDFC"}, - {"SDMA"}, - {"USB_HOST1"}, - {"USB_HOST2"}, - {"USB_OTG"}, - {"RESERVED3"}, - {"MSHC1"}, - {"MSHC2"}, - {"IPU_ERR"}, - {"IPU"}, - {"RESERVED4"}, - {"RESERVED5"}, - {"UART1"}, - {"UART4"}, - {"UART5"}, - {"ETC_IRQ"}, - {"SCC_SCM"}, - {"SCC_SMN"}, - {"GPIO2"}, - {"GPIO1"}, - {"CCM_CLK"}, - {"PCMCIA"}, - {"WDOG"}, - {"GPIO3"}, - {"RESERVED6"}, - {"EXT_PWMG"}, - {"EXT_TEMP"}, - {"EXT_SENS1"}, - {"EXT_SENS2"}, - {"EXT_WDOG"}, - {"EXT_TV"} }; - -enum IMX31_INT_LIST { - RESERVED0 = 0,RESERVED1,RESERVED2,I2C3, - I2C2,MPEG4_ENCODER,RTIC,FIR,MMC_SDHC2, - MMC_SDHC1,I2C1,SSI2,SSI1,CSPI2,CSPI1, - ATA,MBX,CSPI3,UART3,IIM,SIM1,SIM2, - RNGA,EVTMON,KPP,RTC,PWN,EPIT2,EPIT1, - GPT,PWR_FAIL,CCM_DVFS,UART2,NANDFC, - SDMA,USB_HOST1,USB_HOST2,USB_OTG, - RESERVED3,MSHC1,MSHC2,IPU_ERR,IPU, - RESERVED4,RESERVED5,UART1,UART4,UART5, - ETC_IRQ,SCC_SCM,SCC_SMN,GPIO2,GPIO1, - CCM_CLK,PCMCIA,WDOG,GPIO3,RESERVED6, - EXT_PWMG,EXT_TEMP,EXT_SENS1,EXT_SENS2, - EXT_WDOG,EXT_TV,ALL }; - -static struct avic_int { - char * name; - enum INT_TYPE int_type; - unsigned int addr; - unsigned int priority; - void (*pInt_Handler) (void); -} imx31_int[64]; - -void avic_init(void); -void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, - void (*pInt_Handler) (void)); -void avic_disable_int(enum IMX31_INT_LIST ints) ; -void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); -void Unhandled_Int(void); -void vector_init(void) __attribute__ ((section(".avic_int"),naked)); -#endif +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by James Espinoza + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef AVIC_IMX31_H +#define AVIC_IMX31_H + +enum INT_TYPE +{ + IRQ = 0, + FIQ +}; + +enum IMX31_INT_LIST +{ + __IMX31_INT_FIRST = -1, + RESERVED0, RESERVED1, RESERVED2, I2C3, + I2C2, MPEG4_ENCODER, RTIC, FIR, + MMC_SDHC2, MMC_SDHC1, I2C1, SSI2, + SSI1, CSPI2, CSPI1, ATA, + MBX, CSPI3, UART3, IIM, + SIM1, SIM2, RNGA, EVTMON, + KPP, RTC, PWN, EPIT2, + EPIT1, GPT, PWR_FAIL, CCM_DVFS, + UART2, NANDFC, SDMA, USB_HOST1, + USB_HOST2, USB_OTG, RESERVED3, MSHC1, + MSHC2, IPU_ERR, IPU, RESERVED4, + RESERVED5, UART1, UART4, UART5, + ETC_IRQ, SCC_SCM, SCC_SMN, GPIO2, + GPIO1, CCM_CLK, PCMCIA, WDOG, + GPIO3, RESERVED6, EXT_PWMG, EXT_TEMP, + EXT_SENS1, EXT_SENS2, EXT_WDOG, EXT_TV, + ALL +}; + +void avic_init(void); +void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, + void (*handler)(void)); +void avic_disable_int(enum IMX31_INT_LIST ints); +void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); +#endif diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c index 9df90a234..7f882405a 100644 --- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c @@ -1,25 +1,60 @@ +#include "config.h" +#include "system.h" +#include "avic-imx31.h" #include "kernel.h" #include "thread.h" - #include -#include "lcd.h" extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void); -void timer4(void) { - int i; +#ifndef BOOTLOADER +static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void) +{ + int i; + + EPITSR1 = 1; /* Clear the pending status */ + /* Run through the list of tick tasks */ - for(i = 0; i < MAX_NUM_TICK_TASKS; i++) + for(i = 0;i < MAX_NUM_TICK_TASKS;i++) { if(tick_funcs[i]) - { tick_funcs[i](); - } } current_tick++; - - /* following needs to be fixed. */ - /*wake_up_thread();*/ } +#endif + +void tick_start(unsigned int interval_in_ms) +{ + EPITCR1 &= ~(1 << 0); /* Disable the counter */ + EPITCR1 |= (1 << 16); /* Reset */ + CLKCTL_CGR0 |= (0x3 << 6); /* Clock ON */ + CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */ + + /* NOTE: This isn't really accurate yet but it's close enough to work + * with for the moment */ + + /* CLKSRC=32KHz, EPIT Output Disconnected, Enabled + * prescale 1/32, Reload from modulus register, Compare interrupt enabled, + * Count from load value */ + EPITCR1 = (0x3 << 24) | (1 << 19) | (32 << 4) | + (1 << 3) | (1 << 2) | (1 << 1); + EPITSR1 = 1; /* Clear any pending interrupt */ +#ifndef BOOTLOADER + EPITLR1 = interval_in_ms; + EPITCMPR1 = 0; /* Event when counter reaches 0 */ + avic_enable_int(EPIT1, IRQ, EPIT1_HANDLER); +#else + (void)interval_in_ms; +#endif + + EPITCR1 |= (1 << 0); /* Enable the counter */ + + /* Why does only this trigger the counter? Remove when we find out. */ + asm volatile ( + "mcr p15, 0, %0, c7, c0, 4 \n" + : : "r" (0) + ); +} diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S b/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S deleted file mode 100644 index d431c95f2..000000000 --- a/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S +++ /dev/null @@ -1,222 +0,0 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2007 by Michael Sevakis - * - * All files in this archive are subject to the GNU General Public License. - * See the file COPYING in the source tree root for full license agreement. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -#include "config.h" -#include "cpu.h" - -/**************************************************************************** - * void lcd_write_yuv_420_lines(fb_data *dst, - * unsigned char chroma_buf[LCD_HEIGHT/2*3], - unsigned char const * const src[3], - * int width, - * int stride); - * - * |R| |1.000000 -0.000001 1.402000| |Y'| - * |G| = |1.000000 -0.334136 -0.714136| |Pb| - * |B| |1.000000 1.772000 0.000000| |Pr| - * Scaled, normalized, rounded and tweaked to yield RGB 565: - * |R| |74 0 101| |Y' - 16| >> 9 - * |G| = |74 -24 -51| |Cb - 128| >> 8 - * |B| |74 128 0| |Cr - 128| >> 9 - */ - .section .icode, "ax", %progbits - .align 2 - .global lcd_write_yuv420_lines - .type lcd_write_yuv420_lines, %function -lcd_write_yuv420_lines: - @ r0 = dst - @ r1 = chroma_buf - @ r2 = yuv_src - @ r3 = width - @ [sp] = stride - stmdb sp!, { r4-r12, lr } @ save non-scratch - stmdb sp!, { r0, r3 } @ save dst and width - mov r14, #74 @ r14 = Y factor - ldmia r2, { r4, r5, r6 } @ r4 = yuv_src[0] = Y'_p - @ r5 = yuv_src[1] = Cb_p - @ r6 = yuv_src[2] = Cr_p -10: @ loop line 1 @ - ldrb r2, [r4], #1 @ r2 = *Y'_p++; - ldrb r8, [r5], #1 @ r8 = *Cb_p++; - ldrb r11, [r6], #1 @ r11 = *Cr_p++; - @ - @ compute Y - sub r2, r2, #16 @ r7 = Y = (Y' - 16)*74 - mul r7, r2, r14 @ - @ - sub r8, r8, #128 @ Cb -= 128 - sub r11, r11, #128 @ Cr -= 128 - @ - mvn r2, #24 @ compute guv - mul r10, r2, r8 @ r10 = Cb*-24 - mvn r2, #51 @ - mla r10, r2, r11, r10 @ r10 = r10 + Cr*-51 - @ - mov r2, #101 @ compute rv - mul r9, r11, r2 @ r9 = rv = Cr*101 - @ - @ store chromas in line buffer - add r8, r8, #2 @ bu = (Cb + 2) >> 2 - mov r8, r8, asr #2 @ - strb r8, [r1], #1 @ - add r9, r9, #256 @ rv = (Cr + 256) >> 9 - mov r9, r9, asr #9 @ - strb r9, [r1], #1 @ - mov r10, r10, asr #8 @ guv >>= 8 - strb r10, [r1], #1 @ - @ compute R, G, and B - add r2, r8, r7, asr #9 @ r2 = b = (Y >> 9) + bu - add r11, r9, r7, asr #9 @ r11 = r = (Y >> 9) + rv - add r7, r10, r7, asr #8 @ r7 = g = (Y >> 8) + guv - @ - orr r12, r2, r11 @ check if clamping is needed... - orr r12, r12, r7, asr #1 @ ...at all - cmp r12, #31 @ - bls 15f @ no clamp @ - mov r12, #31 @ - cmp r12, r2 @ clamp b - andlo r2, r12, r2, asr #31 @ - eorlo r2, r2, r12 @ - cmp r12, r11 @ clamp r - andlo r11, r12, r11, asr #31 @ - eorlo r11, r11, r12 @ - cmp r12, r7, asr #1 @ clamp g - andlo r7, r12, r7, asr #31 @ - eorlo r7, r7, r12 @ - orrlo r7, r7, r7, asl #1 @ -15: @ no clamp @ - @ - orr r12, r2, r7, lsl #5 @ r4 |= (g << 5) - ldrb r2, [r4], #1 @ r2 = Y' = *Y'_p++ - orr r12, r12, r11, lsl #11 @ r4 = b | (r << 11) - strh r12, [r0], #240 @ store pixel - @ - sub r2, r2, #16 @ r7 = Y = (Y' - 16)*74 - mul r7, r2, r14 @ next Y - @ compute R, G, and B - add r2, r8, r7, asr #9 @ r2 = b = (Y >> 9) + bu - add r11, r9, r7, asr #9 @ r11 = r = (Y >> 9) + rv - add r7, r10, r7, asr #8 @ r7 = g = (Y >> 8) + guv - @ - orr r12, r2, r11 @ check if clamping is needed... - orr r12, r12, r7, asr #1 @ ...at all - cmp r12, #31 @ - bls 15f @ no clamp @ - mov r12, #31 @ - cmp r12, r2 @ clamp b - andlo r2, r12, r2, asr #31 @ - eorlo r2, r2, r12 @ - cmp r12, r11 @ clamp r - andlo r11, r12, r11, asr #31 @ - eorlo r11, r11, r12 @ - cmp r12, r7, asr #1 @ clamp g - andlo r7, r12, r7, asr #31 @ - eorlo r7, r7, r12 @ - orrlo r7, r7, r7, asl #1 @ -15: @ no clamp @ - @ - orr r12, r2, r11, lsl #11 @ r4 = b | (r << 11) - orr r12, r12, r7, lsl #5 @ r4 |= (g << 5) - strh r12, [r0, #240]! @ store pixel - add r0, r0, #2*240 @ - @ - subs r3, r3, #2 @ - bgt 10b @ loop line 1 @ - @ do second line - @ - ldmia sp!, { r0, r3 } @ pop dst and width - sub r0, r0, #2 @ set dst to start of next line - sub r1, r1, r3, asl #1 @ rewind chroma pointer... - ldr r2, [sp, #40] @ r2 = stride - add r1, r1, r3, asr #1 @ ... (r1 -= width/2*3) - @ move sources to start of next line - sub r2, r2, r3 @ r2 = skip = stride - width - add r4, r4, r2 @ r4 = Y'_p + skip - @ -20: @ loop line 2 @ - ldrb r2, [r4], #1 @ r7 = Y' = *Y'_p++ - ldrsb r8, [r1], #1 @ reload saved chromas - ldrsb r9, [r1], #1 @ - ldrsb r10, [r1], #1 @ - @ - sub r2, r2, #16 @ r2 = Y = (Y' - 16)*74 - mul r7, r2, r14 @ - @ compute R, G, and B - add r2, r8, r7, asr #9 @ r2 = b = (Y >> 9) + bu - add r11, r9, r7, asr #9 @ r11 = r = (Y >> 9) + rv - add r7, r10, r7, asr #8 @ r7 = g = (Y >> 8) + guv - @ - orr r12, r2, r11 @ check if clamping is needed... - orr r12, r12, r7, asr #1 @ ...at all - cmp r12, #31 @ - bls 25f @ no clamp @ - mov r12, #31 @ - cmp r12, r2 @ clamp b - andlo r2, r12, r2, asr #31 @ - eorlo r2, r2, r12 @ - cmp r12, r11 @ clamp r - andlo r11, r12, r11, asr #31 @ - eorlo r11, r11, r12 @ - cmp r12, r7, asr #1 @ clamp g - andlo r7, r12, r7, asr #31 @ - eorlo r7, r7, r12 @ - orrlo r7, r7, r7, asl #1 @ -25: @ no clamp @ - @ - orr r12, r2, r11, lsl #11 @ r4 = b | (r << 11) - ldrb r2, [r4], #1 @ r2 = Y' = *Y'_p++ - orr r12, r12, r7, lsl #5 @ r4 |= (g << 5) - strh r12, [r0], #240 @ store pixel - @ - @ do second pixel - @ - sub r2, r2, #16 @ r2 = Y = (Y' - 16)*74 - mul r7, r2, r14 @ - @ compute R, G, and B - add r2, r8, r7, asr #9 @ r2 = b = (Y >> 9) + bu - add r11, r9, r7, asr #9 @ r11 = r = (Y >> 9) + rv - add r7, r10, r7, asr #8 @ r7 = g = (Y >> 8) + guv - @ - orr r12, r2, r11 @ check if clamping is needed... - orr r12, r12, r7, asr #1 @ ...at all - cmp r12, #31 @ - bls 25f @ no clamp @ - mov r12, #31 @ - cmp r12, r2 @ clamp b - andlo r2, r12, r2, asr #31 @ - eorlo r2, r2, r12 @ - cmp r12, r11 @ clamp r - andlo r11, r12, r11, asr #31 @ - eorlo r11, r11, r12 @ - cmp r12, r7, asr #1 @ clamp g - andlo r7, r12, r7, asr #31 @ - eorlo r7, r7, r12 @ - orrlo r7, r7, r7, asl #1 @ -25: @ no clamp @ - @ - orr r12, r2, r11, lsl #11 @ r4 = b | (r << 11) - orr r12, r12, r7, lsl #5 @ r4 |= (g << 5) - strh r12, [r0, #240]! @ store pixel - add r0, r0, #2*240 @ - @ - subs r3, r3, #2 @ - bgt 20b @ loop line 2 @ - @ - ldmia sp!, { r4-r12, pc } @ restore registers and return - .size lcd_write_yuv420_lines, .-lcd_write_yuv420_lines diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c b/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c index c9cce6d65..b39ddbe77 100644 --- a/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c @@ -9,12 +9,15 @@ static volatile bool lcd_on = true; volatile bool lcd_poweroff = false; +static unsigned lcd_yuv_options = 0; /* ** These are imported from lcd-16bit.c */ extern unsigned fg_pattern; extern unsigned bg_pattern; +extern struct viewport* current_vp; + #if 0 bool lcd_enabled() { @@ -22,68 +25,60 @@ bool lcd_enabled() } #endif -void printscreen(unsigned int colour) { +void printscreen(unsigned int colour) +{ int i; - int base = 0x84100000; - for(i=0;i<(320*240*2);i++) { - writel(colour,base); + char * base = (char *)FRAME; + for(i = 0; i < (320*240*2); i++) + { + writel(colour, base); base++; } } -unsigned int LCDBANK(unsigned int address) -{ - return ((address >> 22) & 0xff); -} - -unsigned int LCDBASEU(unsigned int address) -{ - return (address & ((1 << 22)-1)) >> 1; -} - -unsigned int LCDBASEL(unsigned int address) -{ - address += 320*240*2; - return (address & ((1 << 22)-1)) >> 1; -} - - /* LCD init */ void lcd_init_device(void) { - int i; -#ifdef BOOTLOADER - /* When the Rockbox bootloader starts, we are changing framebuffer address, - but we don't want what's shown on the LCD to change until we do an - lcd_update(), so copy the data from the old framebuffer to the new one */ - unsigned short *buf = (unsigned short*)FRAME1; - - memcpy(FRAME1, (short *)((LCDSADDR1)<<1), 320*240*2); - - /* The Rockbox bootloader is transitioning from RGB555I to RGB565 mode - so convert the frambuffer data accordingly */ - for(i=0; i< 320*240; i++){ - *buf = ((*buf>>1) & 0x1F) | (*buf & 0xffc0); - buf++; - } - return; -#endif } /* Update a fraction of the display. */ void lcd_update_rect(int x, int y, int width, int height) { - (void)x; - (void)width; - (void)y; - (void)height; + fb_data *dst, *src; - if(!lcd_on) - { - sleep(200); + if (!lcd_on) return; + + if (x + width > LCD_WIDTH) + width = LCD_WIDTH - x; /* Clip right */ + if (x < 0) + width += x, x = 0; /* Clip left */ + if (width <= 0) + return; /* nothing left to do */ + + if (y + height > LCD_HEIGHT) + height = LCD_HEIGHT - y; /* Clip bottom */ + if (y < 0) + height += y, y = 0; /* Clip top */ + if (height <= 0) + return; /* nothing left to do */ + + /* TODO: It may be faster to swap the addresses of lcd_driver_framebuffer + * and lcd_framebuffer */ + dst = (fb_data *)FRAME + LCD_WIDTH*y + x; + src = &lcd_framebuffer[y][x]; + + /* Copy part of the Rockbox framebuffer to the second framebuffer */ + if (width < LCD_WIDTH) + { + /* Not full width - do line-by-line */ + lcd_copy_buffer_rect(dst, src, width, height); + } + else + { + /* Full width - copy as one line */ + lcd_copy_buffer_rect(dst, src, LCD_WIDTH*height, 1); } - memcpy(((char*)FRAME2) + (y * sizeof(fb_data) * LCD_WIDTH), ((char *)&lcd_framebuffer) + (y * sizeof(fb_data) * LCD_WIDTH), ((height * sizeof(fb_data) * LCD_WIDTH))); } void lcd_enable(bool state) @@ -100,68 +95,82 @@ bool lcd_enabled(void) This must be called after all other LCD functions that change the display. */ void lcd_update(void) { - lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); + if (!lcd_on) + return; + + lcd_copy_buffer_rect((fb_data *)FRAME, &lcd_framebuffer[0][0], + LCD_WIDTH*LCD_HEIGHT, 1); } void lcd_bitmap_transparent_part(const fb_data *src, int src_x, int src_y, int stride, int x, int y, int width, int height) { - fb_data *dst, *dst_end; - unsigned int transcolor; - - /* nothing to draw? */ - if ((width <= 0) || (height <= 0) || (x >= LCD_WIDTH) || (y >= LCD_HEIGHT) - || (x + width <= 0) || (y + height <= 0)) - return; +#if 0 + int w, px; + fb_data *dst; - /* clipping */ - if (x < 0) - { - width += x; - src_x -= x; - x = 0; - } - if (y < 0) - { - height += y; - src_y -= y; - y = 0; - } if (x + width > LCD_WIDTH) - width = LCD_WIDTH - x; + width = LCD_WIDTH - x; /* Clip right */ + if (x < 0) + width += x, x = 0; /* Clip left */ + if (width <= 0) + return; /* nothing left to do */ + if (y + height > LCD_HEIGHT) - height = LCD_HEIGHT - y; + height = LCD_HEIGHT - y; /* Clip bottom */ + if (y < 0) + height += y, y = 0; /* Clip top */ + if (height <= 0) + return; /* nothing left to do */ src += stride * src_y + src_x; /* move starting point */ - dst = &lcd_framebuffer[(y)][(x)]; - dst_end = dst + height * LCD_WIDTH; - width *= 2; - stride *= 2; - transcolor = TRANSPARENT_COLOR; - asm volatile( - "rowstart: \n" - "mov r0, #0 \n" - "nextpixel: \n" - "ldrh r1, [%0, r0] \n" /* Load word src+r0 */ - "cmp r1, %5 \n" /* Compare to transparent color */ - "strneh r1, [%1, r0] \n" /* Store dst+r0 if not transparent */ - "add r0, r0, #2 \n" - "cmp r0, %2 \n" /* r0 == width? */ - "bne nextpixel \n" /* More in this row? */ - "add %0, %0, %4 \n" /* src += stride */ - "add %1, %1, #480 \n" /* dst += LCD_WIDTH (x2) */ - "cmp %1, %3 \n" - "bne rowstart \n" /* if(dst != dst_end), keep going */ - : : "r" (src), "r" (dst), "r" (width), "r" (dst_end), "r" (stride), "r" (transcolor) : "r0", "r1" ); + dst = &lcd_framebuffer[y][x]; + + asm volatile ( + ".rowstart: \r\n" + "mov %[w], %[width] \r\n" /* Load width for inner loop */ + ".nextpixel: \r\n" + "ldrh %[px], [%[s]], #2 \r\n" /* Load src pixel */ + "add %[d], %[d], #2 \r\n" /* Uncoditionally increment dst */ + "cmp %[px], %[fgcolor] \r\n" /* Compare to foreground color */ + "streqh %[fgpat], [%[d], #-2] \r\n" /* Store foregroud if match */ + "cmpne %[px], %[transcolor] \r\n" /* Compare to transparent color */ + "strneh %[px], [%[d], #-2] \r\n" /* Store dst if not transparent */ + "subs %[w], %[w], #1 \r\n" /* Width counter has run down? */ + "bgt .nextpixel \r\n" /* More in this row? */ + "add %[s], %[s], %[sstp], lsl #1 \r\n" /* Skip over to start of next line */ + "add %[d], %[d], %[dstp], lsl #1 \r\n" + "subs %[h], %[h], #1 \r\n" /* Height counter has run down? */ + "bgt .rowstart \r\n" /* More rows? */ + : [w]"=&r"(w), [h]"+&r"(height), [px]"=&r"(px), + [s]"+&r"(src), [d]"+&r"(dst) + : [width]"r"(width), + [sstp]"r"(stride - width), + [dstp]"r"(LCD_WIDTH - width), + [transcolor]"r"(TRANSPARENT_COLOR), + [fgcolor]"r"(REPLACEWITHFG_COLOR), + [fgpat]"r"(current_vp->fg_pattern) + ); +#endif +} + +void lcd_yuv_set_options(unsigned options) +{ + lcd_yuv_options = options; } /* Line write helper function for lcd_yuv_blit. Write two lines of yuv420. */ extern void lcd_write_yuv420_lines(fb_data *dst, - unsigned char chroma_buf[LCD_HEIGHT/2*3], unsigned char const * const src[3], int width, int stride); +extern void lcd_write_yuv420_lines_odither(fb_data *dst, + unsigned char const * const src[3], + int width, + int stride, + int x_screen, /* To align dither pattern */ + int y_screen); /* Performance function to blit a YUV bitmap directly to the LCD */ /* For the Gigabeat - show it rotated */ /* So the LCD_WIDTH is now the height */ @@ -171,7 +180,6 @@ void lcd_yuv_blit(unsigned char * const src[3], { /* Caches for chroma data so it only need be recaculated every other line */ - unsigned char chroma_buf[LCD_HEIGHT/2*3]; /* 480 bytes */ unsigned char const * yuv_src[3]; off_t z; @@ -182,23 +190,39 @@ void lcd_yuv_blit(unsigned char * const src[3], width &= ~1; height >>= 1; - fb_data *dst = (fb_data*)FRAME1 + x * LCD_WIDTH + (LCD_WIDTH - y) - 1; + y = LCD_WIDTH - 1 - y; + fb_data *dst = (fb_data*)FRAME + x * LCD_WIDTH + y; z = stride*src_y; yuv_src[0] = src[0] + z + src_x; yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); yuv_src[2] = src[2] + (yuv_src[1] - src[1]); - do + if (lcd_yuv_options & LCD_YUV_DITHER) + { + do + { + lcd_write_yuv420_lines_odither(dst, yuv_src, width, stride, y, x); + yuv_src[0] += stride << 1; /* Skip down two luma lines */ + yuv_src[1] += stride >> 1; /* Skip down one chroma line */ + yuv_src[2] += stride >> 1; + dst -= 2; + y -= 2; + } + while (--height > 0); + } + else { - lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width, - stride); - yuv_src[0] += stride << 1; /* Skip down two luma lines */ - yuv_src[1] += stride >> 1; /* Skip down one chroma line */ - yuv_src[2] += stride >> 1; - dst -= 2; + do + { + lcd_write_yuv420_lines(dst, yuv_src, width, stride); + yuv_src[0] += stride << 1; /* Skip down two luma lines */ + yuv_src[1] += stride >> 1; /* Skip down one chroma line */ + yuv_src[2] += stride >> 1; + dst -= 2; + } + while (--height > 0); } - while (--height > 0); } void lcd_set_contrast(int val) { diff --git a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c index e8ec49544..e11643921 100644 --- a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c @@ -21,16 +21,20 @@ #include "mmu-arm.h" void memory_init(void) { +#if 0 ttb_init(); set_page_tables(); enable_mmu(); +#endif } void set_page_tables() { +#if 0 map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */ /*This pa *might* change*/ map_section(0x80000000, 0, 64, CACHE_ALL); /* map RAM to 0 and enable caching for it */ map_section((int)FRAME1, (int)FRAME1, 1, BUFFERED); /* enable buffered writing for the framebuffer */ map_section((int)FRAME2, (int)FRAME2, 1, BUFFERED); +#endif } diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c index b62051e41..8485679aa 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c @@ -27,8 +27,6 @@ static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */ -void fiq_handler(void) __attribute__((naked)); - void pcm_play_lock(void) { } @@ -77,12 +75,6 @@ void pcm_play_dma_pause(bool pause) { } -/* Get more samples to play out - call pcm_play_dma_stop and - pcm_play_dma_stopped_callback if the data runs out */ -void fiq_handler(void) -{ -} - /* Set the pcm frequency hardware will use when play is next started or when pcm_apply_settings is called. Do not apply the setting to the hardware here but simply cache it. */ diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c index 544ae3afe..ed5a26cd6 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c @@ -13,27 +13,15 @@ int system_memory_guard(int newmode) return 0; } -extern void timer4(void); -extern void dma0(void); /* free */ -extern void dma1(void); -extern void dma3(void); - -void irq_handler(void) -{ -} - -#ifdef BOOTLOADER -void fiq_handler(void) -{ -} -#endif - void system_reboot(void) { } void system_init(void) { +#ifndef BOOTLOADER + avic_init(); +#endif } inline void dumpregs(void) diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index e87b93b13..1f7a2475a 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h @@ -19,15 +19,15 @@ #ifndef SYSTEM_TARGET_H #define SYSTEM_TARGET_H -#include "mmu-imx31.h" #include "system-arm.h" +#include "mmu-arm.h" #define CPUFREQ_NORMAL 532000000 static inline void udelay(unsigned int usecs) { volatile signed int stop = EPITCNT1 - usecs; - while (EPITCNT1 > stop); + while ((signed int)EPITCNT1 > stop); } #define __dbg_hw_info(...) 0 @@ -36,6 +36,22 @@ static inline void udelay(unsigned int usecs) #define HAVE_INVALIDATE_ICACHE static inline void invalidate_icache(void) { + long rd = 0; + asm volatile( + "mcr p15, 0, %0, c7, c10, 0 \n" + "mcr p15, 0, %0, c7, c5, 0 \n" + : : "r"(rd) + ); +} + +#define HAVE_FLUSH_ICACHE +static inline void flush_icache(void) +{ + long rd = 0; + asm volatile ( + "mcr p15, 0, %0, c7, c10, 0 \n" + : : "r"(rd) + ); } struct ARM_REGS { diff --git a/firmware/thread.c b/firmware/thread.c index fdef2cdf2..41160a080 100644 --- a/firmware/thread.c +++ b/firmware/thread.c @@ -750,6 +750,18 @@ static inline void core_sleep(void) { #warning TODO: Implement core_sleep } +#elif CONFIG_CPU == IMX31L +static inline void core_sleep(void) +{ + asm volatile ( + "mov r0, #0 \n" + "mcr p15, 0, r0, c7, c0, 4 \n" /* Wait for interrupt */ + "mrs r0, cpsr \n" /* Unmask IRQ/FIQ at core level */ + "bic r0, r0, #0xc0 \n" + "msr cpsr_c, r0 \n" + : : : "r0" + ); +} #else static inline void core_sleep(void) { @@ -2542,6 +2554,9 @@ void init_threads(void) struct thread_entry *thread; int slot; + memset(threads, 0, sizeof(threads)); + memset(cores, 0, sizeof(cores)); + /* CPU will initialize first and then sleep */ slot = find_empty_thread_slot(); -- 2.11.4.GIT