From 949379d0047ed303c1564c42e559da905eedb0b6 Mon Sep 17 00:00:00 2001 From: mcuelenaere Date: Tue, 4 Nov 2008 20:30:01 +0000 Subject: [PATCH] Onda VX747: clean up's, bug fixes and reworks git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19007 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/config-ondavx747.h | 11 +- firmware/export/config-ondavx767.h | 5 + firmware/export/config.h | 3 +- firmware/export/jz4740.h | 143 ++++++++++++++------- firmware/export/mipsregs.h | 2 +- firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | 22 ++-- .../target/mips/ingenic_jz47xx/system-jz4740.c | 23 +++- .../target/mips/ingenic_jz47xx/system-target.h | 6 +- firmware/thread.c | 2 +- 9 files changed, 149 insertions(+), 68 deletions(-) diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h index 38bc5d7b0..e52b38700 100644 --- a/firmware/export/config-ondavx747.h +++ b/firmware/export/config-ondavx747.h @@ -33,8 +33,15 @@ /* For Rolo and boot loader */ #define MODEL_NUMBER 35 -/* define this if you use an ATA controller */ -//#define CONFIG_STORAGE STORAGE_ATA +#define HAVE_ATA_SD +#define HAVE_HOTSWAP + +//#define CONFIG_STORAGE (STORAGE_NAND | STORAGE_SD) +#define CONFIG_STORAGE STORAGE_NAND /* Multivolume currently handled at firmware/target/ level */ + +#define CONFIG_NAND NAND_CC + +#define HAVE_MULTIVOLUME /* define this if you have a bitmap LCD display */ #define HAVE_LCD_BITMAP diff --git a/firmware/export/config-ondavx767.h b/firmware/export/config-ondavx767.h index bbead7613..7a635b50e 100644 --- a/firmware/export/config-ondavx767.h +++ b/firmware/export/config-ondavx767.h @@ -36,6 +36,11 @@ /* define this if you use an ATA controller */ //#define CONFIG_STORAGE STORAGE_ATA +#define HAVE_ATA_SD +#define HAVE_HOTSWAP + +#define HAVE_MULTIVOLUME + /* define this if you have a bitmap LCD display */ #define HAVE_LCD_BITMAP diff --git a/firmware/export/config.h b/firmware/export/config.h index 914ac1ee9..4cabaddaa 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -193,6 +193,7 @@ #define NAND_IFP7XX 1 #define NAND_TCC 2 #define NAND_SAMSUNG 3 +#define NAND_CC 4 /* ChinaChip */ /* CONFIG_RTC */ #define RTC_M41ST84W 1 /* Archos Recorder */ @@ -434,7 +435,7 @@ #endif /* BOOTLOADER */ -#ifdef HAVE_USBSTACK +#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) #define HAVE_WAKEUP_OBJECTS #endif diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index 3688819b1..45767b26c 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h @@ -1247,6 +1247,49 @@ #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) +#define ICDC_CDCCR1_ELININ (1 << 29) +#define ICDC_CDCCR1_EMIC (1 << 28) +#define ICDC_CDCCR1_SW1ON (1 << 27) +#define ICDC_CDCCR1_EADC (1 << 26) +#define ICDC_CDCCR1_SW2ON (1 << 25) +#define ICDC_CDCCR1_EDAC (1 << 24) +#define ICDC_CDCCR1_PDVR (1 << 20) +#define ICDC_CDCCR1_PDVRA (1 << 19) +#define ICDC_CDCCR1_VRPLD (1 << 18) +#define ICDC_CDCCR1_VRCGL (1 << 17) +#define ICDC_CDCCR1_VRCGH (1 << 16) +#define ICDC_CDCCR1_HPMUTE (1 << 14) +#define ICDC_CDCCR1_HPOV0 (1 << 13) +#define ICDC_CDCCR1_HPCG (1 << 12) +#define ICDC_CDCCR1_HPPLDM (1 << 11) +#define ICDC_CDCCR1_HPPLDR (1 << 10) +#define ICDC_CDCCR1_PDHPM (1 << 9) +#define ICDC_CDCCR1_PDHP (1 << 8) +#define ICDC_CDCCR1_SUSPD (1 << 1) +#define ICDC_CDCCR1_RST (1 << 0) + +#define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16) +#define ICDC_CDCCR2_SMPR(n) ((n & 4) << 8) +#define ICDC_CDCCR2_MICBG(n) ((n & 2) << 4) +#define ICDC_CDCCR2_HPVOL(n) ((n & 2) << 0) + +#define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5) + +#define ICDC_CDCCR2_SMPR_8 (0) +#define ICDC_CDCCR2_SMPR_11 (1) +#define ICDC_CDCCR2_SMPR_12 (2) +#define ICDC_CDCCR2_SMPR_16 (3) +#define ICDC_CDCCR2_SMPR_22 (4) +#define ICDC_CDCCR2_SMPR_24 (5) +#define ICDC_CDCCR2_SMPR_32 (6) +#define ICDC_CDCCR2_SMPR_44 (7) +#define ICDC_CDCCR2_SMPR_48 (8) + +#define ICDC_CDCCR2_HPVOL_0 (0) +#define ICDC_CDCCR2_HPVOL_2 (1) +#define ICDC_CDCCR2_HPVOL_4 (2) +#define ICDC_CDCCR2_HPVOL_6 (3) + /************************************************************************* * I2C @@ -2281,43 +2324,43 @@ /************************************************************************* * USB Device *************************************************************************/ -#define USB_BASE UDC_BASE +#define USB_BASE UDC_BASE -#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ -#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ -#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ -#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ -#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ +#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ +#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ +#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ +#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ +#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ -#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ +#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ -#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ -#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ +#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ +#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ -#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ -#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ -#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ -#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ -#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ -#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ +#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ +#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ +#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ +#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ +#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ +#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ #define USB_FIFO_EP0 (USB_BASE + 0x20) #define USB_FIFO_EP1 (USB_BASE + 0x24) #define USB_FIFO_EP2 (USB_BASE + 0x28) -#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ -#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ +#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ +#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts 8-bit */ -#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control 32-bit */ -#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr 32-bit */ -#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count 32-bit */ -#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control 32-bit */ -#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr 32-bit */ -#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count 32-bit */ +#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control 32-bit */ +#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr 32-bit */ +#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count 32-bit */ +#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control 32-bit */ +#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr 32-bit */ +#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count 32-bit */ #define REG_USB_REG_FADDR REG8(USB_REG_FADDR) #define REG_USB_REG_POWER REG8(USB_REG_POWER) @@ -2382,48 +2425,52 @@ #define USB_CSR0_SVDSETUPEND 0x80 /* Endpoint CSR register bits */ -#define USB_INCSRH_AUTOSET 0x80 -#define USB_INCSRH_ISO 0x40 +#define USB_INCSRH_AUTOSET 0x80 +#define USB_INCSRH_ISO 0x40 #define USB_INCSRH_MODE 0x20 -#define USB_INCSRH_DMAREQENAB 0x10 -#define USB_INCSRH_DMAREQMODE 0x04 -#define USB_INCSR_CDT 0x40 +#define USB_INCSRH_DMAREQENAB 0x10 +#define USB_INCSRH_DMAREQMODE 0x04 +#define USB_INCSR_CDT 0x40 #define USB_INCSR_SENTSTALL 0x20 #define USB_INCSR_SENDSTALL 0x10 -#define USB_INCSR_FF 0x08 -#define USB_INCSR_UNDERRUN 0x04 +#define USB_INCSR_FF 0x08 +#define USB_INCSR_UNDERRUN 0x04 #define USB_INCSR_FFNOTEMPT 0x02 -#define USB_INCSR_INPKTRDY 0x01 +#define USB_INCSR_INPKTRDY 0x01 #define USB_OUTCSRH_AUTOCLR 0x80 #define USB_OUTCSRH_ISO 0x40 -#define USB_OUTCSRH_DMAREQENAB 0x20 -#define USB_OUTCSRH_DNYT 0x10 -#define USB_OUTCSRH_DMAREQMODE 0x08 -#define USB_OUTCSR_CDT 0x80 -#define USB_OUTCSR_SENTSTALL 0x40 -#define USB_OUTCSR_SENDSTALL 0x20 -#define USB_OUTCSR_FF 0x10 -#define USB_OUTCSR_DATAERR 0x08 -#define USB_OUTCSR_OVERRUN 0x04 -#define USB_OUTCSR_FFFULL 0x02 -#define USB_OUTCSR_OUTPKTRDY 0x01 +#define USB_OUTCSRH_DMAREQENAB 0x20 +#define USB_OUTCSRH_DNYT 0x10 +#define USB_OUTCSRH_DMAREQMODE 0x08 +#define USB_OUTCSR_CDT 0x80 +#define USB_OUTCSR_SENTSTALL 0x40 +#define USB_OUTCSR_SENDSTALL 0x20 +#define USB_OUTCSR_FF 0x10 +#define USB_OUTCSR_DATAERR 0x08 +#define USB_OUTCSR_OVERRUN 0x04 +#define USB_OUTCSR_FFFULL 0x02 +#define USB_OUTCSR_OUTPKTRDY 0x01 /* Testmode register bits */ -#define USB_TEST_SE0NAK 0x01 +#define USB_TEST_SE0NAK 0x01 #define USB_TEST_J 0x02 #define USB_TEST_K 0x04 -#define USB_TEST_PACKET 0x08 +#define USB_TEST_PACKET 0x08 /* DMA control bits */ #define USB_CNTL_ENA 0x01 -#define USB_CNTL_DIR_IN 0x02 -#define USB_CNTL_MODE_1 0x04 +#define USB_CNTL_DIR_IN 0x02 +#define USB_CNTL_MODE_1 0x04 #define USB_CNTL_INTR_EN 0x08 -#define USB_CNTL_EP(n) ((n) << 4) +#define USB_CNTL_EP(n) ((n) << 4) #define USB_CNTL_BURST_0 (0 << 9) #define USB_CNTL_BURST_4 (1 << 9) #define USB_CNTL_BURST_8 (2 << 9) -#define USB_CNTL_BURST_16 (3 << 9) +#define USB_CNTL_BURST_16 (3 << 9) + +/* DMA interrupt bits */ +#define USB_INTR_DMA_BULKIN 1 +#define USB_INTR_DMA_BULKOUT 2 //---------------------------------------------------------------------- diff --git a/firmware/export/mipsregs.h b/firmware/export/mipsregs.h index 2ac5202ed..8898bbd47 100644 --- a/firmware/export/mipsregs.h +++ b/firmware/export/mipsregs.h @@ -545,7 +545,7 @@ */ #define __read_32bit_c0_register(source, sel) \ -({ int __res; \ +({ unsigned int __res; \ if (sel == 0) \ __asm__ __volatile__( \ "mfc0\t%0, " #source "\n\t" \ diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c index af5a132e3..0b105b35a 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c @@ -59,27 +59,27 @@ void lcd_update_rect(int x, int y, int width, int height) { lcd_set_target(x, y, width, height); - REG_DMAC_DCCSR(0) = 0; - REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ - REG_DMAC_DSAR(0) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF; - REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */ - REG_DMAC_DTCR(0) = width*height; + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = 0; + REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ + REG_DMAC_DSAR(DMA_LCD_CHANNEL) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF; + REG_DMAC_DTAR(DMA_LCD_CHANNEL) = 0x130500B0; /* SLCD_FIFO */ + REG_DMAC_DTCR(DMA_LCD_CHANNEL) = width*height; - REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */ - | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ - REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ + REG_DMAC_DCMD(DMA_LCD_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */ + | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; /* (1 << 31) */ __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size */ while(REG_SLCD_STATE & SLCD_STATE_BUSY); REG_SLCD_CTRL = SLCD_CTRL_DMA_EN; - REG_DMAC_DMACR = DMAC_DMACR_DMAE; + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; - while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) ) + while( !(REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) ) yield(); - REG_DMAC_DMACR = 0; + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; while(REG_SLCD_STATE & SLCD_STATE_BUSY); REG_SLCD_CTRL = 0; diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 1a41723ff..89011e1ba 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c @@ -389,6 +389,7 @@ void udelay(unsigned int usec) : "0" (i) ); } + void mdelay(unsigned int msec) { unsigned int i; @@ -437,7 +438,7 @@ void sti(void) #define SYNC_WB() __asm__ __volatile__ ("sync") -#define __CACHE_OP(op, addr) \ +#define __CACHE_OP(op, addr) \ __asm__ __volatile__( \ " .set noreorder \n" \ " .set mips32\n\t \n" \ @@ -632,6 +633,20 @@ static void tlb_call_refill(void) ); } +static void dma_init(void) +{ + __cpm_start_dmac(); + + REG_DMAC_DCCSR(0) = 0; + REG_DMAC_DCCSR(1) = 0; + REG_DMAC_DCCSR(2) = 0; + REG_DMAC_DCCSR(3) = 0; + REG_DMAC_DCCSR(4) = 0; + REG_DMAC_DCCSR(5) = 0; + + REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE); +} + extern int main(void); extern void except_common_entry(void); @@ -660,12 +675,14 @@ void system_main(void) dis_irq(i); tlb_init(); + dma_init(); detect_clock(); + /* Enable interrupts at core level */ sti(); - main(); + main(); /* Shouldn't return */ while(1); } @@ -686,7 +703,7 @@ void power_off(void) /* Put system into hibernate mode */ __rtc_clear_alarm_flag(); __rtc_clear_hib_stat_all(); - //__rtc_set_scratch_pattern(0x12345678); + /* __rtc_set_scratch_pattern(0x12345678); */ __rtc_enable_alarm_wakeup(); __rtc_set_hrcr_val(0xfe0); __rtc_set_hwfcr_val((0xFFFF << 4)); diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h index 01ba176dd..39bf35bba 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-target.h +++ b/firmware/target/mips/ingenic_jz47xx/system-target.h @@ -102,5 +102,9 @@ void mdelay(unsigned int msec); void power_off(void); void system_reboot(void); -#endif /* __SYSTEM_TARGET_H_ */ +#define DMA_LCD_CHANNEL 0 +#define DMA_NAND_CHANNEL 1 +#define DMA_USB_CHANNEL 2 +#define DMA_AIC_TX_CHANNEL 3 +#endif /* __SYSTEM_TARGET_H_ */ diff --git a/firmware/thread.c b/firmware/thread.c index 399f6ef02..23463f596 100644 --- a/firmware/thread.c +++ b/firmware/thread.c @@ -997,7 +997,7 @@ static void __attribute__((used)) _start_thread(void) "lw $8, 4($9) \n" /* Fetch thread function pointer ($8 = $t0, $9 = $t1) */ "lw $29, 40($9) \n" /* Set initial sp(=$29) */ "sw $0, 48($9) \n" /* Clear start address */ - "jalr $8 \n" /* Start the thread */ + "jr $8 \n" /* Start the thread */ "nop \n" ".set at \n" ".set reorder \n" -- 2.11.4.GIT