From 5cd381727e4480bf0717837e9c64d65d30a2fc4f Mon Sep 17 00:00:00 2001
From: bertrik <bertrik@a1c6a512-1295-4272-9138-f99709370657>
Date: Fri, 18 Jun 2010 18:32:38 +0000
Subject: [PATCH] as3525v2: document PLL bits and show current PLL frequency in
 the debug menu

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26930 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/as3525/clock-target.h | 12 +++++++++++-
 firmware/target/arm/as3525/debug-as3525.c | 19 ++++++++++++++++---
 2 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 96c2c264f..1689c5944 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -62,10 +62,20 @@
 #if CONFIG_CPU == AS3525v2
 
 /* PLLA & PLLB registers differ from AS3525(v1)
- * so we use a setting with a known frequency */
+ * PLL bits:
+ * - bit 0-6 = F-1 (F=multiplier)
+ * - bit 7-9 = R-1 (R=divisor)
+ * - bit 10  = OD (output divider)? Divides by 2 if set.
+ * - bit 11  = unknown (no effect)
+ * - bit 12  = unknown (always set to 1)
+ * Fpll = Fin * F / (R * OD), where Fin = 12 MHz
+ */
 #define AS3525_PLLA_FREQ        240000000
 #define AS3525_PLLA_SETTING     0x113B
 
+#define AS3525_PLLB_FREQ        192000000
+#define AS3525_PLLB_SETTING     0x155F
+
 #define AS3525_FCLK_PREDIV      0
 #define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
 
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c
index 2528b1a8a..e6ae3a4a5 100644
--- a/firmware/target/arm/as3525/debug-as3525.c
+++ b/firmware/target/arm/as3525/debug-as3525.c
@@ -112,14 +112,27 @@ static int calc_freq(int clk)
                                                (((CGU_PLLB>>8) & 0x1f)*out_div);
             return 0;
 #else
+    int od, f, r;
+
     /* AS3525v2  */
     switch(clk) {
-        /*  we're using a known setting for PLLA = 240 MHz and PLLB inop  */
         case CLK_PLLA:
-            return 240000000;
+            if(CGU_PLLASUP & (1<<3))
+                return 0;
+
+            f = (CGU_PLLA & 0x7F) + 1;
+            r = ((CGU_PLLA >> 7) & 0x7) + 1;
+            od = (CGU_PLLA >> 10) & 1 ? 2 : 1;
+            return (CLK_MAIN / 2) * f / (r * od);
 
         case CLK_PLLB:
-            return 0;
+            if(CGU_PLLBSUP & (1<<3))
+                return 0;
+
+            f = (CGU_PLLB & 0x7F) + 1;
+            r = ((CGU_PLLB >> 7) & 0x7) + 1;
+            od = (CGU_PLLB >> 10) & 1 ? 2 : 1;
+            return (CLK_MAIN / 2) * f / (r * od);
 #endif
         case CLK_PROC:
 #if CONFIG_CPU == AS3525 /* not in arm926-ejs */
-- 
2.11.4.GIT