firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "led.h"
  27 #include "sdmmc.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "cpu.h"
  31 #include <stdio.h>
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include "as3525v2.h"
  35 #include "pl081.h"  /* DMA controller */
  36 #include "dma-target.h" /* DMA request lines */
  37 #include "clock-target.h"
  38 #include "panic.h"
  39 #include "stdbool.h"
  40 #include "ata_idle_notify.h"
  41 #include "sd.h"
  42 #include "usb.h"
  43
  44 #ifdef HAVE_HOTSWAP
  45 #include "disk.h"
  46 #endif
  47
  48 #ifdef SANSA_FUZEV2
  49 #include "backlight-target.h"
  50 #endif
  51
  52 #include "lcd.h"
  53 #include <stdarg.h>
  54 #include "sysfont.h"
  55
  56 #define     INTERNAL_AS3525  0   /* embedded SD card */
  57 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  58
  59 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  60 #define AMS_OF_SIZE 0xf000
  61
  62 /* command flags */
  63 #define MCI_NO_RESP     (0<<0)
  64 #define MCI_RESP        (1<<0)
  65 #define MCI_LONG_RESP   (1<<1)
  66
  67 /* controller registers */
  68 #define SD_BASE 0xC6070000
  69
  70 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  71
  72 #define MCI_CTRL        SD_REG(0x00)
  73
  74 /* control bits */
  75 #define CTRL_RESET      (1<<0)
  76 #define FIFO_RESET      (1<<1)
  77 #define DMA_RESET       (1<<2)
  78 #define INT_ENABLE      (1<<4)
  79 #define DMA_ENABLE      (1<<5)
  80 #define READ_WAIT       (1<<6)
  81 #define SEND_IRQ_RESP   (1<<7)
  82 #define ABRT_READ_DATA  (1<<8)
  83 #define SEND_CCSD       (1<<9)
  84 #define SEND_AS_CCSD    (1<<10)
  85 #define EN_OD_PULLUP    (1<<24)
  86
  87
  88 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  89
  90 #define PWR_CRD_0       (1<<0)
  91 #define PWR_CRD_1       (1<<1)
  92 #define PWR_CRD_2       (1<<2)
  93 #define PWR_CRD_3       (1<<3)
  94
  95 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  96 /* CLK_DIV_0 :    bits 7:0
  97  * CLK_DIV_1 :    bits 15:8
  98  * CLK_DIV_2 :    bits 23:16
  99  * CLK_DIV_3 :    bits 31:24
 100  */
 101
 102 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 103 /* CLK_SRC_CRD0:  bits 1:0
 104  * CLK_SRC_CRD1:  bits 3:2
 105  * CLK_SRC_CRD2:  bits 5:4
 106  * CLK_SRC_CRD3:  bits 7:6
 107  */
 108
 109 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 110
 111 #define CCLK_ENA_CRD0   (1<<0)
 112 #define CCLK_ENA_CRD1   (1<<1)
 113 #define CCLK_ENA_CRD2   (1<<2)
 114 #define CCLK_ENA_CRD3   (1<<3)
 115 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 116 #define CCLK_LP_CRD1    (1<<17)
 117 #define CCLK_LP_CRD2    (1<<18)
 118 #define CCLK_LP_CRD3    (1<<19)
 119
 120 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 121 /* response timeout bits 0:7
 122  * data timeout bits     8:31
 123  */
 124
 125 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 126                                         /* 1 bit per card, set = wide bus */
 127 #define WIDTH4_CRD0     (1<<0)
 128 #define WIDTH4_CRD1     (1<<1)
 129 #define WIDTH4_CRD2     (1<<2)
 130 #define WIDTH4_CRD3     (1<<3)
 131
 132 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 133 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 134 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 135
 136
 137
 138 #define MCI_ARGUMENT    SD_REG(0x28)
 139 #define MCI_COMMAND     SD_REG(0x2C)
 140
 141 /* command bits (bits 5:0 are the command index) */
 142 #define CMD_RESP_EXP_BIT        (1<<6)
 143 #define CMD_RESP_LENGTH_BIT     (1<<7)
 144 #define CMD_CHECK_CRC_BIT       (1<<8)
 145 #define CMD_DATA_EXP_BIT        (1<<9)
 146 #define CMD_RW_BIT              (1<<10)
 147 #define CMD_TRANSMODE_BIT       (1<<11)
 148 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 149 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 150 #define CMD_ABRT_CMD_BIT        (1<<14)
 151 #define CMD_SEND_INIT_BIT       (1<<15)
 152 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 153 #define CMD_SEND_CLK_ONLY       (1<<21)
 154 #define CMD_READ_CEATA          (1<<22)
 155 #define CMD_CCS_EXPECTED        (1<<23)
 156 #define CMD_DONE_BIT            (1<<31)
 157
 158 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 159                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 160
 161 #define MCI_RESP0       SD_REG(0x30)
 162 #define MCI_RESP1       SD_REG(0x34)
 163 #define MCI_RESP2       SD_REG(0x38)
 164 #define MCI_RESP3       SD_REG(0x3C)
 165
 166 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 167 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 168                                          * status clear */
 169
 170 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 171 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 172 #define MCI_INT_RE      (1<<1)      /* x         response error */
 173 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 174 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 175 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 176 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 177 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 178 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 179 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 180 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 181 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 182 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 183 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 184 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 185 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 186 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 187 #define MCI_INT_SDIO    (0xf<<16)
 188
 189 /*
 190  *  STATUS register
 191  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 192  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 193  *  & 8         = MCI_INT_DTO
 194  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 195  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 196  */
 197
 198 #define MCI_CMD_ERROR    \
 199          (MCI_INT_RE   | \
 200           MCI_INT_RCRC | \
 201           MCI_INT_RTO  | \
 202           MCI_INT_HLE)
 203
 204 #define MCI_DATA_ERROR    \
 205         ( MCI_INT_DCRC  | \
 206           MCI_INT_DRTO  | \
 207           MCI_INT_HTO   | \
 208           MCI_INT_FRUN  | \
 209           MCI_INT_HLE   | \
 210           MCI_INT_SBE   | \
 211           MCI_INT_EBE)
 212
 213 #define MCI_STATUS      SD_REG(0x48)
 214
 215 #define FIFO_RX_WM              (1<<0)
 216 #define FIFO_TX_WM              (1<<1)
 217 #define FIFO_EMPTY              (1<<2)
 218 #define FIFO_FULL               (1<<3)
 219 #define CMD_FSM_STATE_B0        (1<<4)
 220 #define CMD_FSM_STATE_B1        (1<<5)
 221 #define CMD_FSM_STATE_B2        (1<<6)
 222 #define CMD_FSM_STATE_B3        (1<<7)
 223 #define DATA_3_STAT             (1<<8)
 224 #define DATA_BUSY               (1<<9)
 225 #define DATA_STAT_MC_BUSY       (1<<10)
 226 #define RESP_IDX_B0             (1<<11)
 227 #define RESP_IDX_B1             (1<<12)
 228 #define RESP_IDX_B2             (1<<13)
 229 #define RESP_IDX_B3             (1<<14)
 230 #define RESP_IDX_B4             (1<<15)
 231 #define RESP_IDX_B5             (1<<16)
 232 #define FIFO_CNT_B00            (1<<17)
 233 #define FIFO_CNT_B01            (1<<18)
 234 #define FIFO_CNT_B02            (1<<19)
 235 #define FIFO_CNT_B03            (1<<20)
 236 #define FIFO_CNT_B04            (1<<21)
 237 #define FIFO_CNT_B05            (1<<22)
 238 #define FIFO_CNT_B06            (1<<23)
 239 #define FIFO_CNT_B07            (1<<24)
 240 #define FIFO_CNT_B08            (1<<25)
 241 #define FIFO_CNT_B09            (1<<26)
 242 #define FIFO_CNT_B10            (1<<27)
 243 #define FIFO_CNT_B11            (1<<28)
 244 #define FIFO_CNT_B12            (1<<29)
 245 #define DMA_ACK                 (1<<30)
 246 #define START_CMD               (1<<31)
 247
 248 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 249 /* TX watermark :    bits 11:0
 250  * RX watermark :    bits 27:16
 251  * DMA MTRANS SIZE : bits 30:28
 252  * bits 31, 15:12 : unused
 253  */
 254 #define MCI_FIFOTH_MASK 0x8000f000
 255
 256 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 257
 258 #define CDETECT_CRD_0   (1<<0)
 259 #define CDETECT_CRD_1   (1<<1)
 260 #define CDETECT_CRD_2   (1<<2)
 261 #define CDETECT_CRD_3   (1<<3)
 262
 263 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 264 #define MCI_GPIO        SD_REG(0x58)
 265 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 266 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 267 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 268 #define MCI_USRID       SD_REG(0x68)    /* user id */
 269 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 270
 271 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 272 /* bit  0       : card type
 273  * bits 5:1     : maximum card index
 274  * bit  6       : BUS TYPE
 275  * bits 9:7     : DATA WIDTH
 276  * bits 15:10   : ADDR WIDTH
 277  * bits 17:16   : DMA IF
 278  * bits 20:18   : DMA WIDTH
 279  * bit  21      : FIFO RAM INSIDE
 280  * bit  22      : IMPL HOLD REG
 281  * bit  23      : SET CLK FALSE
 282  * bits 25:24   : MAX CLK DIV IDX
 283  * bit  26      : AREA OPTIM
 284  */
 285
 286 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 287 /* bit  0       : SWR
 288  * bit  1       : FB
 289  * bits 6:2     : DSL
 290  * bit  7       : DE
 291  * bit  10:8    : PBL
 292  */
 293
 294 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 295 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 296 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 297 /* bit  0       : TI
 298  * bit  1       : RI
 299  * bit  2       : FBE
 300  * bit  3       : unused
 301  * bit  4       : DU
 302  * bit  5       : CES
 303  * bits 7:6     : unused
 304  * bits 8       : NIS
 305  * bit  9       : AIS
 306  * bits 12:10   : EB
 307  * bits 16:13   : FSM
 308  */
 309
 310 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 311 /* bit  0       : TI
 312  * bit  1       : RI
 313  * bit  2       : FBE
 314  * bit  3       : unused
 315  * bit  4       : DU
 316  * bit  5       : CES
 317  * bits 7:6     : unused
 318  * bits 8       : NI
 319  * bit  9       : AI
 320  */
 321 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 322 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 323
 324 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 325
 326 #define UNALIGNED_NUM_SECTORS 10
 327 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 328 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 329
 330 static tCardInfo card_info[NUM_DRIVES];
 331
 332 /* for compatibility */
 333 static long last_disk_activity = -1;
 334
 335 #define MIN_YIELD_PERIOD 5  /* ticks */
 336 static long next_yield = 0;
 337
 338 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 339 static const char         sd_thread_name[] = "ata/sd";
 340 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 341 static struct event_queue sd_queue;
 342 #ifndef BOOTLOADER
 343 bool sd_enabled = false;
 344 #endif
 345
 346 static struct wakeup transfer_completion_signal;
 347 static struct wakeup command_completion_signal;
 348 static volatile bool retry;
 349 static volatile int cmd_error;
 350
 351 #if defined(HAVE_MULTIDRIVE)
 352 #define EXT_SD_BITS (1<<2)
 353 #endif
 354
 355 static inline void mci_delay(void) { udelay(1000); }
 356
 357 void INT_NAND(void)
 358 {
 359     MCI_CTRL &= ~INT_ENABLE;
 360     /* use raw status here as we need to check some Ints that are masked */
 361     const int status = MCI_RAW_STATUS;
 362
 363     MCI_RAW_STATUS = status;    /* clear status */
 364
 365     if(status & MCI_DATA_ERROR)
 366         retry = true;
 367
 368     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 369         wakeup_signal(&transfer_completion_signal);
 370
 371     cmd_error = status & MCI_CMD_ERROR;
 372
 373     if(status & MCI_INT_CD)
 374         wakeup_signal(&command_completion_signal);
 375
 376     MCI_CTRL |= INT_ENABLE;
 377 }
 378
 379 static inline bool card_detect_target(void)
 380 {
 381 #if defined(HAVE_MULTIDRIVE)
 382 #if defined(SANSA_FUZEV2)
 383     return GPIOA_PIN(2);
 384 #elif defined(SANSA_CLIPPLUS)
 385     return !(GPIOA_PIN(2));
 386 #else
 387 #error "microSD pin not defined for your target"
 388 #endif
 389 #else
 390     return false;
 391 #endif
 392 }
 393
 394 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 395         unsigned long *response)
 396 {
 397     int card_no;
 398
 399 #if defined(HAVE_MULTIDRIVE)
 400     if(sd_present(SD_SLOT_AS3525))
 401         GPIOB_PIN(5) = (1-drive) << 5;
 402 #endif
 403
 404     MCI_ARGUMENT = arg;
 405
 406 #ifdef SANSA_FUZEV2
 407     if (fuzev2_variant == 1)
 408         card_no = 1 << 16;
 409     else
 410 #endif
 411         card_no = CMD_CARD_NO(drive);
 412
 413     /* Construct MCI_COMMAND  */
 414     MCI_COMMAND =
 415       /*b5:0*/    cmd
 416       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 417       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 418       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 419       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 420       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 421       /*b11     | CMD_TRANSMODE_BIT       unused  */
 422       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 423       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 424       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 425       /*b15     | CMD_SEND_INIT_BIT       unused  */
 426    /*b20:16 */  |                                      card_no
 427       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 428       /*b22     | CMD_READ_CEATA          unused  */
 429       /*b23     | CMD_CCS_EXPECTED        unused  */
 430       /*b31 */  |                                      CMD_DONE_BIT;
 431
 432 #ifdef SANSA_FUZEV2
 433     extern int buttonlight_is_on;
 434     if(buttonlight_is_on)
 435         _buttonlight_on();
 436     else
 437         _buttonlight_off();
 438 #endif
 439     wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
 440
 441     /*  Handle command responses & errors */
 442     if(flags & MCI_RESP)
 443     {
 444         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 445             return false;
 446
 447         if(flags & MCI_LONG_RESP)
 448         {
 449             response[0] = MCI_RESP3;
 450             response[1] = MCI_RESP2;
 451             response[2] = MCI_RESP1;
 452             response[3] = MCI_RESP0;
 453         }
 454         else
 455             response[0] = MCI_RESP0;
 456     }
 457     return true;
 458 }
 459
 460 static int sd_wait_for_tran_state(const int drive)
 461 {
 462     unsigned long response;
 463     unsigned int timeout = current_tick + 5*HZ;
 464
 465     while (1)
 466     {
 467         while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
 468
 469         if (((response >> 9) & 0xf) == SD_TRAN)
 470             return 0;
 471
 472         if(TIME_AFTER(current_tick, timeout))
 473             return -10 * ((response >> 9) & 0xf);
 474
 475         if (TIME_AFTER(current_tick, next_yield))
 476         {
 477             yield();
 478             next_yield = current_tick + MIN_YIELD_PERIOD;
 479         }
 480     }
 481 }
 482
 483
 484 static int sd_init_card(const int drive)
 485 {
 486     unsigned long response;
 487     long init_timeout;
 488     bool sd_v2 = false;
 489
 490     /*  assume 24 MHz clock / 60 = 400 kHz  */
 491     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 492
 493     /* 100 - 400kHz clock required for Identification Mode  */
 494     /*  Start of Card Identification Mode ************************************/
 495
 496     /* CMD0 Go Idle  */
 497     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 498         return -1;
 499     mci_delay();
 500
 501     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 502       Non v2 cards will not respond to this command*/
 503     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 504         if((response & 0xFFF) == 0x1AA)
 505             sd_v2 = true;
 506
 507     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 508     init_timeout = current_tick + HZ;
 509
 510     do {
 511         /* this timeout is the only valid error for this loop*/
 512         if(TIME_AFTER(current_tick, init_timeout))
 513             return -2;
 514
 515         /* app_cmd */
 516         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 517
 518          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 519         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 520                         MCI_RESP, &card_info[drive].ocr))
 521             return -3;
 522     } while(!(card_info[drive].ocr & (1<<31)) );
 523
 524     /* CMD2 send CID */
 525     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 526         return -4;
 527
 528     /* CMD3 send RCA */
 529     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 530         return -5;
 531
 532 #ifdef HAVE_MULTIDRIVE
 533     /* Make sure we have 2 unique rca numbers */
 534     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 535         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 536             return -6;
 537 #endif
 538     /*  End of Card Identification Mode   ************************************/
 539
 540     /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 541     /*  CMD7 w/rca: Select card to put it in TRAN state */
 542     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 543         return -7;
 544
 545     if(sd_wait_for_tran_state(drive))
 546         return -8;
 547
 548     /* CMD6 */
 549     if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 550         return -9;
 551     mci_delay();
 552
 553     /*  We need to go back to STBY state now so we can read csd */
 554     /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 555     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 556         return -10;
 557
 558     /* CMD9 send CSD */
 559     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 560                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 561         return -11;
 562
 563     sd_parse_csd(&card_info[drive]);
 564
 565     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 566         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 567
 568     /*  Card back to full speed  */
 569     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 570
 571     /*  CMD7 w/rca: Select card to put it in TRAN state */
 572     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 573         return -12;
 574
 575 #ifndef BOOTLOADER
 576     /*  Switch to to 4 bit widebus mode  */
 577     if(sd_wait_for_tran_state(drive) < 0)
 578         return -13;
 579     /* CMD55 */              /*  Response is requested due to timing issue  */
 580     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 581         return -14;
 582     /* ACMD6  */
 583     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
 584         return -15;
 585     mci_delay();
 586     /* CMD55 */             /*  Response is requested due to timing issue  */
 587     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 588         return -16;
 589     /* ACMD42  */
 590     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
 591         return -17;
 592
 593     /* Now that card is widebus make controller aware */
 594 #ifdef SANSA_FUZEV2
 595     if (fuzev2_variant == 1)
 596         MCI_CTYPE |= 1<<1;
 597     else
 598 #endif
 599         MCI_CTYPE |= (1<<drive);
 600
 601 #endif /* ! BOOTLOADER */
 602
 603     /*  Set low power mode  */
 604 #ifdef SANSA_FUZEV2
 605     if (fuzev2_variant == 1)
 606         MCI_CLKENA |= 1<<16;
 607     else
 608 #endif
 609         MCI_CLKENA |= 1<<(drive + 16);
 610
 611     card_info[drive].initialized = 1;
 612
 613     return 0;
 614 }
 615
 616 static void sd_thread(void) __attribute__((noreturn));
 617 static void sd_thread(void)
 618 {
 619     struct queue_event ev;
 620     bool idle_notified = false;
 621
 622     while (1)
 623     {
 624         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 625
 626         switch ( ev.id )
 627         {
 628 #ifdef HAVE_HOTSWAP
 629         case SYS_HOTSWAP_INSERTED:
 630         case SYS_HOTSWAP_EXTRACTED:
 631         {
 632             int microsd_init = 1;
 633             fat_lock();          /* lock-out FAT activity first -
 634                                     prevent deadlocking via disk_mount that
 635                                     would cause a reverse-order attempt with
 636                                     another thread */
 637             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 638                                     into driver that bypass the fat cache */
 639
 640             /* We now have exclusive control of fat cache and ata */
 641
 642             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 643                                     descriptors aren't leaked and any busy
 644                                     ones are invalid if mounting */
 645             /* Force card init for new card, re-init for re-inserted one or
 646              * clear if the last attempt to init failed with an error. */
 647             card_info[SD_SLOT_AS3525].initialized = 0;
 648
 649             if (ev.id == SYS_HOTSWAP_INSERTED)
 650             {
 651                 sd_enable(true);
 652                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 653                 if (microsd_init < 0) /* initialisation failed */
 654                     panicf("microSD init failed : %d", microsd_init);
 655
 656                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 657             }
 658
 659             /*
 660              * Mount succeeded, or this was an EXTRACTED event,
 661              * in both cases notify the system about the changed filesystems
 662              */
 663             if (microsd_init)
 664                 queue_broadcast(SYS_FS_CHANGED, 0);
 665             /* Access is now safe */
 666             mutex_unlock(&sd_mtx);
 667             fat_unlock();
 668             sd_enable(false);
 669         }
 670             break;
 671 #endif
 672         case SYS_TIMEOUT:
 673             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 674             {
 675                 idle_notified = false;
 676             }
 677             else
 678             {
 679                 /* never let a timer wrap confuse us */
 680                 next_yield = current_tick;
 681
 682                 if (!idle_notified)
 683                 {
 684                     call_storage_idle_notifys(false);
 685                     idle_notified = true;
 686                 }
 687             }
 688             break;
 689
 690         case SYS_USB_CONNECTED:
 691             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 692             /* Wait until the USB cable is extracted again */
 693             usb_wait_for_disconnect(&sd_queue);
 694
 695             break;
 696         case SYS_USB_DISCONNECTED:
 697             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 698             break;
 699         }
 700     }
 701 }
 702
 703 static void init_controller(void)
 704 {
 705     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 706     int card_mask = (1 << hcon_numcards) - 1;
 707     int pwr_mask;
 708
 709 #ifdef SANSA_FUZEV2
 710     if (fuzev2_variant == 1)
 711         pwr_mask = 1 << 1;
 712     else
 713 #endif
 714         pwr_mask = card_mask;
 715
 716     MCI_PWREN &= ~pwr_mask;             /*  power off all cards  */
 717     MCI_PWREN = pwr_mask;               /*  power up cards  */
 718
 719     MCI_CTRL |= CTRL_RESET;
 720     while(MCI_CTRL & CTRL_RESET)
 721         ;
 722
 723     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 724
 725     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 726
 727     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 728
 729     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 730
 731     MCI_ARGUMENT = 0;
 732     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 733     while(MCI_COMMAND & CMD_DONE_BIT)
 734         ;
 735
 736     MCI_DEBNCE = 0xfffff;               /* default value */
 737
 738     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 739     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 740
 741 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 742  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 743  *  them masked for now we can check them in the isr by reading raw status when
 744  *  the CD int is triggered.
 745  */
 746     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
 747
 748     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
 749
 750     MCI_BLKSIZ = SD_BLOCK_SIZE;
 751 }
 752
 753 int sd_init(void)
 754 {
 755     int ret;
 756
 757     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 758
 759     CGU_IDE =   (1<<7)          /* AHB interface enable */
 760             |   (AS3525_IDE_DIV << 2)
 761             |   1;              /* clock source = PLLA */
 762
 763     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 764                  |  (AS3525_MS_DIV << 2)
 765                  |  1;          /* clock source = PLLA */
 766
 767     CGU_SDSLOT = (1<<7)         /* interface enable */
 768                | (AS3525_SDSLOT_DIV << 2)
 769                | 1;             /* clock source = PLLA */
 770
 771     wakeup_init(&transfer_completion_signal);
 772     wakeup_init(&command_completion_signal);
 773
 774 #ifdef HAVE_MULTIDRIVE
 775     /* clear previous irq */
 776     GPIOA_IC = EXT_SD_BITS;
 777     /* enable edge detecting */
 778     GPIOA_IS &= ~EXT_SD_BITS;
 779     /* detect both raising and falling edges */
 780     GPIOA_IBE |= EXT_SD_BITS;
 781     /* enable the card detect interrupt */
 782     GPIOA_IE |= EXT_SD_BITS;
 783 #endif /* HAVE_MULTIDRIVE */
 784
 785 #ifndef SANSA_CLIPV2
 786     /* Configure XPD for SD-MCI interface */
 787     bitset32(&CCU_IO, 1<<2);
 788 #endif
 789
 790     VIC_INT_ENABLE = INTERRUPT_NAND;
 791
 792     init_controller();
 793     ret = sd_init_card(INTERNAL_AS3525);
 794     if(ret < 0)
 795         return ret;
 796
 797     /* init mutex */
 798     mutex_init(&sd_mtx);
 799
 800     queue_init(&sd_queue, true);
 801     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 802             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 803
 804 #ifndef BOOTLOADER
 805     sd_enabled = true;
 806     sd_enable(false);
 807 #endif
 808     return 0;
 809 }
 810
 811 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 812                                 int count, void* buf, bool write)
 813 {
 814     int ret = 0;
 815 #ifndef HAVE_MULTIDRIVE
 816     const int drive = 0;
 817 #endif
 818     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 819
 820
 821     mutex_lock(&sd_mtx);
 822 #ifndef BOOTLOADER
 823     sd_enable(true);
 824     led(true);
 825 #endif
 826
 827     if (card_info[drive].initialized <= 0)
 828     {
 829         ret = sd_init_card(drive);
 830         if (!(card_info[drive].initialized))
 831         {
 832             panicf("card not initialised (%d)", ret);
 833             goto sd_transfer_error;
 834         }
 835     }
 836
 837     if(count < 0) /* XXX: why is it signed ? */
 838     {
 839         ret = -18;
 840         goto sd_transfer_error;
 841     }
 842     if((start+count) > card_info[drive].numblocks)
 843     {
 844         ret = -19;
 845         goto sd_transfer_error;
 846     }
 847
 848     /* skip SanDisk OF */
 849     if (drive == INTERNAL_AS3525)
 850         start += AMS_OF_SIZE;
 851
 852     /*  CMD7 w/rca: Select card to put it in TRAN state */
 853     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 854         return -20;
 855
 856     last_disk_activity = current_tick;
 857     dma_retain();
 858
 859     if(aligned)
 860     {
 861         if(write)
 862             clean_dcache_range(buf, count * SECTOR_SIZE);
 863         else
 864             dump_dcache_range(buf, count * SECTOR_SIZE);
 865     }
 866
 867     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 868
 869     do
 870     {
 871         void *dma_buf;
 872         unsigned int transfer = count;
 873
 874         if(aligned)
 875         {
 876             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 877         }
 878         else
 879         {
 880             dma_buf = aligned_buffer;
 881             if(transfer > UNALIGNED_NUM_SECTORS)
 882                 transfer = UNALIGNED_NUM_SECTORS;
 883
 884             if(write)
 885                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 886         }
 887
 888         /* Interrupt handler might set this to true during transfer */
 889         retry = false;
 890
 891         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 892
 893         ret = sd_wait_for_tran_state(drive);
 894         if (ret < 0)
 895         {
 896             static const char *st[9] = {
 897                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 898                                                                 "PRG", "DIS"};
 899             if(ret <= -10)
 900                 panicf("wait for TRAN state failed (%s) %d",
 901                                                     st[(-ret / 10) % 9], drive);
 902             else
 903                 panicf("wait for state failed");
 904             goto sd_transfer_error;
 905         }
 906
 907         int arg = start;
 908         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 909             arg *= SD_BLOCK_SIZE;
 910
 911         if(write)
 912             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 913                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 914         else
 915             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 916                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 917
 918         unsigned long dummy; /* if we don't ask for a response, writing fails */
 919         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 920             panicf("%s multiple blocks failed", write ? "write" : "read");
 921
 922         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 923
 924         last_disk_activity = current_tick;
 925
 926         if(write)
 927         {
 928             /* wait for the card to exit programming state */
 929             while(MCI_STATUS & DATA_BUSY) ;
 930         }
 931
 932         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 933         {
 934             ret = -666;
 935             panicf("STOP TRANSMISSION failed");
 936             goto sd_transfer_error;
 937         }
 938
 939         if(!retry)
 940         {
 941             if(!write && !aligned)
 942                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 943             buf += transfer * SD_BLOCK_SIZE;
 944             start += transfer;
 945             count -= transfer;
 946         }
 947         else   /*  reset controller if we had an error  */
 948         {
 949             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 950             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 951                 ;
 952         }
 953
 954     } while(retry || count);
 955
 956     dma_release();
 957
 958 #ifndef BOOTLOADER
 959     sd_enable(false);
 960     led(false);
 961 #endif
 962     mutex_unlock(&sd_mtx);
 963     return 0;
 964
 965 sd_transfer_error:
 966     panicf("transfer error : %d",ret);
 967     card_info[drive].initialized = 0;
 968     return ret;
 969 }
 970
 971 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 972                     void* buf)
 973 {
 974     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 975 }
 976
 977 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 978                      const void* buf)
 979 {
 980 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 981 #ifdef HAVE_MULTIDRIVE
 982     (void) drive;
 983 #endif
 984     (void) start;
 985     (void) count;
 986     (void) buf;
 987     return -1;
 988 #else
 989     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 990 #endif /* defined(BOOTLOADER) */
 991 }
 992
 993 #ifndef BOOTLOADER
 994 long sd_last_disk_activity(void)
 995 {
 996     return last_disk_activity;
 997 }
 998
 999 void sd_enable(bool on)
1000 {
1001     if (on)
1002     {
1003         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1004         CGU_IDE |= (1<<7);                  /* AHB interface enable */
1005         CGU_MEMSTICK |= (1<<7);             /* interface enable */
1006         CGU_SDSLOT |= (1<<7);               /* interface enable */
1007     }
1008     else
1009     {
1010         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
1011         CGU_MEMSTICK &= ~(1<<7);            /* interface enable */
1012         CGU_IDE &= ~(1<<7);                 /* AHB interface enable */
1013         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1014     }
1015 }
1016
1017 tCardInfo *card_get_info_target(int card_no)
1018 {
1019     return &card_info[card_no];
1020 }
1021 #endif /* BOOTLOADER */
1022
1023 #ifdef HAVE_HOTSWAP
1024 bool sd_removable(IF_MD_NONVOID(int drive))
1025 {
1026     return (drive==1);
1027 }
1028
1029 bool sd_present(IF_MD_NONVOID(int drive))
1030 {
1031     return (drive == 0) ? true : card_detect_target();
1032 }
1033
1034 static int sd1_oneshot_callback(struct timeout *tmo)
1035 {
1036     (void)tmo;
1037
1038     /* This is called only if the state was stable for 300ms - check state
1039      * and post appropriate event. */
1040     if (card_detect_target())
1041     {
1042         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1043     }
1044     else
1045         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1046
1047     return 0;
1048 }
1049
1050 void sd_gpioa_isr(void)
1051 {
1052     static struct timeout sd1_oneshot;
1053     if (GPIOA_MIS & EXT_SD_BITS)
1054         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1055     /* acknowledge interrupt */
1056     GPIOA_IC = EXT_SD_BITS;
1057 }
1058 #endif /* HAVE_HOTSWAP */
1059
1060 #ifdef CONFIG_STORAGE_MULTI
1061 int sd_num_drives(int first_drive)
1062 {
1063     /* We don't care which logical drive number(s) we have been assigned */
1064     (void)first_drive;
1065
1066     return NUM_DRIVES;
1067 }
1068 #endif /* CONFIG_STORAGE_MULTI */