From d04507c4b1022db0a7cde766ba4be74c548ab6c7 Mon Sep 17 00:00:00 2001
From: Anders Kaseorg <andersk@mit.edu>
Date: Mon, 13 Oct 2008 23:11:15 -0400
Subject: [PATCH] [udis86] Add VMLAUNCH, VMREAD, and VMWRITE instructions.

Signed-off-by: Anders Kaseorg <andersk@mit.edu>
---
 kmodsrc/x86/libudis86/opgen.py       |  2 ++
 kmodsrc/x86/libudis86/x86optable.xml | 19 +++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/kmodsrc/x86/libudis86/opgen.py b/kmodsrc/x86/libudis86/opgen.py
index cc190df..6785d98 100755
--- a/kmodsrc/x86/libudis86/opgen.py
+++ b/kmodsrc/x86/libudis86/opgen.py
@@ -59,6 +59,7 @@ operand_dict = {
     "Ew"       : [    "OP_E"        , "SZ_W"     ],
     "Ev"       : [    "OP_E"        , "SZ_V"     ],
     "Ed"       : [    "OP_E"        , "SZ_D"     ],
+    "Eq"       : [    "OP_E"        , "SZ_Q"     ],
     "Ez"       : [    "OP_E"        , "SZ_Z"     ],
     "Ex"       : [    "OP_E"        , "SZ_MDQ"   ],
     "Ep"       : [    "OP_E"        , "SZ_P"     ],
@@ -68,6 +69,7 @@ operand_dict = {
     "Gv"       : [    "OP_G"        , "SZ_V"     ],
     "Gvw"      : [    "OP_G"        , "SZ_MDQ"   ],
     "Gd"       : [    "OP_G"        , "SZ_D"     ],
+    "Gq"       : [    "OP_G"        , "SZ_Q"     ],
     "Gx"       : [    "OP_G"        , "SZ_MDQ"   ],
     "Gz"       : [    "OP_G"        , "SZ_Z"     ],
     "M"        : [    "OP_M"        , "SZ_NA"    ],
diff --git a/kmodsrc/x86/libudis86/x86optable.xml b/kmodsrc/x86/libudis86/x86optable.xml
index 5c3631e..ec5f3b1 100644
--- a/kmodsrc/x86/libudis86/x86optable.xml
+++ b/kmodsrc/x86/libudis86/x86optable.xml
@@ -3001,6 +3001,11 @@
     <vendor> INTEL </vendor>
   </instruction>
 
+  <instruction mnemonic="vmlaunch">
+    <opcode> 0F 01 /0 /mod=11 /rm=2 ; </opcode>
+    <vendor> INTEL </vendor>
+  </instruction>
+
   <instruction mnemonic="vmresume">
     <opcode> 0F 01 /0 /mod=11 /rm=3 ; </opcode>
     <vendor> INTEL </vendor>
@@ -3011,6 +3016,20 @@
     <vendor> INTEL </vendor>
   </instruction>
 
+  <instruction mnemonic="vmread">
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M16 ; Ed Gd </opcode>
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M32 ; Ed Gd </opcode>
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M64 ; Eq Gq </opcode>
+    <vendor> INTEL </vendor>
+  </instruction>
+
+  <instruction mnemonic="vmwrite">
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M16 ; Gd Ed </opcode>
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M32 ; Gd Ed </opcode>
+    <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M64 ; Gq Eq </opcode>
+    <vendor> INTEL </vendor>
+  </instruction>
+
   <instruction mnemonic="vmrun">
     <opcode> 0F 01 /3 /mod=11 /rm=0 ; </opcode>
     <vendor> AMD </vendor>
-- 
2.11.4.GIT