Aarch64 peephole using csinc
commit8918e1db432c884ebab491f9a96226acfe68fb8c
authorSteve Walk <steve.walk@cavium.com>
Wed, 24 May 2017 00:14:08 +0000 (23 17:14 -0700)
committerHhvm Bot <hhvm-bot@users.noreply.github.com>
Wed, 24 May 2017 00:23:45 +0000 (23 17:23 -0700)
treef89bbbf2515c240aa86ac8001bb8a95ddec7fbd0
parent3880b958237d0eaa259c6b6da3c7db6b33d0babf
Aarch64 peephole using csinc

Summary:
This change introduces an Aarch64 specific pseudo instruction which
is a variation of the conditional move.  One pattern seen in the OOPSLA'14
benchmark tests involved the expression  like this in C

    (cond) ? exp : 1;

The hard-coded zero register can be used with the csinc instruction to
create the 1.

Before
======
     0x146010d0  39c0e361             ldrsb w1, [x27, #56]
     0x146010d4  72001c3f             tst w1, #0xff
     0x146010d8  52800022             movz w2, #0x1   //<<---
     0x146010dc  1a810041             csel w1, w2, w1, eq

After
=====
      0x362011d0  38e16b61              ldrsb w1, [x27, x1]
      0x362011d4  72001c3f              tst w1, #0xff
      0x362011d8  1a9f1421              csinc w1, w1, wzr, ne

This saves 1 instruction per instance.

The standard regression suite was run with 6 option sets.  No new regressions
were introduced.
Closes https://github.com/facebook/hhvm/pull/7823

Differential Revision: D5112346

Pulled By: mxw

fbshipit-source-id: 44cebfb34868523c1bda9615cd4605beb34f06ed
hphp/runtime/vm/jit/vasm-arm.cpp
hphp/runtime/vm/jit/vasm-dead.cpp
hphp/runtime/vm/jit/vasm-instr.cpp
hphp/runtime/vm/jit/vasm-instr.h
hphp/runtime/vm/jit/vasm-simplify-arm.cpp
hphp/vixl/a64/macro-assembler-a64.h