| commit | 561ea23da961fde246d64442cb75088dbed13171 | |
| author | Owen Yamauchi <oyamauchi@fb.com> | |
| Wed, 9 Apr 2014 21:34:12 +0000 (9 14:34 -0700) | ||
| committer | Sara Golemon <sgolemon@fb.com> | |
| Fri, 11 Apr 2014 04:49:48 +0000 (10 21:49 -0700) | ||
| tree | c215854f66e8c87cc1a7a94c4c36e6faf616b99e | treesnapshot (tar.gz zip) |
| parent | 0180412c95dfcf6a94a158f0ea2176f8ba106fff | commitdiff |
Factor out ARM reg saving, add SIMD support
This fixes an apparent bug in my last diff and makes life much easier
for my upcoming catch traces diff.
In the case where there are odd number of both SIMD and GP regs to save,
I could have saved space by packing both into the same 16-byte stack
slot, but I didn't because we're going to need to support 16-byte SIMD
registers soon.
Reviewed By: @swtaarrs
Differential Revision: D1268104
This fixes an apparent bug in my last diff and makes life much easier
for my upcoming catch traces diff.
In the case where there are odd number of both SIMD and GP regs to save,
I could have saved space by packing both into the same 16-byte stack
slot, but I didn't because we're going to need to support 16-byte SIMD
registers soon.
Reviewed By: @swtaarrs
Differential Revision: D1268104
| hphp/runtime/vm/jit/code-gen-arm.cpp | diffblobblamehistory |