| commit | 26efdd8ddc8abb06cd650315e87ec56a63100beb | |
| author | Owen Yamauchi <oyamauchi@fb.com> | |
| Tue, 8 Apr 2014 20:46:37 +0000 (8 13:46 -0700) | ||
| committer | Sara Golemon <sgolemon@fb.com> | |
| Wed, 9 Apr 2014 16:42:41 +0000 (9 09:42 -0700) | ||
| tree | fd7368d464df153ce1ab5ef2d468cfd8dba22c45 | treesnapshot (tar.gz zip) |
| parent | 84fa8a4f86fe394507f5f5d9464fc033e2e6ca50 | commitdiff |
Allocate SIMD regs for doubles on ARM
Turns out vixl already had gpr<->simd and simd<->mem instructions for
the uses cases we need. This was just a matter of making the SIMD
registers available to the register allocator and handling them in a few
places in codegen.
We're not allocating SIMD registers to hold Cells yet. vixl has no
support at all for 128-bit-wide SIMD registers, so I'll have to
implement that separately. This diff also doesn't add support for
passing doubles to builtins on ARM; that'll come next.
I also got rid of some now-useless isConst handling from ARM codegen.
Reviewed By: @edwinsmith
Differential Revision: D1262941
Turns out vixl already had gpr<->simd and simd<->mem instructions for
the uses cases we need. This was just a matter of making the SIMD
registers available to the register allocator and handling them in a few
places in codegen.
We're not allocating SIMD registers to hold Cells yet. vixl has no
support at all for 128-bit-wide SIMD registers, so I'll have to
implement that separately. This diff also doesn't add support for
passing doubles to builtins on ARM; that'll come next.
I also got rid of some now-useless isConst handling from ARM codegen.
Reviewed By: @edwinsmith
Differential Revision: D1262941