| commit | 124bc22f2e33238e1d61bb6d9361a50fd47613e7 | |
| author | Jakub Jermar <jakub@jermar.eu> | |
| Thu, 4 Apr 2019 18:08:51 +0000 (4 20:08 +0200) | ||
| committer | Jakub Jermar <jakub@jermar.eu> | |
| Thu, 4 Apr 2019 18:08:51 +0000 (4 20:08 +0200) | ||
| tree | d220ccf82ce753d868cae9d6f89b241e6723f4df | treesnapshot (tar.gz zip) |
| parent | e064102b80157d447412b71a989a3c26c6447a20 | commitdiff |
Reorganize interrupt and IRQ handling on mips32
This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.
This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.