2 * Copyright (C) 2006 Jakub Jermar
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6 * modification, are permitted provided that the following conditions
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29 /** @addtogroup sparc64interrupt
34 * @brief This file contains fast MMU trap handlers.
37 #ifndef KERN_sparc64_MMU_TRAP_H_
38 #define KERN_sparc64_MMU_TRAP_H_
40 #include <arch/stack.h>
41 #include <arch/regdef.h>
42 #include <arch/mm/tlb.h>
43 #include <arch/mm/mmu.h>
44 #include <arch/mm/tte.h>
45 #include <arch/trap/regwin.h>
48 #include <arch/mm/tsb.h>
51 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
52 #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
53 #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
55 #define FAST_MMU_HANDLER_SIZE 128
59 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
61 * First, try to refill TLB from TSB.
64 ldxa
[%g0
] ASI_IMMU
, %g1
! read TSB Tag Target Register
65 ldxa
[%g0
] ASI_IMMU_TSB_8KB_PTR_REG
, %g2
! read TSB
8K Pointer
66 ldda
[%g2
] ASI_NUCLEUS_QUAD_LDD
, %g4
! 16-byte atomic load into
%g4
and %g5
67 cmp
%g1
, %g4
! is
this the entry we are looking
for?
70 stxa
%g5
, [%g0
] ASI_ITLB_DATA_IN_REG
! copy mapping from ITSB to ITLB
75 wrpr
%g0
, PSTATE_PRIV_BIT
| PSTATE_AG_BIT
, %pstate
76 PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
79 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
81 * First, try to refill TLB from TSB.
85 ldxa
[%g0
] ASI_DMMU
, %g1
! read TSB Tag Target Register
86 srlx
%g1
, TSB_TAG_TARGET_CONTEXT_SHIFT
, %g2
! is
this a kernel miss
?
88 ldxa
[%g0
] ASI_DMMU_TSB_8KB_PTR_REG
, %g3
! read TSB
8K Pointer
89 ldda
[%g3
] ASI_NUCLEUS_QUAD_LDD
, %g4
! 16-byte atomic load into
%g4
and %g5
90 cmp
%g1
, %g4
! is
this the entry we are looking
for?
93 stxa
%g5
, [%g0
] ASI_DTLB_DATA_IN_REG
! copy mapping from DTSB to DTLB
98 * Second, test if it is the portion of the kernel address space
99 * which is faulting. If that is the case, immediately create
100 * identity mapping for that page in DTLB. VPN 0 is excluded from
103 * Note that branch-delay slots are used in order to save space.
106 mov VA_DMMU_TAG_ACCESS
, %g1
107 ldxa
[%g1
] ASI_DMMU
, %g1
! read the faulting Context
and VPN
108 set TLB_TAG_ACCESS_CONTEXT_MASK
, %g2
109 andcc
%g1
, %g2
, %g3
! get Context
110 bnz
0f
! Context is non
-zero
111 andncc
%g1
, %g2
, %g3
! get page address into
%g3
112 bz
0f
! page address is zero
114 sethi
%hi(kernel_8k_tlb_data_template
), %g2
115 ldx
[%g2
+ %lo(kernel_8k_tlb_data_template
)], %g2
117 stxa
%g2
, [%g0
] ASI_DTLB_DATA_IN_REG
! identity map the kernel page
121 * Third, catch and handle special cases when the trap is caused by
122 * the userspace register window spill or fill handler. In case
123 * one of these two traps caused this trap, we just lower the trap
124 * level and service the DTLB miss. In the end, we restart
125 * the offending SAVE or RESTORE.
132 wrpr
%g0
, PSTATE_PRIV_BIT
| PSTATE_AG_BIT
, %pstate
133 PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
136 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
138 * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
145 wrpr
%g0
, PSTATE_PRIV_BIT
| PSTATE_AG_BIT
, %pstate
146 PREEMPTIBLE_HANDLER fast_data_access_protection