kernel/arch/mips32/include/cp0.h

   1 /*
   2  * Copyright (c) 2003-2004 Jakub Jermar
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup mips32
  30  * @{
  31  */
  32 /** @file
  33  */
  34
  35 #ifndef KERN_mips32_CP0_H_
  36 #define KERN_mips32_CP0_H_
  37
  38 #include <arch/types.h>
  39 #include <arch/mm/tlb.h>
  40
  41 #define cp0_status_ie_enabled_bit       (1<<0)
  42 #define cp0_status_exl_exception_bit    (1<<1)
  43 #define cp0_status_erl_error_bit        (1<<2)
  44 #define cp0_status_um_bit               (1<<4)
  45 #define cp0_status_bev_bootstrap_bit    (1<<22)
  46 #define cp0_status_fpu_bit              (1<<29)
  47
  48 #define cp0_status_im_shift             8
  49 #define cp0_status_im_mask              0xff00
  50
  51 #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
  52 #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
  53
  54 #define fpu_cop_id 1
  55
  56 /*
  57  * Magic value for use in msim.
  58  */
  59 #define cp0_compare_value               100000
  60
  61 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
  62 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
  63 #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
  64 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
  65
  66 #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
  67   { \
  68       uint32_t retval; \
  69       asm("mfc0 %0, $" #reg : "=r"(retval)); \
  70       return retval; \
  71   }
  72
  73 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
  74  { \
  75     asm("mtc0 %0, $" #reg : : "r"(val) ); \
  76  }
  77
  78 GEN_READ_CP0(index, 0);
  79 GEN_WRITE_CP0(index, 0);
  80
  81 GEN_READ_CP0(random, 1);
  82
  83 GEN_READ_CP0(entry_lo0, 2);
  84 GEN_WRITE_CP0(entry_lo0, 2);
  85
  86 GEN_READ_CP0(entry_lo1, 3);
  87 GEN_WRITE_CP0(entry_lo1, 3);
  88
  89 GEN_READ_CP0(context, 4);
  90 GEN_WRITE_CP0(context, 4);
  91
  92 GEN_READ_CP0(pagemask, 5);
  93 GEN_WRITE_CP0(pagemask, 5);
  94
  95 GEN_READ_CP0(wired, 6);
  96 GEN_WRITE_CP0(wired, 6);
  97
  98 GEN_READ_CP0(badvaddr, 8);
  99
 100 GEN_READ_CP0(count, 9);
 101 GEN_WRITE_CP0(count, 9);
 102
 103 GEN_READ_CP0(entry_hi, 10);
 104 GEN_WRITE_CP0(entry_hi, 10);
 105
 106 GEN_READ_CP0(compare, 11);
 107 GEN_WRITE_CP0(compare, 11);
 108
 109 GEN_READ_CP0(status, 12);
 110 GEN_WRITE_CP0(status, 12);
 111
 112 GEN_READ_CP0(cause, 13);
 113 GEN_WRITE_CP0(cause, 13);
 114
 115 GEN_READ_CP0(epc, 14);
 116 GEN_WRITE_CP0(epc, 14);
 117
 118 GEN_READ_CP0(prid, 15);
 119
 120 #endif
 121
 122 /** @}
 123  */