1 ## General configuration directives
4 @ "amd64" AMD64/Intel EM64T
8 @ "ppc32" PowerPC 32-bit
9 @ "ppc64" PowerPC 64-bit
10 @ "sparc64" Sun UltraSPARC
15 @ "cross" Cross-compiler
17 ! [ARCH=ia32] IA32_COMPILER (choice)
18 % [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER
21 @ "cross" Cross-compiler
23 ! [ARCH=amd64] AMD64_COMPILER (choice)
24 % [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER
27 @ "cross" Cross-compiler
29 ! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice)
30 % [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER
34 @ "pentium4" Pentium 4
35 @ "pentium3" Pentium 3
36 @ "athlon-xp" Athlon XP
37 @ "athlon-mp" Athlon MP
39 ! [ARCH=ia32|ARCH=xen32] IA32_CPU (choice)
42 @ "msim" MSIM Simulator
43 @ "simics" Virtutech Simics simulator
44 @ "lgxemul" GXEmul Little Endian
45 @ "bgxemul" GXEmul Big Endian
47 ! [ARCH=mips32] MIPS_MACHINE (choice)
50 ! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)|(ARCH=xen32)] CONFIG_FB (y/n)
63 ! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice)
79 ! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice)
85 ! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_BPP (choice)
90 ! [ARCH=ia32|ARCH=amd64|ARCH=xen32] CONFIG_SMP (y/n)
92 # Improved support for hyperthreading
93 ! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_SMP=y] CONFIG_HT (y/n)
95 # Simics BIOS AP boot fix
96 ! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
98 # Lazy FPU context switching
99 ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64|ARCH=xen32] CONFIG_FPU_LAZY (y/n)
102 ! [ARCH=ppc32] CONFIG_POWEROFF (n/y)
104 ## Debugging configuration directives
106 # General debuging and assert checking
109 # Deadlock detection support for spinlocks
110 ! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)
112 # Watchpoint on rewriting AS with zero
113 ! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32|ARCH=xen32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n)
115 # Save all interrupt registers
116 ! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32|ARCH=xen32)] CONFIG_DEBUG_ALLREGS (y/n)
119 ! [ARCH=ia64] CONFIG_VHPT (y/n)
121 ## Run-time configuration directives
125 @ "atomic/atomic1" Test of atomic operations.
126 @ "btree/btree1" B-tree test.
127 @ "synch/rwlock1" Read write test 1
128 @ "synch/rwlock2" Read write test 2
129 @ "synch/rwlock3" Read write test 3
130 @ "synch/rwlock4" Read write test 4
131 @ "synch/rwlock5" Read write test 5
132 @ "synch/semaphore1" Semaphore test 1
133 @ "synch/semaphore2" Sempahore test 2
134 @ [ARCH=ia32|ARCH=amd64|ARCH=ia64|ARCH=xen32] "fpu/fpu1" Intel fpu test 1
135 @ [ARCH=ia32|ARCH=amd64|ARCH=xen32] "fpu/sse1" Intel Sse test 1
136 @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1
137 @ "print/print1" Printf test 1
138 @ "thread/thread1" Thread test 1
139 @ "mm/mapping1" Mapping test 1
140 @ "mm/falloc1" Frame Allocation test 1
141 @ "mm/falloc2" Frame Allocation test 2
142 @ "mm/slab1" SLAB test1 - No CPU-cache
143 @ "mm/slab2" SLAB test2 - SMP CPU cache
144 @ "fault/fault1" Write to NULL (maybe page fault)
145 @ "sysinfo" Sysinfo fill and dump test
146 @ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
147 @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test
148 ! CONFIG_TEST (choice)